regress: ruby random tester and hammer stats updates
This commit is contained in:
Brad Beckmann
parent
8c1494112f
commit
697fd8987b
26 changed files with 1739 additions and 1641 deletions
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@ -74,7 +74,7 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
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# create the tester and system, including ruby
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#
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tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
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wakeup_frequency = 10)
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wakeup_frequency = 10, num_cpus = options.num_cpus)
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system = System(tester = tester, physmem = SimpleMemory())
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@ -90,9 +90,12 @@ system.ruby.randomization = True
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for ruby_port in system.ruby._cpu_ruby_ports:
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#
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# Tie the ruby tester ports to the ruby cpu ports
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# Tie the ruby tester ports to the ruby cpu read and write ports
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#
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tester.cpuPort = ruby_port.slave
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if ruby_port.support_data_reqs:
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tester.cpuDataPort = ruby_port.slave
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if ruby_port.support_inst_reqs:
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tester.cpuInstPort = ruby_port.slave
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#
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# Tell the sequencer this is the ruby tester so that it
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@ -1,6 +1,7 @@
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[root]
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type=Root
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children=system
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full_system=false
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time_sync_enable=false
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time_sync_period=100000000
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time_sync_spin_threshold=100000
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@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
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boot_osflags=a
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=timing
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memories=system.physmem system.funcmem
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num_work_ids=16
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physmem=system.physmem
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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@ -19,7 +26,7 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.sys_port_proxy.port[0]
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system_port=system.sys_port_proxy.slave[0]
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[system.cpu0]
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type=MemTest
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@ -34,9 +41,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[0]
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test=system.l1_cntrl0.sequencer.port[0]
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test=system.l1_cntrl0.sequencer.slave[0]
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[system.cpu1]
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type=MemTest
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@ -51,9 +59,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[1]
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test=system.l1_cntrl1.sequencer.port[0]
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test=system.l1_cntrl1.sequencer.slave[0]
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[system.cpu2]
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type=MemTest
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@ -68,9 +77,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[2]
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test=system.l1_cntrl2.sequencer.port[0]
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test=system.l1_cntrl2.sequencer.slave[0]
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[system.cpu3]
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type=MemTest
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@ -85,9 +95,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[3]
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test=system.l1_cntrl3.sequencer.port[0]
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test=system.l1_cntrl3.sequencer.slave[0]
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[system.cpu4]
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type=MemTest
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@ -102,9 +113,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[4]
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test=system.l1_cntrl4.sequencer.port[0]
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test=system.l1_cntrl4.sequencer.slave[0]
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[system.cpu5]
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type=MemTest
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@ -119,9 +131,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[5]
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test=system.l1_cntrl5.sequencer.port[0]
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test=system.l1_cntrl5.sequencer.slave[0]
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[system.cpu6]
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type=MemTest
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@ -136,9 +149,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[6]
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test=system.l1_cntrl6.sequencer.port[0]
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test=system.l1_cntrl6.sequencer.slave[0]
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[system.cpu7]
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type=MemTest
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@ -153,9 +167,10 @@ percent_source_unaligned=50
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percent_uncacheable=0
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progress_interval=10000
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suppress_func_warnings=true
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sys=system
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trace_addr=0
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functional=system.funcmem.port[7]
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test=system.l1_cntrl7.sequencer.port[0]
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test=system.l1_cntrl7.sequencer.slave[0]
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[system.dir_cntrl0]
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type=Directory_Controller
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@ -237,6 +252,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl0.sequencer
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transitions_per_cycle=32
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version=0
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@ -275,13 +291,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu0.test
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slave=system.cpu0.test
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[system.l1_cntrl1]
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type=L1Cache_Controller
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@ -298,6 +315,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl1.sequencer
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transitions_per_cycle=32
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version=1
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@ -336,13 +354,14 @@ dcache=system.l1_cntrl1.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl1.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=1
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physMemPort=system.physmem.port[1]
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port=system.cpu1.test
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slave=system.cpu1.test
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[system.l1_cntrl2]
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type=L1Cache_Controller
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@ -359,6 +378,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl2.sequencer
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transitions_per_cycle=32
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version=2
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@ -397,13 +417,14 @@ dcache=system.l1_cntrl2.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl2.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=2
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physMemPort=system.physmem.port[2]
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port=system.cpu2.test
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slave=system.cpu2.test
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[system.l1_cntrl3]
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type=L1Cache_Controller
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@ -420,6 +441,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl3.sequencer
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transitions_per_cycle=32
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version=3
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@ -458,13 +480,14 @@ dcache=system.l1_cntrl3.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl3.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=3
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physMemPort=system.physmem.port[3]
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port=system.cpu3.test
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slave=system.cpu3.test
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[system.l1_cntrl4]
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type=L1Cache_Controller
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@ -481,6 +504,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl4.sequencer
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transitions_per_cycle=32
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version=4
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@ -519,13 +543,14 @@ dcache=system.l1_cntrl4.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl4.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=4
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physMemPort=system.physmem.port[4]
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port=system.cpu4.test
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slave=system.cpu4.test
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[system.l1_cntrl5]
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type=L1Cache_Controller
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@ -542,6 +567,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl5.sequencer
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transitions_per_cycle=32
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version=5
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@ -580,13 +606,14 @@ dcache=system.l1_cntrl5.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl5.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=5
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physMemPort=system.physmem.port[5]
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port=system.cpu5.test
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slave=system.cpu5.test
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[system.l1_cntrl6]
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type=L1Cache_Controller
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@ -603,6 +630,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl6.sequencer
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transitions_per_cycle=32
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version=6
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@ -641,13 +669,14 @@ dcache=system.l1_cntrl6.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl6.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=6
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physMemPort=system.physmem.port[6]
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port=system.cpu6.test
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slave=system.cpu6.test
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[system.l1_cntrl7]
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type=L1Cache_Controller
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@ -664,6 +693,7 @@ no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl7.sequencer
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transitions_per_cycle=32
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version=7
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@ -702,13 +732,14 @@ dcache=system.l1_cntrl7.L1DcacheMemory
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deadlock_threshold=1000000
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icache=system.l1_cntrl7.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=7
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physMemPort=system.physmem.port[7]
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port=system.cpu7.test
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slave=system.cpu7.test
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[system.physmem]
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type=PhysicalMemory
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@ -718,7 +749,6 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
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[system.ruby]
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type=RubySystem
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@ -963,11 +993,12 @@ ruby_system=system.ruby
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[system.sys_port_proxy]
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type=RubyPortProxy
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access_phys_mem=true
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physmem=system.physmem
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[8]
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port=system.system_port
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slave=system.system_port
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File diff suppressed because it is too large
Load diff
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@ -1,74 +1,74 @@
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system.cpu2: completed 10000 read, 5409 write accesses @1880159
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system.cpu1: completed 10000 read, 5299 write accesses @1882778
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system.cpu3: completed 10000 read, 5366 write accesses @1911159
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system.cpu7: completed 10000 read, 5649 write accesses @1917229
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system.cpu4: completed 10000 read, 5408 write accesses @1931479
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system.cpu0: completed 10000 read, 5286 write accesses @1950089
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system.cpu5: completed 10000 read, 5459 write accesses @1964580
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system.cpu6: completed 10000 read, 5463 write accesses @1972179
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system.cpu7: completed 20000 read, 10897 write accesses @3761849
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system.cpu2: completed 20000 read, 10831 write accesses @3800179
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system.cpu3: completed 20000 read, 10626 write accesses @3825708
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system.cpu4: completed 20000 read, 10811 write accesses @3842889
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system.cpu6: completed 20000 read, 10715 write accesses @3849899
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system.cpu1: completed 20000 read, 10702 write accesses @3854688
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system.cpu0: completed 20000 read, 10477 write accesses @3872776
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system.cpu5: completed 20000 read, 10977 write accesses @3877309
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system.cpu7: completed 30000 read, 16346 write accesses @5687720
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system.cpu2: completed 30000 read, 16162 write accesses @5688839
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system.cpu3: completed 30000 read, 16041 write accesses @5736199
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system.cpu4: completed 30000 read, 16234 write accesses @5749298
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system.cpu1: completed 30000 read, 15966 write accesses @5776163
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system.cpu5: completed 30000 read, 16541 write accesses @5808819
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system.cpu0: completed 30000 read, 15936 write accesses @5814209
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system.cpu6: completed 30000 read, 16131 write accesses @5822319
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system.cpu7: completed 40000 read, 21881 write accesses @7635659
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system.cpu2: completed 40000 read, 21509 write accesses @7644271
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system.cpu4: completed 40000 read, 21826 write accesses @7644629
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system.cpu3: completed 40000 read, 21340 write accesses @7664288
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system.cpu5: completed 40000 read, 21864 write accesses @7689069
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system.cpu1: completed 40000 read, 21331 write accesses @7720199
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system.cpu6: completed 40000 read, 21482 write accesses @7766439
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system.cpu0: completed 40000 read, 21218 write accesses @7770859
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system.cpu2: completed 50000 read, 26843 write accesses @9567509
|
||||
system.cpu4: completed 50000 read, 27341 write accesses @9587739
|
||||
system.cpu7: completed 50000 read, 27298 write accesses @9594538
|
||||
system.cpu5: completed 50000 read, 27297 write accesses @9615250
|
||||
system.cpu3: completed 50000 read, 26951 write accesses @9629869
|
||||
system.cpu1: completed 50000 read, 26588 write accesses @9668459
|
||||
system.cpu6: completed 50000 read, 26930 write accesses @9674989
|
||||
system.cpu0: completed 50000 read, 26761 write accesses @9717328
|
||||
system.cpu2: completed 60000 read, 32089 write accesses @11434469
|
||||
system.cpu4: completed 60000 read, 32753 write accesses @11460881
|
||||
system.cpu5: completed 60000 read, 32638 write accesses @11489388
|
||||
system.cpu7: completed 60000 read, 32763 write accesses @11509798
|
||||
system.cpu3: completed 60000 read, 32313 write accesses @11569698
|
||||
system.cpu0: completed 60000 read, 32096 write accesses @11591548
|
||||
system.cpu6: completed 60000 read, 32349 write accesses @11615831
|
||||
system.cpu1: completed 60000 read, 31983 write accesses @11646079
|
||||
system.cpu2: completed 70000 read, 37474 write accesses @13359218
|
||||
system.cpu4: completed 70000 read, 38151 write accesses @13362099
|
||||
system.cpu5: completed 70000 read, 38045 write accesses @13387329
|
||||
system.cpu7: completed 70000 read, 38043 write accesses @13412879
|
||||
system.cpu0: completed 70000 read, 37368 write accesses @13497038
|
||||
system.cpu3: completed 70000 read, 37733 write accesses @13497379
|
||||
system.cpu6: completed 70000 read, 37699 write accesses @13552039
|
||||
system.cpu1: completed 70000 read, 37272 write accesses @13629039
|
||||
system.cpu5: completed 80000 read, 43265 write accesses @15246808
|
||||
system.cpu4: completed 80000 read, 43470 write accesses @15247621
|
||||
system.cpu2: completed 80000 read, 42926 write accesses @15318609
|
||||
system.cpu7: completed 80000 read, 43420 write accesses @15337379
|
||||
system.cpu3: completed 80000 read, 42961 write accesses @15362279
|
||||
system.cpu0: completed 80000 read, 42538 write accesses @15399778
|
||||
system.cpu6: completed 80000 read, 42992 write accesses @15485249
|
||||
system.cpu1: completed 80000 read, 42648 write accesses @15573879
|
||||
system.cpu4: completed 90000 read, 48820 write accesses @17171059
|
||||
system.cpu5: completed 90000 read, 48731 write accesses @17183141
|
||||
system.cpu7: completed 90000 read, 48795 write accesses @17265336
|
||||
system.cpu2: completed 90000 read, 48519 write accesses @17267129
|
||||
system.cpu3: completed 90000 read, 48352 write accesses @17313919
|
||||
system.cpu0: completed 90000 read, 47888 write accesses @17331279
|
||||
system.cpu6: completed 90000 read, 48438 write accesses @17390512
|
||||
system.cpu1: completed 90000 read, 48044 write accesses @17499359
|
||||
system.cpu5: completed 100000 read, 53983 write accesses @19076439
|
||||
system.cpu4: completed 10000 read, 5428 write accesses @1878499
|
||||
system.cpu2: completed 10000 read, 5257 write accesses @1890969
|
||||
system.cpu1: completed 10000 read, 5405 write accesses @1903259
|
||||
system.cpu0: completed 10000 read, 5442 write accesses @1918699
|
||||
system.cpu6: completed 10000 read, 5402 write accesses @1925379
|
||||
system.cpu5: completed 10000 read, 5453 write accesses @1936119
|
||||
system.cpu3: completed 10000 read, 5383 write accesses @1964689
|
||||
system.cpu7: completed 10000 read, 5477 write accesses @1974002
|
||||
system.cpu1: completed 20000 read, 10638 write accesses @3776021
|
||||
system.cpu2: completed 20000 read, 10480 write accesses @3783438
|
||||
system.cpu4: completed 20000 read, 10796 write accesses @3811601
|
||||
system.cpu0: completed 20000 read, 10807 write accesses @3816738
|
||||
system.cpu5: completed 20000 read, 10791 write accesses @3817028
|
||||
system.cpu6: completed 20000 read, 10880 write accesses @3864408
|
||||
system.cpu3: completed 20000 read, 10699 write accesses @3874782
|
||||
system.cpu7: completed 20000 read, 10804 write accesses @3897609
|
||||
system.cpu1: completed 30000 read, 15945 write accesses @5673660
|
||||
system.cpu2: completed 30000 read, 16019 write accesses @5707989
|
||||
system.cpu5: completed 30000 read, 16239 write accesses @5712028
|
||||
system.cpu0: completed 30000 read, 16267 write accesses @5714869
|
||||
system.cpu4: completed 30000 read, 16131 write accesses @5724848
|
||||
system.cpu6: completed 30000 read, 16235 write accesses @5805664
|
||||
system.cpu7: completed 30000 read, 16267 write accesses @5825319
|
||||
system.cpu3: completed 30000 read, 16142 write accesses @5867180
|
||||
system.cpu1: completed 40000 read, 21307 write accesses @7616560
|
||||
system.cpu5: completed 40000 read, 21585 write accesses @7616688
|
||||
system.cpu4: completed 40000 read, 21599 write accesses @7620249
|
||||
system.cpu2: completed 40000 read, 21389 write accesses @7632909
|
||||
system.cpu0: completed 40000 read, 21615 write accesses @7651849
|
||||
system.cpu6: completed 40000 read, 21564 write accesses @7709298
|
||||
system.cpu7: completed 40000 read, 21695 write accesses @7766209
|
||||
system.cpu3: completed 40000 read, 21615 write accesses @7866019
|
||||
system.cpu1: completed 50000 read, 26737 write accesses @9546228
|
||||
system.cpu0: completed 50000 read, 27083 write accesses @9562439
|
||||
system.cpu4: completed 50000 read, 27042 write accesses @9600931
|
||||
system.cpu5: completed 50000 read, 27029 write accesses @9601568
|
||||
system.cpu2: completed 50000 read, 26802 write accesses @9604629
|
||||
system.cpu6: completed 50000 read, 27075 write accesses @9624249
|
||||
system.cpu7: completed 50000 read, 27192 write accesses @9660438
|
||||
system.cpu3: completed 50000 read, 26887 write accesses @9811479
|
||||
system.cpu0: completed 60000 read, 32415 write accesses @11433179
|
||||
system.cpu1: completed 60000 read, 32076 write accesses @11442279
|
||||
system.cpu2: completed 60000 read, 32076 write accesses @11484389
|
||||
system.cpu5: completed 60000 read, 32515 write accesses @11499209
|
||||
system.cpu6: completed 60000 read, 32430 write accesses @11544838
|
||||
system.cpu7: completed 60000 read, 32529 write accesses @11565479
|
||||
system.cpu4: completed 60000 read, 32327 write accesses @11584140
|
||||
system.cpu3: completed 60000 read, 32340 write accesses @11706229
|
||||
system.cpu0: completed 70000 read, 37881 write accesses @13354669
|
||||
system.cpu1: completed 70000 read, 37501 write accesses @13371519
|
||||
system.cpu2: completed 70000 read, 37457 write accesses @13403638
|
||||
system.cpu5: completed 70000 read, 37825 write accesses @13427069
|
||||
system.cpu7: completed 70000 read, 37852 write accesses @13444129
|
||||
system.cpu6: completed 70000 read, 37717 write accesses @13454949
|
||||
system.cpu4: completed 70000 read, 37625 write accesses @13521929
|
||||
system.cpu3: completed 70000 read, 37731 write accesses @13621498
|
||||
system.cpu0: completed 80000 read, 43203 write accesses @15289219
|
||||
system.cpu5: completed 80000 read, 43091 write accesses @15290788
|
||||
system.cpu1: completed 80000 read, 42753 write accesses @15297039
|
||||
system.cpu6: completed 80000 read, 43000 write accesses @15306258
|
||||
system.cpu2: completed 80000 read, 42737 write accesses @15322288
|
||||
system.cpu7: completed 80000 read, 43196 write accesses @15371808
|
||||
system.cpu4: completed 80000 read, 43033 write accesses @15469939
|
||||
system.cpu3: completed 80000 read, 43097 write accesses @15545999
|
||||
system.cpu6: completed 90000 read, 48319 write accesses @17195251
|
||||
system.cpu0: completed 90000 read, 48512 write accesses @17243339
|
||||
system.cpu1: completed 90000 read, 48287 write accesses @17243789
|
||||
system.cpu2: completed 90000 read, 48214 write accesses @17248379
|
||||
system.cpu5: completed 90000 read, 48605 write accesses @17266969
|
||||
system.cpu7: completed 90000 read, 48606 write accesses @17318949
|
||||
system.cpu4: completed 90000 read, 48454 write accesses @17350499
|
||||
system.cpu3: completed 90000 read, 48532 write accesses @17502609
|
||||
system.cpu6: completed 100000 read, 53736 write accesses @19116079
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 03:42:19
|
||||
gem5 started Jan 23 2012 04:21:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
gem5 compiled Apr 4 2012 12:40:05
|
||||
gem5 started Apr 4 2012 14:27:12
|
||||
gem5 executing on sc2b0605
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19076439 because maximum number of loads reached
|
||||
Exiting @ tick 19116079 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019076 # Number of seconds simulated
|
||||
sim_ticks 19076439 # Number of ticks simulated
|
||||
final_tick 19076439 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.019116 # Number of seconds simulated
|
||||
sim_ticks 19116079 # Number of ticks simulated
|
||||
final_tick 19116079 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 177702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 347220 # Number of bytes of host memory used
|
||||
host_seconds 107.35 # Real time elapsed on the host
|
||||
host_tick_rate 119117 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 363388 # Number of bytes of host memory used
|
||||
host_seconds 160.48 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
@ -19,29 +19,29 @@ system.funcmem.bytes_written 0 # Nu
|
|||
system.funcmem.num_reads 0 # Number of read requests responded to by this memory
|
||||
system.funcmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.funcmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.cpu0.num_reads 99023 # number of read accesses completed
|
||||
system.cpu0.num_writes 52778 # number of write accesses completed
|
||||
system.cpu0.num_reads 99727 # number of read accesses completed
|
||||
system.cpu0.num_writes 53790 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98234 # number of read accesses completed
|
||||
system.cpu1.num_writes 52491 # number of write accesses completed
|
||||
system.cpu1.num_reads 99867 # number of read accesses completed
|
||||
system.cpu1.num_writes 53581 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99317 # number of read accesses completed
|
||||
system.cpu2.num_writes 53653 # number of write accesses completed
|
||||
system.cpu2.num_reads 99786 # number of read accesses completed
|
||||
system.cpu2.num_writes 53525 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99210 # number of read accesses completed
|
||||
system.cpu3.num_writes 53360 # number of write accesses completed
|
||||
system.cpu3.num_reads 98435 # number of read accesses completed
|
||||
system.cpu3.num_writes 53123 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99715 # number of read accesses completed
|
||||
system.cpu4.num_writes 54038 # number of write accesses completed
|
||||
system.cpu4.num_reads 98900 # number of read accesses completed
|
||||
system.cpu4.num_writes 53208 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 100000 # number of read accesses completed
|
||||
system.cpu5.num_writes 53983 # number of write accesses completed
|
||||
system.cpu5.num_reads 99822 # number of read accesses completed
|
||||
system.cpu5.num_writes 53839 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 98915 # number of read accesses completed
|
||||
system.cpu6.num_writes 53129 # number of write accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53736 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99404 # number of read accesses completed
|
||||
system.cpu7.num_writes 53890 # number of write accesses completed
|
||||
system.cpu7.num_reads 99305 # number of read accesses completed
|
||||
system.cpu7.num_writes 53479 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.port[0]
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -116,13 +115,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
|
|||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
|
|
@ -149,14 +149,15 @@ size=512
|
|||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -269,20 +270,23 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.system_port
|
||||
slave=system.system_port
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.l1_cntrl0.sequencer.port[0]
|
||||
cpuDataPort=system.l1_cntrl0.sequencer.slave[0]
|
||||
cpuInstPort=system.l1_cntrl0.sequencer.slave[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -34,28 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Feb/12/2012 15:33:22
|
||||
Real time: Apr/06/2012 15:56:56
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.95
|
||||
Virtual_time_in_minutes: 0.0158333
|
||||
Virtual_time_in_hours: 0.000263889
|
||||
Virtual_time_in_days: 1.09954e-05
|
||||
Virtual_time_in_seconds: 0.56
|
||||
Virtual_time_in_minutes: 0.00933333
|
||||
Virtual_time_in_hours: 0.000155556
|
||||
Virtual_time_in_days: 6.48148e-06
|
||||
|
||||
Ruby_current_time: 366301
|
||||
Ruby_current_time: 349711
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 366301
|
||||
Ruby_cycles: 349711
|
||||
|
||||
mbytes_resident: 0
|
||||
mbytes_total: 0
|
||||
mbytes_resident: 41.7227
|
||||
mbytes_total: 225.164
|
||||
resident_ratio: 0.185334
|
||||
|
||||
ruby_cycles_executed: [ 366302 ]
|
||||
ruby_cycles_executed: [ 349712 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -65,15 +66,15 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1006 average: 15.8469 | standard deviation: 1.1157 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 35 957 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 994 average: 15.841 | standard deviation: 1.12331 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 39 941 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 8679 count: 991 average: 5857.33 | standard deviation: 2249.49 | 58 7 1 1 1 0 3 2 3 1 4 10 1 4 5 6 6 3 1 5 1 4 4 2 2 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 9 3 6 5 11 12 16 25 25 27 21 16 26 37 28 18 27 29 32 30 33 30 43 30 22 35 23 25 22 21 30 11 12 11 21 8 7 8 5 6 8 4 7 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 8181 count: 42 average: 5660.79 | standard deviation: 2406.12 | 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 3 0 3 1 0 0 0 3 1 1 0 1 2 2 0 0 0 2 2 2 2 1 2 0 2 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8679 count: 891 average: 6182.81 | standard deviation: 1925.75 | 53 6 0 0 1 0 2 1 1 0 1 2 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 8 3 6 4 10 9 16 22 24 27 21 16 23 36 27 18 26 27 30 30 33 30 41 28 20 33 22 23 22 19 30 11 11 11 20 8 7 8 5 6 8 4 6 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 16 max: 1864 count: 58 average: 999.586 | standard deviation: 349.911 | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 2 0 1 0 4 1 2 1 0 0 0 0 3 0 0 0 3 0 2 0 1 1 2 1 0 1 3 2 2 0 0 0 1 0 0 0 1 1 0 3 1 0 0 0 1 1 1 1 1 0 1 2 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 64 max: 8679 count: 991 average: 5857.33 | standard deviation: 2249.49 | 58 7 1 1 1 0 3 2 3 1 4 10 1 4 5 6 6 3 1 5 1 4 4 2 2 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 9 3 6 5 11 12 16 25 25 27 21 16 26 37 28 18 27 29 32 30 33 30 43 30 22 35 23 25 22 21 30 11 12 11 21 8 7 8 5 6 8 4 7 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 8736 count: 979 average: 5661.07 | standard deviation: 2367.21 | 72 10 0 0 2 2 5 2 5 4 6 8 4 7 3 2 4 3 2 4 3 1 1 1 0 1 1 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 21 27 27 32 32 32 39 32 43 26 27 28 36 34 35 22 24 33 26 22 19 22 17 14 7 2 16 6 5 11 5 4 3 3 1 2 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 8339 count: 44 average: 6147 | standard deviation: 2036.5 | 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 1 1 1 1 4 4 1 1 3 2 0 2 1 1 0 3 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8736 count: 879 average: 5937.77 | standard deviation: 2125.68 | 69 9 0 0 2 0 3 2 2 0 3 0 1 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 19 25 25 31 31 31 38 28 39 25 26 25 34 34 33 21 23 33 23 21 18 21 17 13 7 2 16 5 5 11 5 3 3 3 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 16 max: 1853 count: 56 average: 936.107 | standard deviation: 353.831 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 2 0 0 0 0 0 1 0 2 0 0 1 1 2 3 0 0 0 2 0 4 2 0 1 1 1 0 4 1 0 1 0 1 1 1 1 0 0 2 2 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 64 max: 8736 count: 979 average: 5661.07 | standard deviation: 2367.21 | 72 10 0 0 2 2 5 2 5 4 6 8 4 7 3 2 4 3 2 4 3 1 1 1 0 1 1 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 21 27 27 32 32 32 39 32 43 26 27 28 36 34 35 22 24 33 26 22 19 22 17 14 7 2 16 6 5 11 5 4 3 3 1 2 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -84,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 64 max: 8181 count: 42 average: 5660.79 | standard deviation: 2406.12 | 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 3 0 3 1 0 0 0 3 1 1 0 1 2 2 0 0 0 2 2 2 2 1 2 0 2 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 64 max: 8679 count: 891 average: 6182.81 | standard deviation: 1925.75 | 53 6 0 0 1 0 2 1 1 0 1 2 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 8 3 6 4 10 9 16 22 24 27 21 16 23 36 27 18 26 27 30 30 33 30 41 28 20 33 22 23 22 19 30 11 11 11 20 8 7 8 5 6 8 4 6 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 16 max: 1864 count: 58 average: 999.586 | standard deviation: 349.911 | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 2 0 1 0 4 1 2 1 0 0 0 0 3 0 0 0 3 0 2 0 1 1 2 1 0 1 3 2 2 0 0 0 1 0 0 0 1 1 0 3 1 0 0 0 1 1 1 1 1 0 1 2 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 64 max: 8339 count: 44 average: 6147 | standard deviation: 2036.5 | 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 1 1 1 1 4 4 1 1 3 2 0 2 1 1 0 3 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 64 max: 8736 count: 879 average: 5937.77 | standard deviation: 2125.68 | 69 9 0 0 2 0 3 2 2 0 3 0 1 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 19 25 25 31 31 31 38 28 39 25 26 25 34 34 33 21 23 33 23 21 18 21 17 13 7 2 16 5 5 11 5 3 3 3 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 16 max: 1853 count: 56 average: 936.107 | standard deviation: 353.831 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 2 0 0 0 0 0 1 0 2 0 0 1 1 2 3 0 0 0 2 0 4 2 0 1 1 1 0 4 1 0 1 0 1 1 1 1 0 0 2 2 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -100,12 +101,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 64 max: 1983 count: 7123 average: 42.2206 | standard deviation: 170.679 | 6474 162 29 70 40 20 46 28 39 41 18 41 16 18 24 9 6 6 11 4 4 5 1 4 1 2 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 12 count: 4572 average: 0.276903 | standard deviation: 0.988226 | 4110 109 134 119 38 30 14 11 2 1 2 0 2 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 64 max: 1983 count: 2551 average: 117.394 | standard deviation: 269.356 | 1902 162 29 70 40 20 46 28 39 41 18 41 16 18 24 9 6 6 11 4 4 5 1 4 1 2 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_delay_cycles: [binsize: 64 max: 1964 count: 6930 average: 44.9837 | standard deviation: 177.937 | 6277 162 19 77 35 23 39 25 31 46 31 47 16 29 20 14 5 2 2 5 1 3 4 7 1 3 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 10 count: 4452 average: 0.269093 | standard deviation: 0.946561 | 4000 119 113 132 37 23 14 8 1 4 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 64 max: 1964 count: 2478 average: 125.318 | standard deviation: 280.209 | 1825 162 19 77 35 23 39 25 31 46 31 47 16 29 20 14 5 2 2 5 1 3 4 7 1 3 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 7 count: 549 average: 0.142077 | standard deviation: 0.713529 | 523 4 7 6 5 3 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 12 count: 4023 average: 0.295302 | standard deviation: 1.01872 | 3587 105 127 113 33 27 14 10 2 1 2 0 2 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 549 average: 0.173042 | standard deviation: 0.84036 | 521 4 3 10 5 4 1 0 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 10 count: 3903 average: 0.282603 | standard deviation: 0.959989 | 3479 115 110 122 32 19 13 8 1 3 1 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -118,158 +119,158 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11904
|
||||
page_reclaims: 11807
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 4
|
||||
block_outputs: 5
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 5469 43752
|
||||
total_msg_count_Control: 5280 42240
|
||||
total_msg_count_Request_Control: 1647 13176
|
||||
total_msg_count_Response_Data: 7878 567216
|
||||
total_msg_count_Response_Control: 8000 64000
|
||||
total_msg_count_Writeback_Data: 3657 263304
|
||||
total_msg_count_Writeback_Control: 93 744
|
||||
total_msgs: 26744 total_bytes: 952192
|
||||
total_msg_count_Response_Data: 7584 546048
|
||||
total_msg_count_Response_Control: 7733 61864
|
||||
total_msg_count_Writeback_Data: 3603 259416
|
||||
total_msg_count_Writeback_Control: 108 864
|
||||
total_msgs: 25955 total_bytes: 923608
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.53514
|
||||
links_utilized_percent_switch_0_link_0: 1.31572 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.75457 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 1.57251
|
||||
links_utilized_percent_switch_0_link_0: 1.33853 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.80649 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 759 6072 [ 0 759 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 926 7408 [ 926 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 926 7408 [ 0 59 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1219 87768 [ 729 490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 740 5920 [ 0 740 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 892 7136 [ 0 52 840 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1201 86472 [ 704 497 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 36 288 [ 36 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.70775
|
||||
links_utilized_percent_switch_1_link_0: 2.97815 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.43734 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.75106
|
||||
links_utilized_percent_switch_1_link_0: 3.03694 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.46518 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 926 7408 [ 926 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1817 14536 [ 0 951 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1219 87768 [ 729 490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 897 7176 [ 897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 861 61992 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1749 13992 [ 0 909 840 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1201 86472 [ 704 497 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 36 288 [ 36 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1729 124488 [ 0 1729 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 849 6792 [ 0 849 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1667 120024 [ 0 1667 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 828 6624 [ 0 828 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.17246
|
||||
links_utilized_percent_switch_2_link_0: 1.12121 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.22372 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.17862
|
||||
links_utilized_percent_switch_2_link_0: 1.12664 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.23059 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 897 7176 [ 897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 803 57816 [ 0 803 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 90 720 [ 0 90 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 892 7136 [ 0 892 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 770 55440 [ 0 770 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 88 704 [ 0 88 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 861 61992 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 858 6864 [ 0 858 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 1.80521
|
||||
links_utilized_percent_switch_3_link_0: 1.31613 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 2.97829 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.12121 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 1.83409
|
||||
links_utilized_percent_switch_3_link_0: 1.33853 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 3.03708 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.12664 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 759 6072 [ 0 759 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 926 7408 [ 926 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1818 14544 [ 0 951 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1219 87768 [ 729 490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 897 7176 [ 897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 803 57816 [ 0 803 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 90 720 [ 0 90 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 740 5920 [ 0 740 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 861 61992 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1750 14000 [ 0 910 840 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1201 86472 [ 704 497 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 36 288 [ 36 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 770 55440 [ 0 770 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 88 704 [ 0 88 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 58
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 58
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 56
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 56
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 58 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 56 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 870
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 870
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 842
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 842
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.13793%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.8621%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.86936%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.1306%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 870 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 842 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [42 ] 42
|
||||
Ifetch [63 ] 63
|
||||
Store [893 ] 893
|
||||
Load [45 ] 45
|
||||
Ifetch [62 ] 62
|
||||
Store [879 ] 879
|
||||
Inv [549 ] 549
|
||||
L1_Replacement [10707 ] 10707
|
||||
L1_Replacement [10481 ] 10481
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [36 ] 36
|
||||
Data_Exclusive [40 ] 40
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [890 ] 890
|
||||
Data_all_Acks [857 ] 857
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [759 ] 759
|
||||
WB_Ack [740 ] 740
|
||||
|
||||
- Transitions -
|
||||
NP Load [36 ] 36
|
||||
NP Ifetch [58 ] 58
|
||||
NP Store [834 ] 834
|
||||
NP Inv [4 ] 4
|
||||
NP Load [41 ] 41
|
||||
NP Ifetch [56 ] 56
|
||||
NP Store [801 ] 801
|
||||
NP Inv [1 ] 1
|
||||
NP L1_Replacement [0 ] 0
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [154 ] 154
|
||||
I L1_Replacement [146 ] 146
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S Inv [32 ] 32
|
||||
S Inv [27 ] 27
|
||||
S L1_Replacement [7 ] 7
|
||||
|
||||
E Load [0 ] 0
|
||||
E Ifetch [0 ] 0
|
||||
E Store [0 ] 0
|
||||
E Inv [4 ] 4
|
||||
E L1_Replacement [32 ] 32
|
||||
E Store [1 ] 1
|
||||
E Inv [2 ] 2
|
||||
E L1_Replacement [36 ] 36
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
M Load [6 ] 6
|
||||
M Load [4 ] 4
|
||||
M Ifetch [0 ] 0
|
||||
M Store [59 ] 59
|
||||
M Inv [101 ] 101
|
||||
M L1_Replacement [730 ] 730
|
||||
M Store [77 ] 77
|
||||
M Inv [97 ] 97
|
||||
M L1_Replacement [704 ] 704
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
|
|
@ -277,19 +278,19 @@ M Fwd_GET_INSTR [0 ] 0
|
|||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [19 ] 19
|
||||
IS L1_Replacement [418 ] 418
|
||||
IS Data_Exclusive [36 ] 36
|
||||
IS Inv [22 ] 22
|
||||
IS L1_Replacement [508 ] 508
|
||||
IS Data_Exclusive [40 ] 40
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [39 ] 39
|
||||
IS Data_all_Acks [34 ] 34
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [9366 ] 9366
|
||||
IM L1_Replacement [9080 ] 9080
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [832 ] 832
|
||||
IM Data_all_Acks [801 ] 801
|
||||
IM Ack [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
|
|
@ -307,95 +308,95 @@ IS_I Inv [0 ] 0
|
|||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [19 ] 19
|
||||
IS_I Data_all_Acks [22 ] 22
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [5 ] 5
|
||||
M_I Ifetch [6 ] 6
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [389 ] 389
|
||||
M_I Inv [400 ] 400
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [371 ] 371
|
||||
M_I WB_Ack [340 ] 340
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 ] 0
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [388 ] 388
|
||||
SINK_WB_ACK WB_Ack [400 ] 400
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 897
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 897
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 862
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 862
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.01338%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.13155%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.8551%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.75638%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 5.80046%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4432%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 897 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 862 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [58 ] 58
|
||||
L1_GETS [36 ] 36
|
||||
L1_GETX [832 ] 832
|
||||
L1_GET_INSTR [56 ] 56
|
||||
L1_GETS [41 ] 41
|
||||
L1_GETX [801 ] 801
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [377 ] 377
|
||||
L1_PUTX [349 ] 349
|
||||
L1_PUTX_old [757 ] 757
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [331 ] 331
|
||||
L2_Replacement_clean [1184 ] 1184
|
||||
Mem_Data [897 ] 897
|
||||
Mem_Ack [892 ] 892
|
||||
WB_Data [472 ] 472
|
||||
WB_Data_clean [18 ] 18
|
||||
L2_Replacement [297 ] 297
|
||||
L2_Replacement_clean [1183 ] 1183
|
||||
Mem_Data [861 ] 861
|
||||
Mem_Ack [856 ] 856
|
||||
WB_Data [473 ] 473
|
||||
WB_Data_clean [24 ] 24
|
||||
Ack [0 ] 0
|
||||
Ack_all [59 ] 59
|
||||
Ack_all [52 ] 52
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [866 ] 866
|
||||
Exclusive_Unblock [840 ] 840
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [55 ] 55
|
||||
NP L1_GETS [36 ] 36
|
||||
NP L1_GETX [806 ] 806
|
||||
NP L1_GET_INSTR [50 ] 50
|
||||
NP L1_GETS [41 ] 41
|
||||
NP L1_GETX [771 ] 771
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [259 ] 259
|
||||
NP L1_PUTX_old [264 ] 264
|
||||
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [3 ] 3
|
||||
SS L1_GETX [6 ] 6
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [55 ] 55
|
||||
SS L2_Replacement_clean [50 ] 50
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [3 ] 3
|
||||
M L1_GET_INSTR [6 ] 6
|
||||
M L1_GETS [0 ] 0
|
||||
M L1_GETX [23 ] 23
|
||||
M L1_GETX [24 ] 24
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [331 ] 331
|
||||
M L2_Replacement_clean [13 ] 13
|
||||
M L2_Replacement [297 ] 297
|
||||
M L2_Replacement_clean [12 ] 12
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [371 ] 371
|
||||
MT L1_PUTX [340 ] 340
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L2_Replacement_clean [494 ] 494
|
||||
MT L2_Replacement_clean [499 ] 499
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -403,8 +404,8 @@ M_I L1_GETS [0 ] 0
|
|||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [129 ] 129
|
||||
M_I Mem_Ack [892 ] 892
|
||||
M_I L1_PUTX_old [136 ] 136
|
||||
M_I Mem_Ack [856 ] 856
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -423,10 +424,10 @@ MCT_I L1_GETS [0 ] 0
|
|||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [176 ] 176
|
||||
MCT_I WB_Data [472 ] 472
|
||||
MCT_I WB_Data_clean [18 ] 18
|
||||
MCT_I Ack_all [4 ] 4
|
||||
MCT_I L1_PUTX_old [181 ] 181
|
||||
MCT_I WB_Data [473 ] 473
|
||||
MCT_I WB_Data_clean [24 ] 24
|
||||
MCT_I Ack_all [2 ] 2
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
|
|
@ -435,7 +436,7 @@ I_I L1_UPGRADE [0 ] 0
|
|||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [55 ] 55
|
||||
I_I Ack_all [50 ] 50
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
|
|
@ -453,8 +454,8 @@ ISS L1_GETX [0 ] 0
|
|||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [3 ] 3
|
||||
ISS Mem_Data [36 ] 36
|
||||
ISS L2_Replacement_clean [14 ] 14
|
||||
ISS Mem_Data [40 ] 40
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -464,7 +465,7 @@ IS L1_PUTX [0 ] 0
|
|||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [69 ] 69
|
||||
IS Mem_Data [55 ] 55
|
||||
IS Mem_Data [50 ] 50
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -473,8 +474,8 @@ IM L1_GETX [0 ] 0
|
|||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [231 ] 231
|
||||
IM Mem_Data [806 ] 806
|
||||
IM L2_Replacement_clean [225 ] 225
|
||||
IM Mem_Data [771 ] 771
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -486,19 +487,19 @@ SS_MB L1_PUTX_old [0 ] 0
|
|||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [3 ] 3
|
||||
SS_MB Exclusive_Unblock [6 ] 6
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [6 ] 6
|
||||
MT_MB L1_PUTX_old [193 ] 193
|
||||
MT_MB L1_PUTX [9 ] 9
|
||||
MT_MB L1_PUTX_old [176 ] 176
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [319 ] 319
|
||||
MT_MB L2_Replacement_clean [314 ] 314
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [863 ] 863
|
||||
MT_MB Exclusive_Unblock [834 ] 834
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -550,37 +551,37 @@ MT_SB Unblock [0 ] 0
|
|||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1700
|
||||
memory_reads: 897
|
||||
memory_writes: 802
|
||||
memory_refreshes: 763
|
||||
memory_total_request_delays: 1143
|
||||
memory_delays_per_request: 0.672353
|
||||
memory_delays_in_input_queue: 158
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 983
|
||||
memory_stalls_for_bank_busy: 180
|
||||
memory_total_requests: 1632
|
||||
memory_reads: 861
|
||||
memory_writes: 770
|
||||
memory_refreshes: 729
|
||||
memory_total_request_delays: 1043
|
||||
memory_delays_per_request: 0.639093
|
||||
memory_delays_in_input_queue: 147
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 896
|
||||
memory_stalls_for_bank_busy: 170
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 84
|
||||
memory_stalls_for_bus: 390
|
||||
memory_stalls_for_arbitration: 70
|
||||
memory_stalls_for_bus: 355
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 247
|
||||
memory_stalls_for_read_read_turnaround: 82
|
||||
accesses_per_bank: 52 56 61 98 64 67 64 53 45 52 56 48 55 35 40 46 42 46 59 50 52 46 56 44 56 57 52 59 52 58 40 39
|
||||
memory_stalls_for_read_write_turnaround: 230
|
||||
memory_stalls_for_read_read_turnaround: 71
|
||||
accesses_per_bank: 59 40 48 77 75 69 65 47 55 56 48 54 65 48 34 60 44 35 56 37 49 41 46 49 50 48 50 47 58 40 41 41
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [897 ] 897
|
||||
Data [803 ] 803
|
||||
Memory_Data [897 ] 897
|
||||
Memory_Ack [802 ] 802
|
||||
Fetch [862 ] 862
|
||||
Data [770 ] 770
|
||||
Memory_Data [861 ] 861
|
||||
Memory_Ack [770 ] 770
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [90 ] 90
|
||||
CleanReplacement [88 ] 88
|
||||
|
||||
- Transitions -
|
||||
I Fetch [897 ] 897
|
||||
I Fetch [862 ] 862
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -596,20 +597,20 @@ ID_W Memory_Ack [0 ] 0
|
|||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [803 ] 803
|
||||
M Data [770 ] 770
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [90 ] 90
|
||||
M CleanReplacement [88 ] 88
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [897 ] 897
|
||||
IM Memory_Data [861 ] 861
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [802 ] 802
|
||||
MI Memory_Ack [770 ] 770
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 15:33:08
|
||||
gem5 started Feb 12 2012 15:33:21
|
||||
gem5 executing on Alis-MacBook-Pro.local
|
||||
gem5 compiled Apr 6 2012 15:45:29
|
||||
gem5 started Apr 6 2012 15:56:56
|
||||
gem5 executing on sc2b0605
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
print getting inst port 0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 366301 because Ruby Tester completed
|
||||
Exiting @ tick 349711 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000366 # Number of seconds simulated
|
||||
sim_ticks 366301 # Number of ticks simulated
|
||||
final_tick 366301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000350 # Number of seconds simulated
|
||||
sim_ticks 349711 # Number of ticks simulated
|
||||
final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 728650 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266424 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 1593950 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230572 # Number of bytes of host memory used
|
||||
host_seconds 0.22 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
|
@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
|
|||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.port[0]
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -76,6 +82,7 @@ number_of_TBEs=256
|
|||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -105,13 +112,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
|
|||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
|
|
@ -137,14 +145,15 @@ size=512
|
|||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -257,19 +266,23 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.system_port
|
||||
slave=system.system_port
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.l1_cntrl0.sequencer.port[0]
|
||||
cpuDataPort=system.l1_cntrl0.sequencer.slave[0]
|
||||
cpuInstPort=system.l1_cntrl0.sequencer.slave[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/23/2012 04:22:16
|
||||
Real time: Apr/06/2012 15:57:36
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.62
|
||||
Virtual_time_in_minutes: 0.0103333
|
||||
Virtual_time_in_hours: 0.000172222
|
||||
Virtual_time_in_days: 7.17593e-06
|
||||
Virtual_time_in_seconds: 1.05
|
||||
Virtual_time_in_minutes: 0.0175
|
||||
Virtual_time_in_hours: 0.000291667
|
||||
Virtual_time_in_days: 1.21528e-05
|
||||
|
||||
Ruby_current_time: 371241
|
||||
Ruby_current_time: 357561
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 371241
|
||||
Ruby_cycles: 357561
|
||||
|
||||
mbytes_resident: 39.6328
|
||||
mbytes_total: 209.516
|
||||
resident_ratio: 0.189164
|
||||
mbytes_resident: 41.7969
|
||||
mbytes_total: 225.496
|
||||
resident_ratio: 0.18539
|
||||
|
||||
ruby_cycles_executed: [ 371242 ]
|
||||
ruby_cycles_executed: [ 357562 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L2Cache-0:0
|
||||
|
|
@ -66,15 +66,15 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 993 average: 15.8197 | standard deviation: 1.13014 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 60 919 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 959 average: 15.8321 | standard deviation: 1.14411 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 42 903 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 41885 count: 980 average: 5911.29 | standard deviation: 9158.49 | 92 27 107 116 84 56 57 54 23 16 22 11 13 12 11 6 8 7 8 3 3 6 5 4 5 3 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 1 4 4 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 6 1 6 2 4 3 2 1 1 2 2 3 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 256 max: 28410 count: 50 average: 3572.56 | standard deviation: 6675.9 | 5 1 7 5 3 6 7 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 256 max: 41885 count: 880 average: 6339.85 | standard deviation: 9428.49 | 84 21 77 99 75 49 50 49 23 15 21 11 13 12 11 5 7 7 8 3 3 6 5 4 4 2 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 0 4 3 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 5 1 6 2 4 3 2 1 1 2 1 2 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1453 count: 50 average: 707.26 | standard deviation: 269.766 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 2 1 1 0 0 0 1 0 1 0 1 0 4 2 1 0 1 0 1 0 1 1 0 0 0 0 2 0 1 2 0 0 0 0 0 0 0 0 2 1 0 1 1 0 1 0 0 3 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 256 max: 41885 count: 980 average: 5911.29 | standard deviation: 9158.49 | 92 27 107 116 84 56 57 54 23 16 22 11 13 12 11 6 8 7 8 3 3 6 5 4 5 3 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 1 4 4 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 6 1 6 2 4 3 2 1 1 2 2 3 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 256 max: 35755 count: 944 average: 5943.47 | standard deviation: 8648.87 | 80 45 92 101 84 54 37 40 29 42 18 14 12 10 11 11 4 10 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 5 2 1 1 4 1 8 4 3 6 6 6 2 4 10 4 6 2 5 3 3 3 1 4 5 3 3 4 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 1 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 256 max: 32625 count: 44 average: 6010.95 | standard deviation: 9060.42 | 5 4 0 9 2 5 2 0 2 2 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 256 max: 35755 count: 844 average: 6286.24 | standard deviation: 8806.66 | 73 32 69 78 75 48 35 40 27 40 18 13 12 10 11 11 4 8 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 4 2 1 1 4 1 8 3 3 5 6 6 2 4 9 4 6 2 4 3 2 2 1 4 5 3 3 2 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1342 count: 56 average: 724.5 | standard deviation: 266.653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 1 1 0 0 0 0 2 2 4 1 0 0 1 1 0 0 1 1 0 0 2 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_NULL: [binsize: 256 max: 35755 count: 944 average: 5943.47 | standard deviation: 8648.87 | 80 45 92 101 84 54 37 40 29 42 18 14 12 10 11 11 4 10 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 5 2 1 1 4 1 8 4 3 6 6 6 2 4 10 4 6 2 5 3 3 3 1 4 5 3 3 4 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 1 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 256 max: 28410 count: 50 average: 3572.56 | standard deviation: 6675.9 | 5 1 7 5 3 6 7 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 256 max: 41885 count: 880 average: 6339.85 | standard deviation: 9428.49 | 84 21 77 99 75 49 50 49 23 15 21 11 13 12 11 5 7 7 8 3 3 6 5 4 4 2 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 0 4 3 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 5 1 6 2 4 3 2 1 1 2 1 2 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 8 max: 1453 count: 50 average: 707.26 | standard deviation: 269.766 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 2 1 1 0 0 0 1 0 1 0 1 0 4 2 1 0 1 0 1 0 1 1 0 0 0 0 2 0 1 2 0 0 0 0 0 0 0 0 2 1 0 1 1 0 1 0 0 3 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 256 max: 32625 count: 44 average: 6010.95 | standard deviation: 9060.42 | 5 4 0 9 2 5 2 0 2 2 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 256 max: 35755 count: 844 average: 6286.24 | standard deviation: 8806.66 | 73 32 69 78 75 48 35 40 27 40 18 13 12 10 11 11 4 8 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 4 2 1 1 4 1 8 3 3 5 6 6 2 4 9 4 6 2 4 3 2 2 1 4 5 3 3 2 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 8 max: 1342 count: 56 average: 724.5 | standard deviation: 266.653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 1 1 0 0 0 0 2 2 4 1 0 0 1 1 0 0 1 1 0 0 2 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -119,87 +119,87 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10451
|
||||
page_reclaims: 11804
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 80
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 5209 41672
|
||||
total_msg_count_Response_Data: 5058 364176
|
||||
total_msg_count_ResponseL2hit_Data: 150 10800
|
||||
total_msg_count_Writeback_Data: 4929 354888
|
||||
total_msg_count_Writeback_Control: 10567 84536
|
||||
total_msg_count_Unblock_Control: 5193 41544
|
||||
total_msgs: 31106 total_bytes: 897616
|
||||
total_msg_count_Request_Control: 5082 40656
|
||||
total_msg_count_Response_Data: 4932 355104
|
||||
total_msg_count_ResponseL2hit_Data: 138 9936
|
||||
total_msg_count_Writeback_Data: 4785 344520
|
||||
total_msg_count_Writeback_Control: 10307 82456
|
||||
total_msg_count_Unblock_Control: 5058 40464
|
||||
total_msgs: 30302 total_bytes: 873136
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.51865
|
||||
links_utilized_percent_switch_0_link_0: 2.57016 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.46713 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.54369
|
||||
links_utilized_percent_switch_0_link_0: 2.59676 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.49062 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1721 13768 [ 888 833 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 1802 14416 [ 888 836 78 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 870 6960 [ 870 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 862 62064 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1678 13424 [ 865 813 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Unblock_Control: 866 6928 [ 0 0 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 824 6592 [ 0 824 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 733 52776 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 1758 14064 [ 865 813 80 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 820 6560 [ 0 0 820 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.31922
|
||||
links_utilized_percent_switch_1_link_0: 1.20205 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.4364 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 1.33089
|
||||
links_utilized_percent_switch_1_link_0: 1.21322 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.44856 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 888 7104 [ 888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 894 7152 [ 894 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 889 7112 [ 889 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 864 6912 [ 864 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 870 6960 [ 870 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 862 62064 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 865 6920 [ 865 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Unblock_Control: 866 6928 [ 0 0 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.19949
|
||||
links_utilized_percent_switch_2_link_0: 1.26481 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.13417 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.21273
|
||||
links_utilized_percent_switch_2_link_0: 1.27726 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.1482 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 912 7296 [ 0 834 78 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 834 6672 [ 0 834 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 824 6592 [ 0 824 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 733 52776 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 893 7144 [ 0 813 80 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Unblock_Control: 820 6560 [ 0 0 820 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 813 6504 [ 0 813 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 1.67901
|
||||
links_utilized_percent_switch_3_link_0: 2.57016 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.20205 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.26481 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 1.69579
|
||||
links_utilized_percent_switch_3_link_0: 2.59676 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.21336 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.27726 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 1721 13768 [ 888 833 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 888 7104 [ 888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 912 7296 [ 0 834 78 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 870 6960 [ 870 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 862 62064 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 1678 13424 [ 865 813 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Unblock_Control: 866 6928 [ 0 0 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 865 6920 [ 865 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 824 6592 [ 0 824 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 733 52776 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 893 7144 [ 0 813 80 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 820 6560 [ 0 0 820 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
|
|
@ -219,10 +219,10 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50 ] 50
|
||||
Ifetch [304 ] 304
|
||||
Store [970 ] 970
|
||||
L1_Replacement [527165 ] 527165
|
||||
Load [47 ] 47
|
||||
Ifetch [318 ] 318
|
||||
Store [964 ] 964
|
||||
L1_Replacement [506921 ] 506921
|
||||
Own_GETX [0 ] 0
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
|
|
@ -230,17 +230,17 @@ Fwd_DMA [0 ] 0
|
|||
Inv [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [893 ] 893
|
||||
Exclusive_Data [868 ] 868
|
||||
Writeback_Ack [0 ] 0
|
||||
Writeback_Ack_Data [888 ] 888
|
||||
Writeback_Ack_Data [864 ] 864
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [799 ] 799
|
||||
Use_Timeout [890 ] 890
|
||||
All_acks [772 ] 772
|
||||
Use_Timeout [866 ] 866
|
||||
|
||||
- Transitions -
|
||||
I Load [45 ] 45
|
||||
I Ifetch [49 ] 49
|
||||
I Store [800 ] 800
|
||||
I Load [41 ] 41
|
||||
I Ifetch [56 ] 56
|
||||
I Store [773 ] 773
|
||||
I L1_Replacement [0 ] 0
|
||||
I Inv [0 ] 0
|
||||
|
||||
|
|
@ -261,51 +261,51 @@ O Fwd_GETS [0 ] 0
|
|||
O Fwd_DMA [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Ifetch [0 ] 0
|
||||
M Store [0 ] 0
|
||||
M L1_Replacement [91 ] 91
|
||||
M L1_Replacement [94 ] 94
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_DMA [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Load [1 ] 1
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L1_Replacement [1727 ] 1727
|
||||
M_W L1_Replacement [1321 ] 1321
|
||||
M_W Own_GETX [0 ] 0
|
||||
M_W Fwd_GETX [0 ] 0
|
||||
M_W Fwd_GETS [0 ] 0
|
||||
M_W Fwd_DMA [0 ] 0
|
||||
M_W Inv [0 ] 0
|
||||
M_W Use_Timeout [92 ] 92
|
||||
M_W Use_Timeout [94 ] 94
|
||||
|
||||
MM Load [5 ] 5
|
||||
MM Load [2 ] 2
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [70 ] 70
|
||||
MM L1_Replacement [798 ] 798
|
||||
MM Store [66 ] 66
|
||||
MM L1_Replacement [771 ] 771
|
||||
MM Fwd_GETX [0 ] 0
|
||||
MM Fwd_GETS [0 ] 0
|
||||
MM Fwd_DMA [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [11 ] 11
|
||||
MM_W L1_Replacement [29093 ] 29093
|
||||
MM_W Store [6 ] 6
|
||||
MM_W L1_Replacement [28136 ] 28136
|
||||
MM_W Own_GETX [0 ] 0
|
||||
MM_W Fwd_GETX [0 ] 0
|
||||
MM_W Fwd_GETS [0 ] 0
|
||||
MM_W Fwd_DMA [0 ] 0
|
||||
MM_W Inv [0 ] 0
|
||||
MM_W Use_Timeout [798 ] 798
|
||||
MM_W Use_Timeout [772 ] 772
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L1_Replacement [453807 ] 453807
|
||||
IM L1_Replacement [439219 ] 439219
|
||||
IM Inv [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [799 ] 799
|
||||
IM Exclusive_Data [772 ] 772
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
|
|
@ -321,21 +321,21 @@ SM Exclusive_Data [0 ] 0
|
|||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM L1_Replacement [14583 ] 14583
|
||||
OM L1_Replacement [14936 ] 14936
|
||||
OM Own_GETX [0 ] 0
|
||||
OM Fwd_GETX [0 ] 0
|
||||
OM Fwd_GETS [0 ] 0
|
||||
OM Fwd_DMA [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [799 ] 799
|
||||
OM All_acks [772 ] 772
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L1_Replacement [27066 ] 27066
|
||||
IS L1_Replacement [22444 ] 22444
|
||||
IS Inv [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Exclusive_Data [94 ] 94
|
||||
IS Exclusive_Data [96 ] 96
|
||||
|
||||
SI Load [0 ] 0
|
||||
SI Ifetch [0 ] 0
|
||||
|
|
@ -359,15 +359,15 @@ OI Writeback_Ack [0 ] 0
|
|||
OI Writeback_Ack_Data [0 ] 0
|
||||
OI Writeback_Nack [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [254 ] 254
|
||||
MI Store [89 ] 89
|
||||
MI Load [2 ] 2
|
||||
MI Ifetch [262 ] 262
|
||||
MI Store [119 ] 119
|
||||
MI L1_Replacement [0 ] 0
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Fwd_GETS [0 ] 0
|
||||
MI Fwd_DMA [0 ] 0
|
||||
MI Writeback_Ack [0 ] 0
|
||||
MI Writeback_Ack_Data [888 ] 888
|
||||
MI Writeback_Ack_Data [864 ] 864
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
|
|
@ -389,10 +389,10 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [157 ] 157
|
||||
L1_GETX [842 ] 842
|
||||
L1_GETS [127 ] 127
|
||||
L1_GETX [839 ] 839
|
||||
L1_PUTO [0 ] 0
|
||||
L1_PUTX [2111 ] 2111
|
||||
L1_PUTX [2005 ] 2005
|
||||
L1_PUTS_only [0 ] 0
|
||||
L1_PUTS [0 ] 0
|
||||
Fwd_GETX [0 ] 0
|
||||
|
|
@ -402,21 +402,21 @@ Own_GETX [0 ] 0
|
|||
Inv [0 ] 0
|
||||
IntAck [0 ] 0
|
||||
ExtAck [0 ] 0
|
||||
All_Acks [759 ] 759
|
||||
Data [759 ] 759
|
||||
Data_Exclusive [84 ] 84
|
||||
L1_WBCLEANDATA [82 ] 82
|
||||
L1_WBDIRTYDATA [806 ] 806
|
||||
Writeback_Ack [833 ] 833
|
||||
All_Acks [736 ] 736
|
||||
Data [736 ] 736
|
||||
Data_Exclusive [86 ] 86
|
||||
L1_WBCLEANDATA [84 ] 84
|
||||
L1_WBDIRTYDATA [778 ] 778
|
||||
Writeback_Ack [813 ] 813
|
||||
Writeback_Nack [0 ] 0
|
||||
Unblock [0 ] 0
|
||||
Exclusive_Unblock [890 ] 890
|
||||
Exclusive_Unblock [866 ] 866
|
||||
DmaAck [0 ] 0
|
||||
L2_Replacement [836 ] 836
|
||||
L2_Replacement [814 ] 814
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [84 ] 84
|
||||
NP L1_GETX [759 ] 759
|
||||
NP L1_GETS [87 ] 87
|
||||
NP L1_GETX [737 ] 737
|
||||
NP L1_PUTO [0 ] 0
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTS [0 ] 0
|
||||
|
|
@ -442,7 +442,7 @@ ILS L2_Replacement [0 ] 0
|
|||
ILX L1_GETS [0 ] 0
|
||||
ILX L1_GETX [0 ] 0
|
||||
ILX L1_PUTO [0 ] 0
|
||||
ILX L1_PUTX [888 ] 888
|
||||
ILX L1_PUTX [865 ] 865
|
||||
ILX L1_PUTS_only [0 ] 0
|
||||
ILX L1_PUTS [0 ] 0
|
||||
ILX Fwd_GETX [0 ] 0
|
||||
|
|
@ -542,14 +542,14 @@ SLS Inv [0 ] 0
|
|||
SLS L2_Replacement [0 ] 0
|
||||
|
||||
M L1_GETS [10 ] 10
|
||||
M L1_GETX [40 ] 40
|
||||
M L1_GETX [36 ] 36
|
||||
M L1_PUTO [0 ] 0
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTS [0 ] 0
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_DMA [0 ] 0
|
||||
M L2_Replacement [836 ] 836
|
||||
M L2_Replacement [813 ] 813
|
||||
|
||||
IFGX L1_GETS [0 ] 0
|
||||
IFGX L1_GETX [0 ] 0
|
||||
|
|
@ -798,8 +798,8 @@ OLSXW Inv [0 ] 0
|
|||
OLSXW Unblock [0 ] 0
|
||||
OLSXW L2_Replacement [0 ] 0
|
||||
|
||||
ILXW L1_GETS [63 ] 63
|
||||
ILXW L1_GETX [23 ] 23
|
||||
ILXW L1_GETS [30 ] 30
|
||||
ILXW L1_GETX [31 ] 31
|
||||
ILXW L1_PUTO [0 ] 0
|
||||
ILXW L1_PUTX [0 ] 0
|
||||
ILXW L1_PUTS_only [0 ] 0
|
||||
|
|
@ -809,8 +809,8 @@ ILXW Fwd_GETS [0 ] 0
|
|||
ILXW Fwd_DMA [0 ] 0
|
||||
ILXW Inv [0 ] 0
|
||||
ILXW Data [0 ] 0
|
||||
ILXW L1_WBCLEANDATA [82 ] 82
|
||||
ILXW L1_WBDIRTYDATA [806 ] 806
|
||||
ILXW L1_WBCLEANDATA [84 ] 84
|
||||
ILXW L1_WBDIRTYDATA [778 ] 778
|
||||
ILXW Unblock [0 ] 0
|
||||
ILXW L2_Replacement [0 ] 0
|
||||
|
||||
|
|
@ -898,7 +898,7 @@ IFLXO L2_Replacement [0 ] 0
|
|||
IGS L1_GETS [0 ] 0
|
||||
IGS L1_GETX [0 ] 0
|
||||
IGS L1_PUTO [0 ] 0
|
||||
IGS L1_PUTX [99 ] 99
|
||||
IGS L1_PUTX [87 ] 87
|
||||
IGS L1_PUTS_only [0 ] 0
|
||||
IGS L1_PUTS [0 ] 0
|
||||
IGS Fwd_GETX [0 ] 0
|
||||
|
|
@ -907,9 +907,9 @@ IGS Fwd_DMA [0 ] 0
|
|||
IGS Own_GETX [0 ] 0
|
||||
IGS Inv [0 ] 0
|
||||
IGS Data [0 ] 0
|
||||
IGS Data_Exclusive [84 ] 84
|
||||
IGS Data_Exclusive [86 ] 86
|
||||
IGS Unblock [0 ] 0
|
||||
IGS Exclusive_Unblock [83 ] 83
|
||||
IGS Exclusive_Unblock [84 ] 84
|
||||
IGS L2_Replacement [0 ] 0
|
||||
|
||||
IGM L1_GETS [0 ] 0
|
||||
|
|
@ -924,7 +924,7 @@ IGM Fwd_DMA [0 ] 0
|
|||
IGM Own_GETX [0 ] 0
|
||||
IGM Inv [0 ] 0
|
||||
IGM ExtAck [0 ] 0
|
||||
IGM Data [759 ] 759
|
||||
IGM Data [736 ] 736
|
||||
IGM Data_Exclusive [0 ] 0
|
||||
IGM L2_Replacement [0 ] 0
|
||||
|
||||
|
|
@ -945,7 +945,7 @@ IGMLS L2_Replacement [0 ] 0
|
|||
IGMO L1_GETS [0 ] 0
|
||||
IGMO L1_GETX [0 ] 0
|
||||
IGMO L1_PUTO [0 ] 0
|
||||
IGMO L1_PUTX [1113 ] 1113
|
||||
IGMO L1_PUTX [1037 ] 1037
|
||||
IGMO L1_PUTS_only [0 ] 0
|
||||
IGMO L1_PUTS [0 ] 0
|
||||
IGMO Fwd_GETX [0 ] 0
|
||||
|
|
@ -953,8 +953,8 @@ IGMO Fwd_GETS [0 ] 0
|
|||
IGMO Fwd_DMA [0 ] 0
|
||||
IGMO Own_GETX [0 ] 0
|
||||
IGMO ExtAck [0 ] 0
|
||||
IGMO All_Acks [759 ] 759
|
||||
IGMO Exclusive_Unblock [758 ] 758
|
||||
IGMO All_Acks [736 ] 736
|
||||
IGMO Exclusive_Unblock [736 ] 736
|
||||
IGMO L2_Replacement [0 ] 0
|
||||
|
||||
IGMIO L1_GETS [0 ] 0
|
||||
|
|
@ -1027,14 +1027,14 @@ II All_Acks [0 ] 0
|
|||
MM L1_GETS [0 ] 0
|
||||
MM L1_GETX [0 ] 0
|
||||
MM L1_PUTO [0 ] 0
|
||||
MM L1_PUTX [11 ] 11
|
||||
MM L1_PUTX [0 ] 0
|
||||
MM L1_PUTS_only [0 ] 0
|
||||
MM L1_PUTS [0 ] 0
|
||||
MM Fwd_GETX [0 ] 0
|
||||
MM Fwd_GETS [0 ] 0
|
||||
MM Fwd_DMA [0 ] 0
|
||||
MM Inv [0 ] 0
|
||||
MM Exclusive_Unblock [40 ] 40
|
||||
MM Exclusive_Unblock [36 ] 36
|
||||
MM L2_Replacement [0 ] 0
|
||||
|
||||
SS L1_GETS [0 ] 0
|
||||
|
|
@ -1053,7 +1053,7 @@ SS L2_Replacement [0 ] 0
|
|||
OO L1_GETS [0 ] 0
|
||||
OO L1_GETX [0 ] 0
|
||||
OO L1_PUTO [0 ] 0
|
||||
OO L1_PUTX [0 ] 0
|
||||
OO L1_PUTX [16 ] 16
|
||||
OO L1_PUTS_only [0 ] 0
|
||||
OO L1_PUTS [0 ] 0
|
||||
OO Fwd_GETX [0 ] 0
|
||||
|
|
@ -1061,8 +1061,8 @@ OO Fwd_GETS [0 ] 0
|
|||
OO Fwd_DMA [0 ] 0
|
||||
OO Inv [0 ] 0
|
||||
OO Unblock [0 ] 0
|
||||
OO Exclusive_Unblock [9 ] 9
|
||||
OO L2_Replacement [0 ] 0
|
||||
OO Exclusive_Unblock [10 ] 10
|
||||
OO L2_Replacement [1 ] 1
|
||||
|
||||
OLSS L1_GETS [0 ] 0
|
||||
OLSS L1_GETX [0 ] 0
|
||||
|
|
@ -1117,7 +1117,7 @@ OI Writeback_Nack [0 ] 0
|
|||
OI L2_Replacement [0 ] 0
|
||||
|
||||
MI L1_GETS [0 ] 0
|
||||
MI L1_GETX [20 ] 20
|
||||
MI L1_GETX [35 ] 35
|
||||
MI L1_PUTO [0 ] 0
|
||||
MI L1_PUTX [0 ] 0
|
||||
MI L1_PUTS_only [0 ] 0
|
||||
|
|
@ -1125,7 +1125,7 @@ MI L1_PUTS [0 ] 0
|
|||
MI Fwd_GETX [0 ] 0
|
||||
MI Fwd_GETS [0 ] 0
|
||||
MI Fwd_DMA [0 ] 0
|
||||
MI Writeback_Ack [833 ] 833
|
||||
MI Writeback_Ack [813 ] 813
|
||||
MI L2_Replacement [0 ] 0
|
||||
|
||||
MII L1_GETS [0 ] 0
|
||||
|
|
@ -1232,51 +1232,51 @@ ILOXD DmaAck [0 ] 0
|
|||
ILOXD L2_Replacement [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1598
|
||||
memory_reads: 843
|
||||
memory_writes: 755
|
||||
memory_refreshes: 774
|
||||
memory_total_request_delays: 711
|
||||
memory_delays_per_request: 0.444931
|
||||
memory_delays_in_input_queue: 99
|
||||
memory_delays_behind_head_of_bank_queue: 1
|
||||
memory_delays_stalled_at_head_of_bank_queue: 611
|
||||
memory_stalls_for_bank_busy: 192
|
||||
memory_total_requests: 1557
|
||||
memory_reads: 824
|
||||
memory_writes: 733
|
||||
memory_refreshes: 745
|
||||
memory_total_request_delays: 699
|
||||
memory_delays_per_request: 0.44894
|
||||
memory_delays_in_input_queue: 100
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 599
|
||||
memory_stalls_for_bank_busy: 167
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 42
|
||||
memory_stalls_for_bus: 230
|
||||
memory_stalls_for_arbitration: 37
|
||||
memory_stalls_for_bus: 228
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 69
|
||||
memory_stalls_for_read_write_turnaround: 89
|
||||
memory_stalls_for_read_read_turnaround: 78
|
||||
accesses_per_bank: 55 50 42 77 67 66 60 47 44 55 47 36 56 64 44 42 45 36 61 44 58 41 44 55 46 43 43 50 49 41 48 42
|
||||
accesses_per_bank: 58 56 38 78 87 60 65 48 44 42 38 35 56 49 46 40 29 55 43 35 47 44 52 40 42 46 53 46 44 46 52 43
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [761 ] 761
|
||||
GETS [84 ] 84
|
||||
PUTX [834 ] 834
|
||||
GETX [788 ] 788
|
||||
GETS [87 ] 87
|
||||
PUTX [817 ] 817
|
||||
PUTO [0 ] 0
|
||||
PUTO_SHARERS [0 ] 0
|
||||
Unblock [0 ] 0
|
||||
Last_Unblock [0 ] 0
|
||||
Exclusive_Unblock [841 ] 841
|
||||
Clean_Writeback [78 ] 78
|
||||
Dirty_Writeback [755 ] 755
|
||||
Memory_Data [843 ] 843
|
||||
Memory_Ack [754 ] 754
|
||||
Exclusive_Unblock [820 ] 820
|
||||
Clean_Writeback [80 ] 80
|
||||
Dirty_Writeback [733 ] 733
|
||||
Memory_Data [822 ] 822
|
||||
Memory_Ack [732 ] 732
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_ACK [0 ] 0
|
||||
Data [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I GETX [759 ] 759
|
||||
I GETS [84 ] 84
|
||||
I GETX [737 ] 737
|
||||
I GETS [87 ] 87
|
||||
I PUTX [0 ] 0
|
||||
I PUTO [0 ] 0
|
||||
I Memory_Data [0 ] 0
|
||||
I Memory_Ack [750 ] 750
|
||||
I Memory_Ack [728 ] 728
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -1301,7 +1301,7 @@ O DMA_WRITE [0 ] 0
|
|||
|
||||
M GETX [0 ] 0
|
||||
M GETS [0 ] 0
|
||||
M PUTX [834 ] 834
|
||||
M PUTX [813 ] 813
|
||||
M PUTO [0 ] 0
|
||||
M PUTO_SHARERS [0 ] 0
|
||||
M Memory_Data [0 ] 0
|
||||
|
|
@ -1315,9 +1315,9 @@ IS PUTX [0 ] 0
|
|||
IS PUTO [0 ] 0
|
||||
IS PUTO_SHARERS [0 ] 0
|
||||
IS Unblock [0 ] 0
|
||||
IS Exclusive_Unblock [83 ] 83
|
||||
IS Memory_Data [84 ] 84
|
||||
IS Memory_Ack [1 ] 1
|
||||
IS Exclusive_Unblock [84 ] 84
|
||||
IS Memory_Data [86 ] 86
|
||||
IS Memory_Ack [0 ] 0
|
||||
IS DMA_READ [0 ] 0
|
||||
IS DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -1359,24 +1359,24 @@ MO DMA_WRITE [0 ] 0
|
|||
|
||||
MM GETX [0 ] 0
|
||||
MM GETS [0 ] 0
|
||||
MM PUTX [0 ] 0
|
||||
MM PUTX [4 ] 4
|
||||
MM PUTO [0 ] 0
|
||||
MM PUTO_SHARERS [0 ] 0
|
||||
MM Exclusive_Unblock [758 ] 758
|
||||
MM Memory_Data [759 ] 759
|
||||
MM Memory_Ack [3 ] 3
|
||||
MM Exclusive_Unblock [736 ] 736
|
||||
MM Memory_Data [736 ] 736
|
||||
MM Memory_Ack [4 ] 4
|
||||
MM DMA_READ [0 ] 0
|
||||
MM DMA_WRITE [0 ] 0
|
||||
|
||||
|
||||
MI GETX [2 ] 2
|
||||
MI GETX [51 ] 51
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTO [0 ] 0
|
||||
MI PUTO_SHARERS [0 ] 0
|
||||
MI Unblock [0 ] 0
|
||||
MI Clean_Writeback [78 ] 78
|
||||
MI Dirty_Writeback [755 ] 755
|
||||
MI Clean_Writeback [80 ] 80
|
||||
MI Dirty_Writeback [733 ] 733
|
||||
MI Memory_Data [0 ] 0
|
||||
MI Memory_Ack [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 03:47:36
|
||||
gem5 started Jan 23 2012 04:22:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
gem5 compiled Apr 6 2012 15:48:19
|
||||
gem5 started Apr 6 2012 15:57:35
|
||||
gem5 executing on sc2b0605
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
print getting inst port 0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 371241 because Ruby Tester completed
|
||||
Exiting @ tick 357561 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000371 # Number of seconds simulated
|
||||
sim_ticks 371241 # Number of ticks simulated
|
||||
final_tick 371241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000358 # Number of seconds simulated
|
||||
sim_ticks 357561 # Number of ticks simulated
|
||||
final_tick 357561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 812201 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214548 # Number of bytes of host memory used
|
||||
host_seconds 0.46 # Real time elapsed on the host
|
||||
host_tick_rate 507408 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230912 # Number of bytes of host memory used
|
||||
host_seconds 0.70 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
|
@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
|
|||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.port[0]
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -85,6 +91,7 @@ number_of_TBEs=256
|
|||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -114,13 +121,14 @@ dcache=system.l1_cntrl0.L1DcacheMemory
|
|||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
|
|
@ -148,14 +156,15 @@ size=512
|
|||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -268,19 +277,23 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.system_port
|
||||
slave=system.system_port
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.l1_cntrl0.sequencer.port[0]
|
||||
cpuDataPort=system.l1_cntrl0.sequencer.slave[0]
|
||||
cpuInstPort=system.l1_cntrl0.sequencer.slave[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/23/2012 04:22:32
|
||||
Real time: Apr/06/2012 15:58:16
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.28
|
||||
Virtual_time_in_minutes: 0.00466667
|
||||
Virtual_time_in_hours: 7.77778e-05
|
||||
Virtual_time_in_days: 3.24074e-06
|
||||
Virtual_time_in_seconds: 0.53
|
||||
Virtual_time_in_minutes: 0.00883333
|
||||
Virtual_time_in_hours: 0.000147222
|
||||
Virtual_time_in_days: 6.13426e-06
|
||||
|
||||
Ruby_current_time: 254811
|
||||
Ruby_current_time: 262451
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 254811
|
||||
Ruby_cycles: 262451
|
||||
|
||||
mbytes_resident: 39.6562
|
||||
mbytes_total: 209.445
|
||||
resident_ratio: 0.189339
|
||||
mbytes_resident: 41.8164
|
||||
mbytes_total: 225.266
|
||||
resident_ratio: 0.185666
|
||||
|
||||
ruby_cycles_executed: [ 254812 ]
|
||||
ruby_cycles_executed: [ 262452 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -66,17 +66,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 968 average: 15.8223 | standard deviation: 1.1424 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 901 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 984 average: 15.8354 | standard deviation: 1.13036 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 43 927 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 6786 count: 953 average: 4217 | standard deviation: 1907.02 | 76 12 1 4 2 6 12 15 5 9 2 8 6 3 1 0 1 2 3 0 0 0 3 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 7 8 5 15 14 23 19 28 37 33 34 37 54 51 30 34 31 30 25 32 21 23 24 23 23 15 17 15 6 6 8 9 3 6 5 4 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 6374 count: 48 average: 4227.06 | standard deviation: 2103.17 | 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 2 0 0 0 2 3 1 0 1 1 0 4 0 1 0 0 1 0 1 2 0 0 1 0 0 1 1 0 0 0 1 1 0 2 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6786 count: 853 average: 4438.8 | standard deviation: 1719.13 | 68 11 0 2 1 3 3 6 0 2 1 3 1 1 1 0 0 2 3 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 6 7 5 15 14 21 19 27 36 32 31 37 52 47 29 33 27 29 24 31 19 22 24 21 23 14 16 12 6 6 6 8 3 6 5 3 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1410 count: 52 average: 569.423 | standard deviation: 218.615 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 3 1 2 2 0 0 1 0 0 1 1 2 0 2 3 2 0 1 1 0 0 1 0 0 1 1 1 1 2 0 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 116 count: 88 average: 17.0114 | standard deviation: 36.8762 | 0 22 14 23 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 2 1 0 1 1 1 0 1 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 6374 count: 41 average: 3115.78 | standard deviation: 2260.77 | 0 0 0 0 0 0 0 2 0 1 2 1 0 1 4 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 2 0 1 0 0 3 1 0 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6786 count: 824 average: 4720.34 | standard deviation: 1325.89 | 0 0 1 2 1 3 11 11 5 8 0 8 5 2 1 0 1 2 2 0 0 0 3 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 6 8 4 14 14 21 19 27 35 32 31 36 52 48 30 33 31 30 25 32 21 23 23 23 23 15 16 15 6 5 8 8 3 6 5 3 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 6619 count: 969 average: 4277.35 | standard deviation: 1934.43 | 79 13 3 7 10 1 7 11 10 4 3 6 6 2 3 2 2 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 10 9 3 13 13 19 16 25 19 27 24 32 34 43 37 42 39 38 33 36 32 41 32 28 15 14 18 19 13 8 18 7 4 5 3 4 1 2 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 6616 count: 51 average: 4258.78 | standard deviation: 2119.03 | 7 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 2 1 2 3 5 3 3 1 0 2 0 2 3 1 0 2 2 1 2 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6619 count: 869 average: 4491.44 | standard deviation: 1749.39 | 71 11 1 3 2 1 2 6 2 0 2 2 1 1 2 2 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 10 9 2 13 13 19 16 24 19 25 23 30 31 38 34 39 38 38 31 36 30 38 31 28 13 12 17 17 11 8 18 7 4 5 3 4 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1029 count: 49 average: 499.857 | standard deviation: 220.453 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 1 2 1 0 0 0 2 3 0 2 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 1 0 0 0 0 1 1 2 2 1 0 0 2 2 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 116 count: 91 average: 17.9121 | standard deviation: 38.4436 | 0 28 14 19 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 0 0 2 4 0 1 2 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 6221 count: 45 average: 2770.13 | standard deviation: 2320.89 | 0 1 0 0 2 1 0 3 2 1 0 0 0 1 0 2 0 3 0 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 2 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 2 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6619 count: 833 average: 4824.09 | standard deviation: 1289.25 | 0 0 0 4 7 1 6 9 7 3 3 6 5 1 2 1 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 9 7 2 12 13 19 14 25 18 25 24 31 34 43 36 40 39 37 31 35 31 41 32 28 14 14 17 19 12 8 18 7 4 4 3 4 1 2 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -86,15 +86,14 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 824
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 111 count: 9 average: 14.2222 | standard deviation: 36.3043 | 0 3 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 32 max: 6374 count: 2 average: 5575 | standard deviation: 1129.96 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 6097 count: 37 average: 5178.95 | standard deviation: 519.569 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1 0 0 0 2 3 1 0 1 1 0 4 0 1 0 0 1 0 1 2 0 0 1 0 0 1 1 0 0 0 1 1 0 2 1 0 0 0 0 1 1 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 79 average: 17.3291 | standard deviation: 37.1563 | 0 19 13 19 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 2 1 0 0 1 1 0 1 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 6128 count: 33 average: 3448.85 | standard deviation: 2129.45 | 0 0 0 0 0 0 0 1 0 1 1 1 0 1 2 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 2 0 1 0 0 2 1 0 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6786 count: 741 average: 4954.27 | standard deviation: 899.825 | 0 0 0 1 0 1 2 4 0 2 0 3 0 0 1 0 0 2 2 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 5 2 0 2 5 7 4 14 14 19 19 26 34 31 29 36 50 44 29 32 27 29 24 31 19 22 23 21 23 14 15 12 6 5 6 7 3 6 5 3 1 0 1 4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 4 max: 669 count: 6 average: 464.167 | standard deviation: 153.369 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1410 count: 46 average: 583.152 | standard deviation: 223.341 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 3 1 2 2 0 0 1 0 0 0 0 2 0 2 3 2 0 1 1 0 0 1 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 833
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 116 count: 9 average: 27.1111 | standard deviation: 49.5568 | 0 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 64 max: 6616 count: 42 average: 5165.57 | standard deviation: 838.074 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 2 1 2 3 5 3 3 1 0 2 0 2 3 1 0 2 2 1 2 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 82 average: 16.9024 | standard deviation: 37.2711 | 0 26 12 16 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 0 0 2 3 0 1 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 6221 count: 35 average: 3440 | standard deviation: 2206.6 | 0 0 0 0 0 1 0 2 1 1 0 0 0 1 0 2 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 2 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 2 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6619 count: 752 average: 5028.29 | standard deviation: 889.008 | 0 0 0 1 0 1 1 4 1 0 2 2 1 0 2 1 0 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 4 2 0 2 9 7 1 12 13 19 14 24 18 23 23 29 31 38 33 37 38 37 29 35 29 38 31 28 12 12 16 17 10 8 18 7 4 4 3 4 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 8 max: 897 count: 10 average: 425.6 | standard deviation: 295.308 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1029 count: 39 average: 518.897 | standard deviation: 197.26 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 2 3 0 2 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 1 0 0 0 0 1 1 2 2 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -126,125 +125,125 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10441
|
||||
page_faults: 0
|
||||
page_reclaims: 11804
|
||||
page_faults: 3
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 80
|
||||
block_inputs: 1456
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 5091 40728
|
||||
total_msg_count_Response_Data: 2586 186192
|
||||
total_msg_count_ResponseL2hit_Data: 120 8640
|
||||
total_msg_count_Response_Control: 9 72
|
||||
total_msg_count_Writeback_Data: 4998 359856
|
||||
total_msg_count_Writeback_Control: 210 1680
|
||||
total_msg_count_Persistent_Control: 2100 16800
|
||||
total_msgs: 15114 total_bytes: 613968
|
||||
total_msg_count_Request_Control: 5154 41232
|
||||
total_msg_count_Response_Data: 2646 190512
|
||||
total_msg_count_ResponseL2hit_Data: 123 8856
|
||||
total_msg_count_Response_Control: 3 24
|
||||
total_msg_count_Writeback_Data: 5019 361368
|
||||
total_msg_count_Writeback_Control: 201 1608
|
||||
total_msg_count_Persistent_Control: 2034 16272
|
||||
total_msgs: 15180 total_bytes: 619872
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.82645
|
||||
links_utilized_percent_switch_0_link_0: 1.74522 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.90769 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 1.78671
|
||||
links_utilized_percent_switch_0_link_0: 1.70737 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.86606 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 844 60768 [ 0 0 0 0 844 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 65 4680 [ 0 0 0 0 65 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 867 6936 [ 0 867 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 927 66744 [ 0 0 0 0 927 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 57 4104 [ 0 0 0 0 57 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 22 1584 [ 0 0 0 0 22 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.66584
|
||||
links_utilized_percent_switch_1_link_0: 1.76111 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.57058 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 1.64269
|
||||
links_utilized_percent_switch_1_link_0: 1.73061 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.55477 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 867 6936 [ 0 867 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 862 62064 [ 0 0 0 0 862 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 732 52704 [ 0 0 0 0 732 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 70 560 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 839 6712 [ 0 0 839 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 25 1800 [ 0 0 0 0 25 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 740 53280 [ 0 0 0 0 740 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 67 536 [ 0 0 0 0 67 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.5275
|
||||
links_utilized_percent_switch_2_link_0: 1.58215 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.47286 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.49114
|
||||
links_utilized_percent_switch_2_link_0: 1.54715 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.43513 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 739 53208 [ 0 0 0 0 739 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 70 560 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 827 59544 [ 0 0 0 0 827 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 839 6712 [ 0 0 839 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 22 1584 [ 0 0 0 0 22 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 742 53424 [ 0 0 0 0 742 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 67 536 [ 0 0 0 0 67 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 835 60120 [ 0 0 0 0 835 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 1.67327
|
||||
links_utilized_percent_switch_3_link_0: 1.67654 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.76111 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.58215 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 1.64018
|
||||
links_utilized_percent_switch_3_link_0: 1.64278 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.73061 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.54715 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 844 60768 [ 0 0 0 0 844 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 65 4680 [ 0 0 0 0 65 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 867 6936 [ 0 867 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 862 62064 [ 0 0 0 0 862 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 739 53208 [ 0 0 0 0 739 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 70 560 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 350 2800 [ 0 0 0 350 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 57 4104 [ 0 0 0 0 57 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 839 6712 [ 0 0 839 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 22 1584 [ 0 0 0 0 22 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 742 53424 [ 0 0 0 0 742 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 67 536 [ 0 0 0 0 67 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 339 2712 [ 0 0 0 339 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 52
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 52
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 49
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 49
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 52 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 49 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 815
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 815
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 830
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 830
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.78528%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.2147%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.06024%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.9398%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 815 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 830 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [48 ] 48
|
||||
Ifetch [52 ] 52
|
||||
Store [855 ] 855
|
||||
Load [51 ] 51
|
||||
Ifetch [49 ] 49
|
||||
Store [870 ] 870
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [18483 ] 18483
|
||||
Data_Shared [8 ] 8
|
||||
Data_Owner [3 ] 3
|
||||
Data_All_Tokens [937 ] 937
|
||||
L1_Replacement [19023 ] 19023
|
||||
Data_Shared [7 ] 7
|
||||
Data_Owner [1 ] 1
|
||||
Data_All_Tokens [949 ] 949
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [3 ] 3
|
||||
Ack_All_Tokens [1 ] 1
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
|
|
@ -254,21 +253,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
|
|||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [350 ] 350
|
||||
Request_Timeout [565 ] 565
|
||||
Own_Lock_or_Unlock [339 ] 339
|
||||
Request_Timeout [548 ] 548
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [856 ] 856
|
||||
Use_TimeoutNoStarvers [870 ] 870
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [39 ] 39
|
||||
NP Ifetch [52 ] 52
|
||||
NP Store [776 ] 776
|
||||
NP Load [42 ] 42
|
||||
NP Ifetch [49 ] 49
|
||||
NP Store [788 ] 788
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [83 ] 83
|
||||
NP Data_All_Tokens [79 ] 79
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
|
|
@ -277,7 +276,7 @@ NP Transient_Local_GETS [0 ] 0
|
|||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [168 ] 168
|
||||
NP Own_Lock_or_Unlock [167 ] 167
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
|
|
@ -303,7 +302,7 @@ S Load [0 ] 0
|
|||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [8 ] 8
|
||||
S L1_Replacement [7 ] 7
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
|
|
@ -343,70 +342,70 @@ M Load [0 ] 0
|
|||
M Ifetch [0 ] 0
|
||||
M Store [0 ] 0
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [80 ] 80
|
||||
M L1_Replacement [81 ] 81
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [14 ] 14
|
||||
M Own_Lock_or_Unlock [9 ] 9
|
||||
|
||||
MM Load [9 ] 9
|
||||
MM Load [8 ] 8
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [68 ] 68
|
||||
MM Store [71 ] 71
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [774 ] 774
|
||||
MM L1_Replacement [786 ] 786
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [17 ] 17
|
||||
MM Own_Lock_or_Unlock [13 ] 13
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [1 ] 1
|
||||
M_W Store [0 ] 0
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [353 ] 353
|
||||
M_W L1_Replacement [382 ] 382
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
M_W Transient_Local_GETS [0 ] 0
|
||||
M_W Persistent_GETX [0 ] 0
|
||||
M_W Persistent_GETS [0 ] 0
|
||||
M_W Own_Lock_or_Unlock [3 ] 3
|
||||
M_W Own_Lock_or_Unlock [1 ] 1
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [81 ] 81
|
||||
M_W Use_TimeoutNoStarvers [83 ] 83
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [10 ] 10
|
||||
MM_W Store [11 ] 11
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [7103 ] 7103
|
||||
MM_W L1_Replacement [7361 ] 7361
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [22 ] 22
|
||||
MM_W Own_Lock_or_Unlock [17 ] 17
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [775 ] 775
|
||||
MM_W Use_TimeoutNoStarvers [787 ] 787
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [9674 ] 9674
|
||||
IM L1_Replacement [9875 ] 9875
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [3 ] 3
|
||||
IM Data_All_Tokens [771 ] 771
|
||||
IM Data_Owner [1 ] 1
|
||||
IM Data_All_Tokens [786 ] 786
|
||||
IM Ack [0 ] 0
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
|
|
@ -417,8 +416,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0
|
|||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [104 ] 104
|
||||
IM Request_Timeout [466 ] 466
|
||||
IM Own_Lock_or_Unlock [118 ] 118
|
||||
IM Request_Timeout [494 ] 494
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
|
|
@ -449,7 +448,7 @@ OM L1_Replacement [0 ] 0
|
|||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [3 ] 3
|
||||
OM Ack_All_Tokens [1 ] 1
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
|
|
@ -459,17 +458,17 @@ OM Transient_Local_GETS_Last_Token [0 ] 0
|
|||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [3 ] 3
|
||||
OM Request_Timeout [24 ] 24
|
||||
OM Own_Lock_or_Unlock [1 ] 1
|
||||
OM Request_Timeout [1 ] 1
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [491 ] 491
|
||||
IS Data_Shared [8 ] 8
|
||||
IS L1_Replacement [531 ] 531
|
||||
IS Data_Shared [7 ] 7
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [83 ] 83
|
||||
IS Data_All_Tokens [84 ] 84
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
|
|
@ -480,8 +479,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0
|
|||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [19 ] 19
|
||||
IS Request_Timeout [75 ] 75
|
||||
IS Own_Lock_or_Unlock [13 ] 13
|
||||
IS Request_Timeout [53 ] 53
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
|
|
@ -585,50 +584,50 @@ IS_L Own_Lock_or_Unlock [0 ] 0
|
|||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 830
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 830
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 839
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 839
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.0119%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.9881%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 830 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 839 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [91 ] 91
|
||||
L1_GETS_Last_Token [0 ] 0
|
||||
L1_GETX [776 ] 776
|
||||
L1_GETX [788 ] 788
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [762 ] 762
|
||||
L2_Replacement [779 ] 779
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [4 ] 4
|
||||
Writeback_All_Tokens [858 ] 858
|
||||
Writeback_Shared_Data [3 ] 3
|
||||
Writeback_All_Tokens [871 ] 871
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [152 ] 152
|
||||
Persistent_GETS [23 ] 23
|
||||
Persistent_GETX [154 ] 154
|
||||
Persistent_GETS [16 ] 16
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [175 ] 175
|
||||
Own_Lock_or_Unlock [169 ] 169
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [83 ] 83
|
||||
NP L1_GETX [744 ] 744
|
||||
NP L1_GETS [81 ] 81
|
||||
NP L1_GETX [754 ] 754
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [0 ] 0
|
||||
NP Writeback_All_Tokens [766 ] 766
|
||||
NP Writeback_Shared_Data [2 ] 2
|
||||
NP Writeback_All_Tokens [781 ] 781
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
|
|
@ -637,25 +636,25 @@ NP Ack [0 ] 0
|
|||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [154 ] 154
|
||||
NP Own_Lock_or_Unlock [145 ] 145
|
||||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS [3 ] 3
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [0 ] 0
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [18 ] 18
|
||||
I L2_Replacement [25 ] 25
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [3 ] 3
|
||||
I Writeback_All_Tokens [30 ] 30
|
||||
I Writeback_Shared_Data [1 ] 1
|
||||
I Writeback_All_Tokens [31 ] 31
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
I Data_All_Tokens [0 ] 0
|
||||
I Ack [0 ] 0
|
||||
I Persistent_GETX [1 ] 1
|
||||
I Persistent_GETX [0 ] 0
|
||||
I Persistent_GETS [0 ] 0
|
||||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
|
@ -667,7 +666,7 @@ S L1_INV [0 ] 0
|
|||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [0 ] 0
|
||||
S L2_Replacement [2 ] 2
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
|
|
@ -676,21 +675,21 @@ S Data_Shared [0 ] 0
|
|||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Persistent_GETX [3 ] 3
|
||||
S Persistent_GETX [1 ] 1
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [1 ] 1
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [3 ] 3
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [0 ] 0
|
||||
O L2_Replacement [2 ] 2
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [1 ] 1
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [4 ] 4
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
|
|
@ -702,13 +701,13 @@ O Persistent_GETS_Last_Token [0 ] 0
|
|||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [7 ] 7
|
||||
M L1_GETX [29 ] 29
|
||||
M L1_GETX [33 ] 33
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [744 ] 744
|
||||
M Persistent_GETX [15 ] 15
|
||||
M Persistent_GETS [2 ] 2
|
||||
M L2_Replacement [748 ] 748
|
||||
M Persistent_GETX [21 ] 21
|
||||
M Persistent_GETS [4 ] 4
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
|
|
@ -717,18 +716,18 @@ I_L L1_INV [0 ] 0
|
|||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [0 ] 0
|
||||
I_L L2_Replacement [2 ] 2
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [58 ] 58
|
||||
I_L Writeback_All_Tokens [55 ] 55
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [133 ] 133
|
||||
I_L Persistent_GETS [21 ] 21
|
||||
I_L Own_Lock_or_Unlock [21 ] 21
|
||||
I_L Persistent_GETX [132 ] 132
|
||||
I_L Persistent_GETS [12 ] 12
|
||||
I_L Own_Lock_or_Unlock [24 ] 24
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
|
|
@ -752,83 +751,83 @@ S_L Persistent_GETS_Last_Token [0 ] 0
|
|||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1574
|
||||
memory_reads: 826
|
||||
memory_writes: 748
|
||||
memory_refreshes: 531
|
||||
memory_total_request_delays: 1037
|
||||
memory_delays_per_request: 0.658831
|
||||
memory_delays_in_input_queue: 141
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 894
|
||||
memory_stalls_for_bank_busy: 217
|
||||
memory_total_requests: 1596
|
||||
memory_reads: 835
|
||||
memory_writes: 761
|
||||
memory_refreshes: 547
|
||||
memory_total_request_delays: 1074
|
||||
memory_delays_per_request: 0.672932
|
||||
memory_delays_in_input_queue: 139
|
||||
memory_delays_behind_head_of_bank_queue: 6
|
||||
memory_delays_stalled_at_head_of_bank_queue: 929
|
||||
memory_stalls_for_bank_busy: 268
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 83
|
||||
memory_stalls_for_bus: 353
|
||||
memory_stalls_for_arbitration: 74
|
||||
memory_stalls_for_bus: 361
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 169
|
||||
memory_stalls_for_read_read_turnaround: 72
|
||||
accesses_per_bank: 45 29 60 82 68 54 61 51 42 44 37 39 45 54 39 49 42 55 46 41 46 48 53 59 44 62 49 35 51 49 60 35
|
||||
memory_stalls_for_read_write_turnaround: 153
|
||||
memory_stalls_for_read_read_turnaround: 73
|
||||
accesses_per_bank: 46 42 72 75 73 65 78 39 46 46 48 32 36 37 38 55 48 51 51 51 51 45 60 38 39 64 62 41 48 31 39 49
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [768 ] 768
|
||||
GETS [83 ] 83
|
||||
Lockdown [175 ] 175
|
||||
Unlockdown [175 ] 175
|
||||
GETX [789 ] 789
|
||||
GETS [84 ] 84
|
||||
Lockdown [170 ] 170
|
||||
Unlockdown [169 ] 169
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [757 ] 757
|
||||
Data_Owner [2 ] 2
|
||||
Data_All_Tokens [762 ] 762
|
||||
Ack_Owner [0 ] 0
|
||||
Ack_Owner_All_Tokens [70 ] 70
|
||||
Ack_Owner_All_Tokens [65 ] 65
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Ack_All_Tokens [2 ] 2
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [825 ] 825
|
||||
Memory_Ack [748 ] 748
|
||||
Memory_Data [835 ] 835
|
||||
Memory_Ack [760 ] 760
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [739 ] 739
|
||||
O GETS [83 ] 83
|
||||
O Lockdown [4 ] 4
|
||||
O GETX [748 ] 748
|
||||
O GETS [81 ] 81
|
||||
O Lockdown [5 ] 5
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [0 ] 0
|
||||
O Ack_All_Tokens [2 ] 2
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [6 ] 6
|
||||
NO GETS [0 ] 0
|
||||
NO Lockdown [159 ] 159
|
||||
NO GETX [3 ] 3
|
||||
NO GETS [3 ] 3
|
||||
NO Lockdown [149 ] 149
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [0 ] 0
|
||||
NO Data_All_Tokens [748 ] 748
|
||||
NO Data_Owner [2 ] 2
|
||||
NO Data_All_Tokens [759 ] 759
|
||||
NO Ack_Owner [0 ] 0
|
||||
NO Ack_Owner_All_Tokens [70 ] 70
|
||||
NO Ack_Owner_All_Tokens [65 ] 65
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [2 ] 2
|
||||
L GETX [4 ] 4
|
||||
L GETS [0 ] 0
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [173 ] 173
|
||||
L Unlockdown [168 ] 168
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [9 ] 9
|
||||
L Data_All_Tokens [3 ] 3
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [0 ] 0
|
||||
L Tokens [0 ] 0
|
||||
|
|
@ -838,7 +837,7 @@ L DMA_WRITE_All_Tokens [0 ] 0
|
|||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W Lockdown [2 ] 2
|
||||
O_W Lockdown [1 ] 1
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
|
|
@ -847,16 +846,16 @@ O_W Data_All_Tokens [0 ] 0
|
|||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [748 ] 748
|
||||
O_W Memory_Data [1 ] 1
|
||||
O_W Memory_Ack [759 ] 759
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [21 ] 21
|
||||
L_O_W GETX [34 ] 34
|
||||
L_O_W GETS [0 ] 0
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [2 ] 2
|
||||
L_O_W Unlockdown [1 ] 1
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
|
|
@ -864,8 +863,8 @@ L_O_W Data_All_Tokens [0 ] 0
|
|||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [4 ] 4
|
||||
L_O_W Memory_Ack [0 ] 0
|
||||
L_O_W Memory_Data [5 ] 5
|
||||
L_O_W Memory_Ack [1 ] 1
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
@ -881,7 +880,7 @@ L_NO_W Data_All_Tokens [0 ] 0
|
|||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [10 ] 10
|
||||
L_NO_W Memory_Data [15 ] 15
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
@ -922,7 +921,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
|||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [10 ] 10
|
||||
NO_W Lockdown [15 ] 15
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
|
|
@ -931,7 +930,7 @@ NO_W Data_All_Tokens [0 ] 0
|
|||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [811 ] 811
|
||||
NO_W Memory_Data [814 ] 814
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 03:50:16
|
||||
gem5 started Jan 23 2012 04:22:31
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
gem5 compiled Apr 6 2012 14:55:37
|
||||
gem5 started Apr 6 2012 15:58:16
|
||||
gem5 executing on sc2b0605
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
print getting inst port 0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 254811 because Ruby Tester completed
|
||||
Exiting @ tick 262451 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000255 # Number of seconds simulated
|
||||
sim_ticks 254811 # Number of ticks simulated
|
||||
final_tick 254811 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000262 # Number of seconds simulated
|
||||
sim_ticks 262451 # Number of ticks simulated
|
||||
final_tick 262451 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 1986774 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214476 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 1346552 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230676 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
|
@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
|
|||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.port[0]
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -91,6 +97,7 @@ no_mig_atomic=true
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -129,23 +136,25 @@ dcache=system.l1_cntrl0.L1DcacheMemory
|
|||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -236,19 +245,23 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.system_port
|
||||
slave=system.system_port
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
check_flush=true
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.l1_cntrl0.sequencer.port[0]
|
||||
cpuDataPort=system.l1_cntrl0.sequencer.slave[0]
|
||||
cpuInstPort=system.l1_cntrl0.sequencer.slave[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/23/2012 04:21:49
|
||||
Real time: Apr/06/2012 15:58:55
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.25
|
||||
Virtual_time_in_minutes: 0.00416667
|
||||
Virtual_time_in_hours: 6.94444e-05
|
||||
Virtual_time_in_days: 2.89352e-06
|
||||
Virtual_time_in_seconds: 0.47
|
||||
Virtual_time_in_minutes: 0.00783333
|
||||
Virtual_time_in_hours: 0.000130556
|
||||
Virtual_time_in_days: 5.43981e-06
|
||||
|
||||
Ruby_current_time: 213131
|
||||
Ruby_current_time: 205611
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 213131
|
||||
Ruby_cycles: 205611
|
||||
|
||||
mbytes_resident: 39.2617
|
||||
mbytes_total: 209.207
|
||||
resident_ratio: 0.187669
|
||||
mbytes_resident: 41.4375
|
||||
mbytes_total: 225.051
|
||||
resident_ratio: 0.18416
|
||||
|
||||
ruby_cycles_executed: [ 213132 ]
|
||||
ruby_cycles_executed: [ 205612 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -65,17 +65,18 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.7883 | standard deviation: 1.14907 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 82 879 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 955 average: 15.8063 | standard deviation: 1.1547 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 64 876 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 6858 count: 963 average: 3505.41 | standard deviation: 1666 | 67 16 4 2 10 5 22 17 6 9 5 8 4 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 9 13 24 17 17 29 22 26 32 30 39 37 41 29 39 32 34 28 34 30 27 28 19 18 10 3 7 12 5 7 7 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 6253 count: 51 average: 3926.14 | standard deviation: 1480.7 | 3 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6858 count: 863 average: 3652.34 | standard deviation: 1553.9 | 60 13 3 2 7 3 9 13 1 7 0 4 1 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 8 13 21 16 16 26 21 25 32 30 37 35 38 27 38 28 33 28 33 28 23 25 18 18 9 1 7 10 5 7 7 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1022 count: 49 average: 479.796 | standard deviation: 243.565 | 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 114 count: 72 average: 17.4167 | standard deviation: 35.9832 | 0 9 9 12 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 1 2 0 0 1 0 0 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 5339 count: 41 average: 2283.05 | standard deviation: 1908.79 | 5 0 0 6 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6858 count: 850 average: 3859.83 | standard deviation: 1320.43 | 0 0 4 0 10 4 22 15 6 8 5 8 3 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 9 12 23 17 15 27 21 25 31 29 38 35 41 29 39 32 33 28 32 30 27 28 19 18 9 3 7 12 5 7 6 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 32 max: 5995 count: 940 average: 3454.8 | standard deviation: 1689.48 | 73 0 0 15 0 3 1 1 9 6 2 7 11 6 2 14 6 0 5 12 4 2 3 2 1 3 2 1 0 0 1 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 3 3 2 4 5 6 5 14 2 7 10 3 17 12 13 12 12 19 15 16 15 18 28 27 20 15 26 23 19 24 21 26 18 22 22 18 11 20 18 12 11 10 9 7 8 8 11 9 0 7 5 8 5 7 3 3 4 5 4 1 1 5 2 2 0 0 3 0 0 2 0 0 2 5 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5688 count: 51 average: 3691.18 | standard deviation: 1748.75 | 8 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 0 0 0 1 0 0 1 0 0 2 1 0 4 1 3 1 1 0 1 2 1 3 0 0 4 1 1 2 2 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 5995 count: 837 average: 3617.77 | standard deviation: 1564.58 | 62 0 0 14 0 2 1 0 4 4 2 3 5 2 0 10 2 0 2 7 4 1 2 0 1 2 2 1 0 0 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 3 3 2 4 5 6 4 14 2 7 10 3 15 12 13 12 12 18 15 16 14 18 28 25 19 15 22 21 16 23 20 26 17 20 21 14 11 20 14 11 10 8 7 7 8 8 10 9 0 7 5 7 4 7 3 3 3 5 3 1 0 5 2 2 0 0 3 0 0 2 0 0 1 5 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 809 count: 49 average: 434 | standard deviation: 189.079 | 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 2 2 1 0 1 0 0 0 0 0 0 1 0 2 4 2 0 0 1 2 1 0 0 2 0 0 1 2 1 0 2 0 1 1 0 0 0 0 1 1 0 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_FLUSH: [binsize: 32 max: 4507 count: 3 average: 3306 | standard deviation: 1853.78 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 4507 count: 81 average: 139.605 | standard deviation: 691.167 | 67 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 5708 count: 38 average: 2643.53 | standard deviation: 1886.57 | 6 0 0 4 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 2 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 2 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 5995 count: 821 average: 3819.42 | standard deviation: 1346.15 | 0 0 0 0 0 3 1 1 9 5 2 7 11 5 2 14 6 0 5 11 4 2 3 2 1 3 2 1 0 0 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 2 2 2 4 4 6 5 12 2 7 10 2 17 12 13 12 11 18 14 15 14 17 28 25 19 14 25 21 19 23 21 26 18 22 22 16 11 20 18 12 11 10 8 7 8 8 11 9 0 7 5 8 5 7 3 3 4 5 4 1 1 5 2 2 0 0 3 0 0 2 0 0 2 4 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,15 +86,16 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 850
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 103 count: 4 average: 27.75 | standard deviation: 50.183 | 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 6253 count: 47 average: 4257.91 | standard deviation: 974.148 | 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 114 count: 66 average: 17.197 | standard deviation: 35.8598 | 0 8 9 11 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 2 0 0 1 0 0 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 5339 count: 37 average: 2523.57 | standard deviation: 1854.34 | 3 0 0 4 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6858 count: 760 average: 4022.97 | standard deviation: 1109.22 | 0 0 3 0 7 2 9 11 1 6 0 4 0 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 8 12 20 16 14 24 20 24 31 29 36 33 38 27 38 28 32 28 31 28 23 25 18 18 8 1 7 10 5 7 6 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 2 average: 4 | standard deviation: 0 | 0 0 0 0 2 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 112 count: 4 average: 58.25 | standard deviation: 60.9289 | 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1022 count: 43 average: 541.14 | standard deviation: 189.677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 821
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 7 average: 2.42857 | standard deviation: 1 | 0 1 3 2 1 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 32 max: 4298 count: 2 average: 2152.5 | standard deviation: 3034.2 | 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5688 count: 42 average: 4379.24 | standard deviation: 762.412 | 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 0 0 0 1 0 0 1 0 0 2 1 0 4 1 3 0 1 0 1 2 1 3 0 0 4 1 1 2 2 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 71 average: 19.338 | standard deviation: 39.1116 | 0 12 12 16 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 3 1 0 0 2 0 1 0 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 5708 count: 32 average: 3000.47 | standard deviation: 1710.17 | 2 0 0 3 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 2 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 2 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 5995 count: 734 average: 3992.76 | standard deviation: 1120.88 | 0 0 0 0 0 2 1 0 4 3 2 3 5 1 0 10 2 0 2 6 4 1 2 0 1 2 2 1 0 0 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 2 2 2 4 4 6 4 12 2 7 10 2 15 12 13 12 11 17 14 15 13 17 28 23 18 14 21 20 16 23 20 26 17 20 21 13 11 20 14 11 10 8 6 7 8 8 10 9 0 7 5 7 4 7 3 3 3 5 3 1 0 5 2 2 0 0 3 0 0 2 0 0 1 4 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 115 count: 4 average: 33.5 | standard deviation: 54.3476 | 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 809 count: 45 average: 469.6 | standard deviation: 151.399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 2 2 1 0 1 0 0 0 0 0 0 1 0 2 4 2 0 0 1 2 1 0 0 2 0 0 1 2 1 0 2 0 1 1 0 0 0 0 1 1 0 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_FLUSH_L1Cache: [binsize: 32 max: 4507 count: 3 average: 3306 | standard deviation: 1853.78 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -125,107 +127,109 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10363
|
||||
page_faults: 0
|
||||
page_reclaims: 11717
|
||||
page_faults: 4
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 80
|
||||
block_inputs: 1448
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 2553 20424
|
||||
total_msg_count_Response_Data: 2550 183600
|
||||
total_msg_count_Writeback_Data: 2292 165024
|
||||
total_msg_count_Writeback_Control: 5291 42328
|
||||
total_msg_count_Unblock_Control: 2546 20368
|
||||
total_msgs: 15232 total_bytes: 431744
|
||||
total_msg_count_Request_Control: 2475 19800
|
||||
total_msg_count_Response_Data: 2469 177768
|
||||
total_msg_count_Writeback_Data: 2211 159192
|
||||
total_msg_count_Writeback_Control: 5145 41160
|
||||
total_msg_count_Unblock_Control: 2460 19680
|
||||
total_msgs: 14760 total_bytes: 417600
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.11044
|
||||
links_utilized_percent_switch_0_link_0: 1.9922 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.22868 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.11565
|
||||
links_utilized_percent_switch_0_link_0: 2.00014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.23115 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 0 0 845 0 0 78 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 823 59256 [ 0 0 0 0 823 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 818 6544 [ 0 0 0 818 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 825 6600 [ 0 0 825 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 737 53064 [ 0 0 0 0 0 737 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 897 7176 [ 0 0 817 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 820 6560 [ 0 0 0 0 0 820 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.10985
|
||||
links_utilized_percent_switch_1_link_0: 2.2275 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.9922 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.11565
|
||||
links_utilized_percent_switch_1_link_0: 2.23115 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.00014 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 850 6800 [ 0 0 850 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 848 6784 [ 0 0 0 0 0 848 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 825 6600 [ 0 0 825 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 737 53064 [ 0 0 0 0 0 737 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 897 7176 [ 0 0 817 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 820 6560 [ 0 0 0 0 0 820 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 823 59256 [ 0 0 0 0 823 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 818 6544 [ 0 0 0 818 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.11009
|
||||
links_utilized_percent_switch_2_link_0: 1.9922 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.22797 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 2.11565
|
||||
links_utilized_percent_switch_2_link_0: 2.00014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.23115 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 823 59256 [ 0 0 0 0 823 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 818 6544 [ 0 0 0 818 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 825 6600 [ 0 0 825 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 737 53064 [ 0 0 0 0 0 737 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 897 7176 [ 0 0 817 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 820 6560 [ 0 0 0 0 0 820 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 47
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 47
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 49
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 49
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 47 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 49 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 846
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 846
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 812
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 812
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.55556%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4444%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.41872%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4581%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_FLUSH: 0.123153%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 846 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 812 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 893
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 893
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 863
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 863
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.26316%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.4737%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.26316%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.09849%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 88.876%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.67787%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_FLUSH: 0.347625%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 893 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 863 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [51 ] 51
|
||||
Ifetch [52 ] 52
|
||||
Store [889 ] 889
|
||||
L2_Replacement [845 ] 845
|
||||
L1_to_L2 [15901 ] 15901
|
||||
Trigger_L2_to_L1D [37 ] 37
|
||||
Load [53 ] 53
|
||||
Ifetch [49 ] 49
|
||||
Store [861 ] 861
|
||||
L2_Replacement [814 ] 814
|
||||
L1_to_L2 [15927 ] 15927
|
||||
Trigger_L2_to_L1D [35 ] 35
|
||||
Trigger_L2_to_L1I [4 ] 4
|
||||
Complete_L2_to_L1 [41 ] 41
|
||||
Complete_L2_to_L1 [39 ] 39
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
|
|
@ -236,18 +240,18 @@ Ack [0 ] 0
|
|||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [850 ] 850
|
||||
Writeback_Ack [842 ] 842
|
||||
Exclusive_Data [823 ] 823
|
||||
Writeback_Ack [817 ] 817
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [850 ] 850
|
||||
Flush_line [0 ] 0
|
||||
Block_Ack [0 ] 0
|
||||
All_acks_no_sharers [823 ] 823
|
||||
Flush_line [3 ] 3
|
||||
Block_Ack [1 ] 1
|
||||
|
||||
- Transitions -
|
||||
I Load [47 ] 47
|
||||
I Ifetch [43 ] 43
|
||||
I Store [762 ] 762
|
||||
I Load [42 ] 42
|
||||
I Ifetch [45 ] 45
|
||||
I Store [735 ] 735
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
|
|
@ -257,7 +261,7 @@ I Other_GETS [0 ] 0
|
|||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [0 ] 0
|
||||
I Flush_line [2 ] 2
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
|
|
@ -289,11 +293,11 @@ O Invalidate [0 ] 0
|
|||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Ifetch [0 ] 0
|
||||
M Store [0 ] 0
|
||||
M L2_Replacement [79 ] 79
|
||||
M L1_to_L2 [88 ] 88
|
||||
M Trigger_L2_to_L1D [9 ] 9
|
||||
M L2_Replacement [78 ] 78
|
||||
M L1_to_L2 [84 ] 84
|
||||
M Trigger_L2_to_L1D [6 ] 6
|
||||
M Trigger_L2_to_L1I [0 ] 0
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
|
|
@ -303,12 +307,12 @@ M NC_DMA_GETS [0 ] 0
|
|||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [4 ] 4
|
||||
MM Ifetch [1 ] 1
|
||||
MM Store [65 ] 65
|
||||
MM L2_Replacement [766 ] 766
|
||||
MM L1_to_L2 [800 ] 800
|
||||
MM Trigger_L2_to_L1D [28 ] 28
|
||||
MM Load [6 ] 6
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [69 ] 69
|
||||
MM L2_Replacement [736 ] 736
|
||||
MM L1_to_L2 [771 ] 771
|
||||
MM Trigger_L2_to_L1D [29 ] 29
|
||||
MM Trigger_L2_to_L1I [4 ] 4
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
|
|
@ -338,21 +342,21 @@ OR Flush_line [0 ] 0
|
|||
|
||||
MR Load [0 ] 0
|
||||
MR Ifetch [0 ] 0
|
||||
MR Store [9 ] 9
|
||||
MR L1_to_L2 [43 ] 43
|
||||
MR Store [6 ] 6
|
||||
MR L1_to_L2 [25 ] 25
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [0 ] 0
|
||||
MMR Load [2 ] 2
|
||||
MMR Ifetch [4 ] 4
|
||||
MMR Store [28 ] 28
|
||||
MMR L1_to_L2 [78 ] 78
|
||||
MMR Flush_line [0 ] 0
|
||||
MMR Store [26 ] 26
|
||||
MMR L1_to_L2 [91 ] 91
|
||||
MMR Flush_line [1 ] 1
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [9451 ] 9451
|
||||
IM L1_to_L2 [9582 ] 9582
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
|
|
@ -360,7 +364,7 @@ IM NC_DMA_GETS [0 ] 0
|
|||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [760 ] 760
|
||||
IM Exclusive_Data [734 ] 734
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
|
|
@ -407,25 +411,25 @@ M_W Load [0 ] 0
|
|||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [239 ] 239
|
||||
M_W L1_to_L2 [253 ] 253
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [90 ] 90
|
||||
M_W All_acks_no_sharers [87 ] 87
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [1 ] 1
|
||||
MM_W Store [2 ] 2
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [4486 ] 4486
|
||||
MM_W L1_to_L2 [4505 ] 4505
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [760 ] 760
|
||||
MM_W All_acks_no_sharers [734 ] 734
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [611 ] 611
|
||||
IS L1_to_L2 [525 ] 525
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
|
|
@ -435,7 +439,7 @@ IS Ack [0 ] 0
|
|||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [90 ] 90
|
||||
IS Exclusive_Data [87 ] 87
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
|
|
@ -464,7 +468,7 @@ OI Writeback_Ack [0 ] 0
|
|||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [1 ] 1
|
||||
MI Ifetch [0 ] 0
|
||||
MI Store [2 ] 2
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
|
|
@ -474,7 +478,7 @@ MI Merged_GETS [0 ] 0
|
|||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [842 ] 842
|
||||
MI Writeback_Ack [814 ] 814
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
|
|
@ -514,23 +518,23 @@ OT Complete_L2_to_L1 [0 ] 0
|
|||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [3 ] 3
|
||||
MT Store [1 ] 1
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [81 ] 81
|
||||
MT Complete_L2_to_L1 [9 ] 9
|
||||
MT L1_to_L2 [14 ] 14
|
||||
MT Complete_L2_to_L1 [6 ] 6
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [2 ] 2
|
||||
MMT Store [19 ] 19
|
||||
MMT Load [2 ] 2
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [20 ] 20
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [24 ] 24
|
||||
MMT Complete_L2_to_L1 [32 ] 32
|
||||
MMT L1_to_L2 [77 ] 77
|
||||
MMT Complete_L2_to_L1 [33 ] 33
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [0 ] 0
|
||||
MI_F Writeback_Ack [3 ] 3
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
|
|
@ -547,7 +551,7 @@ MM_F Ack [0 ] 0
|
|||
MM_F All_acks [0 ] 0
|
||||
MM_F All_acks_no_sharers [0 ] 0
|
||||
MM_F Flush_line [0 ] 0
|
||||
MM_F Block_Ack [0 ] 0
|
||||
MM_F Block_Ack [1 ] 1
|
||||
|
||||
IM_F Load [0 ] 0
|
||||
IM_F Ifetch [0 ] 0
|
||||
|
|
@ -561,7 +565,7 @@ IM_F NC_DMA_GETS [0 ] 0
|
|||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [0 ] 0
|
||||
IM_F Exclusive_Data [2 ] 2
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
|
|
@ -610,7 +614,7 @@ MM_WF Store [0 ] 0
|
|||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [0 ] 0
|
||||
MM_WF All_acks_no_sharers [2 ] 2
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
|
|
@ -622,42 +626,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
|
|||
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1614
|
||||
memory_reads: 850
|
||||
memory_writes: 764
|
||||
memory_refreshes: 444
|
||||
memory_total_request_delays: 1136
|
||||
memory_delays_per_request: 0.703841
|
||||
memory_delays_in_input_queue: 148
|
||||
memory_delays_behind_head_of_bank_queue: 4
|
||||
memory_delays_stalled_at_head_of_bank_queue: 984
|
||||
memory_stalls_for_bank_busy: 278
|
||||
memory_total_requests: 1560
|
||||
memory_reads: 824
|
||||
memory_writes: 736
|
||||
memory_refreshes: 429
|
||||
memory_total_request_delays: 1115
|
||||
memory_delays_per_request: 0.714744
|
||||
memory_delays_in_input_queue: 138
|
||||
memory_delays_behind_head_of_bank_queue: 10
|
||||
memory_delays_stalled_at_head_of_bank_queue: 967
|
||||
memory_stalls_for_bank_busy: 228
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 71
|
||||
memory_stalls_for_bus: 363
|
||||
memory_stalls_for_arbitration: 72
|
||||
memory_stalls_for_bus: 362
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 151
|
||||
memory_stalls_for_read_read_turnaround: 121
|
||||
accesses_per_bank: 44 58 47 90 75 58 58 48 47 49 56 50 32 37 53 44 53 47 48 55 53 40 39 41 34 44 54 59 55 47 50 49
|
||||
memory_stalls_for_read_write_turnaround: 186
|
||||
memory_stalls_for_read_read_turnaround: 119
|
||||
accesses_per_bank: 47 55 53 77 82 53 68 47 52 57 48 52 53 45 30 61 44 37 47 47 54 41 43 45 39 47 27 43 41 34 39 52
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [760 ] 760
|
||||
GETS [91 ] 91
|
||||
PUT [889 ] 889
|
||||
GETX [735 ] 735
|
||||
GETS [88 ] 88
|
||||
PUT [864 ] 864
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [848 ] 848
|
||||
UnblockM [820 ] 820
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [78 ] 78
|
||||
Writeback_Exclusive_Dirty [764 ] 764
|
||||
Writeback_Exclusive_Clean [80 ] 80
|
||||
Writeback_Exclusive_Dirty [736 ] 736
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [850 ] 850
|
||||
Memory_Ack [763 ] 763
|
||||
Memory_Data [823 ] 823
|
||||
Memory_Ack [735 ] 735
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
|
|
@ -667,8 +671,8 @@ All_acks_and_shared_data [0 ] 0
|
|||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [0 ] 0
|
||||
PUTF [0 ] 0
|
||||
GETF [3 ] 3
|
||||
PUTF [3 ] 3
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
|
|
@ -681,11 +685,11 @@ NX GETF [0 ] 0
|
|||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [842 ] 842
|
||||
NO PUT [814 ] 814
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [0 ] 0
|
||||
NO GETF [1 ] 1
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
|
|
@ -703,12 +707,12 @@ O DMA_READ [0 ] 0
|
|||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [760 ] 760
|
||||
E GETS [90 ] 90
|
||||
E GETX [735 ] 735
|
||||
E GETS [87 ] 87
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [0 ] 0
|
||||
E GETF [2 ] 2
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
|
|
@ -745,9 +749,9 @@ NO_R GETF [0 ] 0
|
|||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [47 ] 47
|
||||
NO_B PUT [50 ] 50
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [848 ] 848
|
||||
NO_B UnblockM [820 ] 820
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
|
|
@ -801,7 +805,7 @@ NO_B_W UnblockM [0 ] 0
|
|||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [850 ] 850
|
||||
NO_B_W Memory_Data [821 ] 821
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
|
|
@ -928,8 +932,8 @@ WB PUT [0 ] 0
|
|||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [78 ] 78
|
||||
WB Writeback_Exclusive_Dirty [764 ] 764
|
||||
WB Writeback_Exclusive_Clean [80 ] 80
|
||||
WB Writeback_Exclusive_Dirty [736 ] 736
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
|
|
@ -950,7 +954,7 @@ WB_E_W PUT [0 ] 0
|
|||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [763 ] 763
|
||||
WB_E_W Memory_Ack [735 ] 735
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
|
|
@ -959,7 +963,7 @@ NO_F PUT [0 ] 0
|
|||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [0 ] 0
|
||||
NO_F PUTF [3 ] 3
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
|
|
@ -967,6 +971,6 @@ NO_F_W PUT [0 ] 0
|
|||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W Memory_Data [2 ] 2
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 03:42:19
|
||||
gem5 started Jan 23 2012 04:21:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
gem5 compiled Apr 6 2012 14:43:55
|
||||
gem5 started Apr 6 2012 15:58:55
|
||||
gem5 executing on sc2b0605
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
print getting inst port 0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 213131 because Ruby Tester completed
|
||||
Exiting @ tick 205611 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000213 # Number of seconds simulated
|
||||
sim_ticks 213131 # Number of ticks simulated
|
||||
final_tick 213131 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000206 # Number of seconds simulated
|
||||
sim_ticks 205611 # Number of ticks simulated
|
||||
final_tick 205611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 2118201 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214232 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 1440620 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230456 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
|
@ -8,10 +9,15 @@ time_sync_spin_threshold=100000
|
|||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -19,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.sys_port_proxy.port[0]
|
||||
system_port=system.sys_port_proxy.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -75,6 +81,7 @@ issue_latency=2
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -95,23 +102,25 @@ dcache=system.l1_cntrl0.cacheMemory
|
|||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -202,19 +211,23 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
system=system
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.system_port
|
||||
slave=system.system_port
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.l1_cntrl0.sequencer.port[0]
|
||||
cpuDataPort=system.l1_cntrl0.sequencer.slave[0]
|
||||
cpuInstPort=system.l1_cntrl0.sequencer.slave[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/23/2012 04:59:28
|
||||
Real time: Apr/06/2012 15:39:16
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.22
|
||||
Virtual_time_in_minutes: 0.00366667
|
||||
Virtual_time_in_hours: 6.11111e-05
|
||||
Virtual_time_in_days: 2.5463e-06
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
|
||||
Ruby_current_time: 277351
|
||||
Ruby_current_time: 280571
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 277351
|
||||
Ruby_cycles: 280571
|
||||
|
||||
mbytes_resident: 38.8945
|
||||
mbytes_total: 208.887
|
||||
resident_ratio: 0.186199
|
||||
mbytes_resident: 41.168
|
||||
mbytes_total: 224.66
|
||||
resident_ratio: 0.18328
|
||||
|
||||
ruby_cycles_executed: [ 277352 ]
|
||||
ruby_cycles_executed: [ 280572 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -65,16 +65,16 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 997 average: 15.7763 | standard deviation: 1.14597 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 8 90 886 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1000 average: 15.774 | standard deviation: 1.14469 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 8 93 886 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 6224 count: 983 average: 4476.87 | standard deviation: 570.324 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 2 0 2 3 0 2 1 4 3 2 4 9 5 6 7 2 0 12 12 1 15 9 13 19 15 17 26 15 14 15 22 15 27 26 24 26 29 18 22 28 28 18 36 21 21 25 22 24 27 21 26 29 13 19 18 6 19 19 15 12 5 10 11 10 8 5 7 4 4 3 0 2 0 0 0 2 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5442 count: 42 average: 4462.83 | standard deviation: 536.15 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 3 0 1 0 1 1 0 2 1 0 0 0 0 3 1 4 1 0 0 1 0 0 2 1 4 1 0 0 0 0 2 0 0 2 0 0 0 0 1 0 0 1 2 0 0 0 1 1 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 6224 count: 883 average: 4472.62 | standard deviation: 577.868 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 2 0 1 3 0 2 0 4 2 1 4 9 5 4 7 2 0 11 10 1 12 9 11 19 14 15 26 13 11 15 21 14 24 23 21 19 28 17 20 26 28 18 29 20 17 21 21 19 24 19 24 24 12 17 15 6 18 18 14 11 5 9 8 10 8 4 6 3 4 2 0 2 0 0 0 2 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5789 count: 58 average: 4551.81 | standard deviation: 472.973 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 2 0 1 1 3 0 2 3 0 1 2 1 0 0 5 0 0 3 1 5 3 2 0 5 1 0 3 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 5122 count: 40 average: 3916 | standard deviation: 434.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 1 0 2 0 0 1 2 0 3 1 1 0 1 1 0 0 0 2 3 3 2 3 0 1 1 0 0 0 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6224 count: 943 average: 4500.67 | standard deviation: 563.316 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 2 2 0 1 1 2 3 2 3 7 5 3 6 1 0 11 11 1 15 9 11 16 12 15 23 15 13 14 22 15 27 24 23 25 27 18 22 28 28 18 36 21 21 25 22 24 27 21 26 29 13 18 18 6 19 19 15 11 5 10 11 10 8 5 7 4 4 3 0 2 0 0 0 2 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency: [binsize: 32 max: 6185 count: 986 average: 4512.83 | standard deviation: 564.917 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 2 0 1 1 1 0 3 0 1 1 2 5 4 6 5 8 7 2 12 9 11 7 16 19 21 19 24 15 26 28 20 22 22 30 33 30 27 30 31 27 29 27 19 18 31 35 23 21 29 18 15 18 17 12 17 5 13 10 2 9 7 5 6 6 5 5 6 4 1 2 3 1 1 0 3 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5593 count: 43 average: 4526 | standard deviation: 440.983 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 2 2 2 1 1 1 1 1 0 1 1 0 3 1 0 1 1 2 2 1 0 2 1 1 1 2 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 6185 count: 886 average: 4517.13 | standard deviation: 578.837 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 2 0 1 1 1 0 2 0 1 1 2 5 4 6 4 6 4 2 12 9 10 5 15 13 17 16 20 14 20 25 18 21 19 29 32 26 25 26 30 26 26 25 16 17 28 32 21 17 25 17 14 15 16 11 17 5 9 8 2 9 7 5 6 5 5 5 4 4 1 2 3 0 1 0 3 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5314 count: 57 average: 4436.05 | standard deviation: 407.417 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 1 1 4 2 1 3 0 5 2 1 1 2 0 1 1 1 4 0 0 1 0 2 1 1 2 1 3 2 1 0 2 1 0 0 0 3 1 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 5682 count: 39 average: 3989.69 | standard deviation: 543.603 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 2 0 0 1 0 2 1 1 2 1 1 0 3 1 0 0 0 0 1 2 0 0 0 2 1 2 0 1 0 0 2 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6185 count: 947 average: 4534.38 | standard deviation: 555.581 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 3 3 5 3 7 6 2 9 8 11 7 16 19 20 17 24 15 26 26 19 20 22 29 33 30 25 30 30 27 29 27 18 18 29 35 23 21 29 18 15 18 17 11 17 5 13 10 2 9 7 5 6 6 5 5 6 4 1 2 3 1 1 0 2 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -84,13 +84,12 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 943
|
||||
miss_latency_LD_L1Cache: [binsize: 16 max: 3058 count: 1 average: 3058 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5442 count: 41 average: 4497.1 | standard deviation: 494.066 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 3 0 1 0 1 1 0 2 1 0 0 0 0 3 1 4 1 0 0 1 0 0 2 1 4 1 0 0 0 0 2 0 0 2 0 0 0 0 1 0 0 1 2 0 0 0 1 1 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 32 max: 5122 count: 38 average: 3945.16 | standard deviation: 420.627 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 0 1 0 2 0 0 1 2 0 2 1 1 0 1 1 0 0 0 2 3 3 2 3 0 1 1 0 0 0 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6224 count: 845 average: 4496.34 | standard deviation: 572.818 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 2 0 1 0 2 2 1 3 7 5 2 6 1 0 10 9 1 12 9 9 16 11 13 23 13 10 14 21 14 24 21 20 18 26 17 20 26 28 18 29 20 17 21 21 19 24 19 24 24 12 16 15 6 18 18 14 10 5 9 8 10 8 4 6 3 4 2 0 2 0 0 0 2 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 3666 count: 1 average: 3666 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5789 count: 57 average: 4567.35 | standard deviation: 461.996 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 2 0 1 1 3 0 2 3 0 1 2 1 0 0 5 0 0 3 1 5 3 2 0 5 1 0 3 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 947
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5593 count: 43 average: 4526 | standard deviation: 440.983 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 2 2 2 1 1 1 1 1 0 1 1 0 3 1 0 1 1 2 2 1 0 2 1 1 1 2 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 32 max: 5682 count: 37 average: 4008.19 | standard deviation: 551.275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 0 2 1 1 2 0 1 0 3 1 0 0 0 0 1 2 0 0 0 2 1 2 0 1 0 0 2 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6185 count: 849 average: 4539.31 | standard deviation: 570.066 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 3 3 5 2 6 3 2 9 8 10 5 15 13 16 14 20 14 20 23 17 19 19 28 32 26 23 26 29 26 26 25 15 17 26 32 21 17 25 17 14 15 16 10 17 5 9 8 2 9 7 5 6 5 5 5 4 4 1 2 3 0 1 0 2 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 3792 count: 2 average: 3647.5 | standard deviation: 204.355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5314 count: 55 average: 4464.73 | standard deviation: 384.051 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 1 4 2 1 3 0 5 2 1 1 2 0 1 1 1 4 0 0 1 0 2 1 1 2 1 3 2 1 0 2 1 0 0 0 3 1 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -104,11 +103,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 8 count: 1883 average: 0.143919 | standard deviation: 0.683804 | 1778 27 30 26 12 5 3 1 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 8 count: 1883 average: 0.143919 | standard deviation: 0.683804 | 1778 27 30 26 12 5 3 1 1 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 8 count: 1890 average: 0.140212 | standard deviation: 0.700147 | 1792 21 32 25 7 8 1 1 3 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 8 count: 1890 average: 0.140212 | standard deviation: 0.700147 | 1792 21 32 25 7 8 1 1 3 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 6 count: 943 average: 0.19088 | standard deviation: 0.752914 | 867 25 22 15 7 4 3 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 940 average: 0.0968085 | standard deviation: 0.604386 | 911 2 8 11 5 1 0 1 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 947 average: 0.198522 | standard deviation: 0.78638 | 871 19 27 18 5 5 0 0 2 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 943 average: 0.0816543 | standard deviation: 0.596344 | 921 2 5 7 2 3 1 1 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -122,145 +121,145 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10335
|
||||
page_faults: 0
|
||||
page_reclaims: 11677
|
||||
page_faults: 1
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 72
|
||||
block_inputs: 624
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 2829 22632
|
||||
total_msg_count_Data: 2820 203040
|
||||
total_msg_count_Response_Data: 2829 203688
|
||||
total_msg_count_Writeback_Control: 2820 22560
|
||||
total_msgs: 11298 total_bytes: 451920
|
||||
total_msg_count_Control: 2841 22728
|
||||
total_msg_count_Data: 2833 203976
|
||||
total_msg_count_Response_Data: 2841 204552
|
||||
total_msg_count_Writeback_Control: 2829 22632
|
||||
total_msgs: 11344 total_bytes: 453888
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.69731
|
||||
links_utilized_percent_switch_0_link_0: 1.69947 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.69514 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 1.68505
|
||||
links_utilized_percent_switch_0_link_0: 1.68692 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.68317 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 943 67896 [ 0 0 0 0 943 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 940 7520 [ 0 0 0 940 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 945 68040 [ 0 0 945 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.69731
|
||||
links_utilized_percent_switch_1_link_0: 1.69514 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.69947 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 1.68487
|
||||
links_utilized_percent_switch_1_link_0: 1.68282 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.68692 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 943 67896 [ 0 0 0 0 943 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 940 7520 [ 0 0 0 940 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 944 67968 [ 0 0 944 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.69731
|
||||
links_utilized_percent_switch_2_link_0: 1.69947 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.69514 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.68487
|
||||
links_utilized_percent_switch_2_link_0: 1.68692 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.68282 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 943 67896 [ 0 0 0 0 943 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 940 7520 [ 0 0 0 940 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 943 7544 [ 0 0 943 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 940 67680 [ 0 0 940 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 944 67968 [ 0 0 944 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 945
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 945
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 949
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 949
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 4.33862%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 89.5238%
|
||||
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 6.13757%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 4.63646%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 89.568%
|
||||
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 5.79557%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 945 100%
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 949 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [42 ] 42
|
||||
Ifetch [59 ] 59
|
||||
Store [884 ] 884
|
||||
Data [943 ] 943
|
||||
Load [44 ] 44
|
||||
Ifetch [57 ] 57
|
||||
Store [887 ] 887
|
||||
Data [947 ] 947
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [942 ] 942
|
||||
Writeback_Ack [940 ] 940
|
||||
Replacement [946 ] 946
|
||||
Writeback_Ack [943 ] 943
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [41 ] 41
|
||||
I Ifetch [58 ] 58
|
||||
I Store [846 ] 846
|
||||
I Load [44 ] 44
|
||||
I Ifetch [55 ] 55
|
||||
I Store [850 ] 850
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [1 ] 1
|
||||
M Ifetch [1 ] 1
|
||||
M Store [38 ] 38
|
||||
M Load [0 ] 0
|
||||
M Ifetch [2 ] 2
|
||||
M Store [37 ] 37
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [942 ] 942
|
||||
M Replacement [946 ] 946
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [940 ] 940
|
||||
MI Writeback_Ack [943 ] 943
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [98 ] 98
|
||||
|
||||
IM Data [845 ] 845
|
||||
IM Data [849 ] 849
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1883
|
||||
memory_reads: 943
|
||||
memory_writes: 940
|
||||
memory_refreshes: 578
|
||||
memory_total_request_delays: 2832
|
||||
memory_delays_per_request: 1.50398
|
||||
memory_delays_in_input_queue: 707
|
||||
memory_delays_behind_head_of_bank_queue: 5
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2120
|
||||
memory_stalls_for_bank_busy: 238
|
||||
memory_total_requests: 1891
|
||||
memory_reads: 947
|
||||
memory_writes: 944
|
||||
memory_refreshes: 585
|
||||
memory_total_request_delays: 2814
|
||||
memory_delays_per_request: 1.4881
|
||||
memory_delays_in_input_queue: 676
|
||||
memory_delays_behind_head_of_bank_queue: 12
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2126
|
||||
memory_stalls_for_bank_busy: 294
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 276
|
||||
memory_stalls_for_bus: 930
|
||||
memory_stalls_for_arbitration: 265
|
||||
memory_stalls_for_bus: 935
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 552
|
||||
memory_stalls_for_read_read_turnaround: 124
|
||||
accesses_per_bank: 58 56 64 106 113 56 57 46 52 52 46 52 62 66 52 50 52 62 56 50 76 64 47 60 68 62 44 56 48 58 48 44
|
||||
memory_stalls_for_read_write_turnaround: 518
|
||||
memory_stalls_for_read_read_turnaround: 114
|
||||
accesses_per_bank: 46 50 40 88 149 74 58 50 50 48 58 62 54 60 56 58 60 62 54 54 63 54 56 44 54 77 52 48 46 62 46 58
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [943 ] 943
|
||||
GETX [947 ] 947
|
||||
GETS [0 ] 0
|
||||
PUTX [940 ] 940
|
||||
PUTX [944 ] 944
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [943 ] 943
|
||||
Memory_Ack [940 ] 940
|
||||
Memory_Data [947 ] 947
|
||||
Memory_Ack [944 ] 944
|
||||
|
||||
- Transitions -
|
||||
I GETX [943 ] 943
|
||||
I GETX [947 ] 947
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [940 ] 940
|
||||
M PUTX [944 ] 944
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
|
@ -283,7 +282,7 @@ IM PUTX [0 ] 0
|
|||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [943 ] 943
|
||||
IM Memory_Data [947 ] 947
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
|
|
@ -291,7 +290,7 @@ MI PUTX [0 ] 0
|
|||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [940 ] 940
|
||||
MI Memory_Ack [944 ] 944
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:48:33
|
||||
gem5 started Jan 23 2012 04:59:28
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby
|
||||
gem5 compiled Apr 6 2012 14:39:05
|
||||
gem5 started Apr 6 2012 15:39:15
|
||||
gem5 executing on sc2b0605
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
print getting inst port 0
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 277351 because Ruby Tester completed
|
||||
Exiting @ tick 280571 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000277 # Number of seconds simulated
|
||||
sim_ticks 277351 # Number of ticks simulated
|
||||
final_tick 277351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000281 # Number of seconds simulated
|
||||
sim_ticks 280571 # Number of ticks simulated
|
||||
final_tick 280571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 3834985 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213904 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 2823981 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230056 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
|
|||
Loading…
Reference in a new issue