Updated FastCPU model with all the recent changes.
arch/alpha/ev5.cc: Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future. arch/isa_parser.py: Added in FastCPU model. --HG-- extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
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@ -153,8 +153,10 @@ void
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AlphaISA::zeroRegisters(XC *xc)
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{
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// Insure ISA semantics
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xc->setIntReg(ZeroReg, 0);
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xc->setFloatRegDouble(ZeroReg, 0.0);
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// (no longer very clean due to the change in setIntReg() in the
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// cpu model. Consider changing later.)
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xc->xc->setIntReg(ZeroReg, 0);
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xc->xc->setFloatRegDouble(ZeroReg, 0.0);
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}
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void
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@ -630,6 +630,9 @@ class CpuModel:
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CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
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'#include "cpu/simple_cpu/simple_cpu.hh"',
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{ 'CPU_exec_context': 'SimpleCPU' })
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CpuModel('FastCPU', 'fast_cpu_exec.cc',
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'#include "cpu/fast_cpu/fast_cpu.hh"',
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{ 'CPU_exec_context': 'FastCPU' })
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CpuModel('FullCPU', 'full_cpu_exec.cc',
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'#include "cpu/full_cpu/dyn_inst.hh"',
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{ 'CPU_exec_context': 'DynInst' })
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