The beginnings of an instruction format to deal with block loads and stores. This takes advantage of microcode.
--HG-- extra : convert_revision : ac912df76c781f40fc462f314451148c5cdfaf43
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Gabe Black
parent
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commit
6943c731ea
1 changed files with 370 additions and 0 deletions
370
src/arch/sparc/isa/formats/blockmem.isa
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370
src/arch/sparc/isa/formats/blockmem.isa
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@ -0,0 +1,370 @@
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////////////////////////////////////////////////////////////////////
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//
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// Block Memory instructions
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//
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output header {{
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class BlockMem : public SparcMacroInst
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{
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protected:
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// Constructor
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// We make the assumption that all block memory operations
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// Will take 8 instructions to execute
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BlockMem(const char *mnem,
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ExtMachInst _machInst, OpClass __opClass) :
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SparcMacroInst(mnem, _machInst, __opClass, 8)
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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class BlockMemImm : public BlockMem
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{
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protected:
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// Constructor
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BlockMemImm(const char *mnem,
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ExtMachInst _machInst, OpClass __opClass) :
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BlockMem(mnem, _machInst, __opClass),
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imm(sext<13>(SIMM13))
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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const int32_t imm;
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};
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class BlockMemMicro : public SparcDelayedMicroInst
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{
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protected:
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// Constructor
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BlockMemMicro(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, int8_t _offset) :
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SparcDelayedMicroInst(mnem, _machInst, __opClass),
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offset(_offset)
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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const int8_t offset;
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};
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class BlockMemImmMicro : public BlockMemMicro
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{
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protected:
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// Constructor
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BlockMemImmMicro(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, int8_t _offset) :
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BlockMemMicro(mnem, _machInst, __opClass, _offset),
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imm(sext<13>(SIMM13))
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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const int32_t imm;
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};
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}};
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output decoder {{
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std::string BlockMem::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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bool load = flags[IsLoad];
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bool save = flags[IsStore];
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printMnemonic(response, mnemonic);
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if(save)
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{
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printReg(response, _srcRegIdx[0]);
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ccprintf(response, ", ");
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[!save ? 0 : 1]);
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ccprintf(response, " + ");
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printReg(response, _srcRegIdx[!save ? 1 : 2]);
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ccprintf(response, " ]");
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if(load)
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{
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ccprintf(response, ", ");
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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std::string BlockMemImm::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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bool load = flags[IsLoad];
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bool save = flags[IsStore];
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printMnemonic(response, mnemonic);
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if(save)
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{
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printReg(response, _srcRegIdx[0]);
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ccprintf(response, ", ");
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[!save ? 0 : 1]);
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if(imm >= 0)
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ccprintf(response, " + 0x%x ]", imm);
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else
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ccprintf(response, " + -0x%x ]", -imm);
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if(load)
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{
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ccprintf(response, ", ");
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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}};
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def template LoadStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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uint64_t write_result = 0;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(priv_check)s;
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%(ea_code)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
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%(code)s;
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if(fault == NoFault)
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{
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xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template BlockMemDeclare {{
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/**
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* Static instruction class for a block memory operation
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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//Constructor
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%(class_name)s(MachInst machInst);
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class %(class_name)s_0 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_0(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[0]",
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machInst, %(op_class)s, 0*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_1 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_1(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[1]",
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machInst, %(op_class)s, 1*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_2 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_2(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[2]",
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machInst, %(op_class)s, 2*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_3 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_3(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[3]",
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machInst, %(op_class)s, 3*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_4 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_4(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[4]",
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machInst, %(op_class)s, 4*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_5 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_5(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[5]",
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machInst, %(op_class)s, 5*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_6 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_6(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[6]",
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machInst, %(op_class)s, 6*8)
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{;}
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%(BasicExecDeclare)s
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};
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class %(class_name)s_7 : public %(base_class)sMicro
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{
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//Constructor
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%(class_name)s_7(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[7]",
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machInst, %(op_class)s, 7*8)
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{
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flags[IsLastMicroOp] = true;
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}
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%(BasicExecDeclare)s
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};
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};
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}};
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// Basic instruction class constructor template.
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def template BlockMemConstructor {{
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inline %(class_name)s::%(class_name)s(MachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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microOps =
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{new %(class_name)s_0(machInst),
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new %(class_name)s_1(machInst),
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new %(class_name)s_2(machInst),
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new %(class_name)s_3(machInst),
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new %(class_name)s_4(machInst),
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new %(class_name)s_5(machInst),
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new %(class_name)s_6(machInst),
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new %(class_name)s_7(machInst)}
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}
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}};
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def template MicroLoadExecute {{
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Fault %(class_name)s_%(micro_pc)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(fault_check)s;
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%(ea_code)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
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%(code)s;
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroStoreExecute {{
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Fault %(class_name)s_%(micro_pc)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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uint64_t write_result = 0;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(fault_check)s;
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%(ea_code)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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%(code)s;
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if(fault == NoFault)
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{
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xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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let {{
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def doBlockMemFormat(code, execute, name, Name, opt_flags):
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# XXX Need to take care of pstate.hpriv as well. The lower ASIs
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# are split into ones that are available in priv and hpriv, and
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# those that are only available in hpriv
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faultCheck = '''if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
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return new PrivilegedAction;
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if(AsiIsAsIfUser(EXT_ASI) && !bits(Pstate,2,2))
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return new PrivilegedAction;
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if(RD & 0xf)
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return new IllegalInstruction;
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if(EA & 0x3f)
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return new MemAddressNotAligned;'''
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addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
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addrCalcImm = 'EA = Rs1 + imm + offset;'
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iop = InstObjParams(name, Name, 'Mem', code, opt_flags)
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iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code, opt_flags)
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header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
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decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
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decode_block = ROrImmDecode.subst(iop)
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for microPC in range(8):
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pcedCode = code % ("micro_pc", microPC)
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iop = InstObjParams(name, Name, 'Mem', pcedCode,
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opt_flags, ("ea_code", addrCalcReg),
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("fault_check", faultCheck), ("micro_pc", microPC))
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iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', pcedCode,
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opt_flags, ("ea_code", addrCalcImm),
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("fault_check", faultCheck), ("micro_pc", microPC))
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exec_output += execute.subst(iop)
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exec_output += execute.subst(iop_imm)
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faultCheck = ''
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return (header_output, decoder_output, exec_output, decode_block)
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}};
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def format BlockLoad(code, *opt_flags) {{
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doBlockMemFormat(code, MicroLoadExecute,
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name, Name, opt_flags)
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}};
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def format BlockStore(code, *opt_flags) {{
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doBlockMemFormat(code, MicroStoreExecute,
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name, Name, opt_flags)
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}};
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