Move around misc reg code
src/arch/sparc/faults.cc: Moved some code here from miscregfile.cc src/arch/sparc/miscregfile.cc: Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc src/arch/sparc/miscregfile.hh: readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect. --HG-- extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
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3 changed files with 134 additions and 51 deletions
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@ -33,12 +33,13 @@
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "base/bitfield.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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#include "arch/sparc/process.hh"
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#include "mem/page_table.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#include "sim/process.hh"
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#endif
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#endif
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@ -361,6 +362,39 @@ void SparcFault::invoke(ThreadContext * tc)
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//Use the SPARC trap state machine
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//Use the SPARC trap state machine
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}
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}
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void PowerOnReset::invoke(ThreadContext * tc)
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{
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//For SPARC, when a system is first started, there is a power
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//on reset Trap which sets the processor into the following state.
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//Bits that aren't set aren't defined on startup.
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/*
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tl = MaxTL;
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gl = MaxGL;
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tickFields.counter = 0; //The TICK register is unreadable bya
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tickFields.npt = 1; //The TICK register is unreadable by by !priv
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softint = 0; // Clear all the soft interrupt bits
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tick_cmprFields.int_dis = 1; // disable timer compare interrupts
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tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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stickFields.npt = 1; //The TICK register is unreadable by by !priv
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stick_cmprFields.int_dis = 1; // disable timer compare interrupts
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stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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tt[tl] = _trapType;
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pstate = 0; // fields 0 but pef
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pstateFields.pef = 1;
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hpstate = 0;
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hpstateFields.red = 1;
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hpstateFields.hpriv = 1;
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hpstateFields.tlz = 0; // this is a guess
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hintp = 0; // no interrupts pending
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hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
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hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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*/
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}
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#endif
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#endif
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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@ -31,9 +31,14 @@
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#include "arch/sparc/miscregfile.hh"
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#include "arch/sparc/miscregfile.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#if FULL_SYSTEM
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#include "arch/sparc/system.hh"
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#endif
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using namespace SparcISA;
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using namespace SparcISA;
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using namespace std;
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using namespace std;
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@ -55,51 +60,8 @@ string SparcISA::getMiscRegName(RegIndex index)
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return miscRegName[index];
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return miscRegName[index];
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}
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}
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#if FULL_SYSTEM
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//XXX These need an implementation someplace
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/** Fullsystem only register version of ReadRegWithEffect() */
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MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext *tc);
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/** Fullsystem only register version of SetRegWithEffect() */
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void MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext * tc);
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#endif
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void MiscRegFile::reset()
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void MiscRegFile::reset()
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{
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{
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//pstateFields.pef = 0; //No FPU
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//pstateFields.pef = 1; //FPU
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#if FULL_SYSTEM
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//For SPARC, when a system is first started, there is a power
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//on reset Trap which sets the processor into the following state.
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//Bits that aren't set aren't defined on startup.
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//XXX this code should be moved into the POR fault.
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tl = MaxTL;
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gl = MaxGL;
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tickFields.counter = 0; //The TICK register is unreadable bya
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tickFields.npt = 1; //The TICK register is unreadable by by !priv
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softint = 0; // Clear all the soft interrupt bits
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tick_cmprFields.int_dis = 1; // disable timer compare interrupts
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tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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stickFields.npt = 1; //The TICK register is unreadable by by !priv
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stick_cmprFields.int_dis = 1; // disable timer compare interrupts
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stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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tt[tl] = power_on_reset;
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pstate = 0; // fields 0 but pef
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pstateFields.pef = 1;
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hpstate = 0;
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hpstateFields.red = 1;
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hpstateFields.hpriv = 1;
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hpstateFields.tlz = 0; // this is a guess
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hintp = 0; // no interrupts pending
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hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
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hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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#endif
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}
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}
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MiscReg MiscRegFile::readReg(int miscReg)
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MiscReg MiscRegFile::readReg(int miscReg)
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@ -199,10 +161,20 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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case MISCREG_PCR:
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case MISCREG_PCR:
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case MISCREG_PIC:
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case MISCREG_PIC:
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panic("Performance Instrumentation not impl\n");
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panic("Performance Instrumentation not impl\n");
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/** Floating Point Status Register */
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/** Floating Point Status Register */
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case MISCREG_FSR:
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case MISCREG_FSR:
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panic("Floating Point not implemented\n");
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panic("Floating Point not implemented\n");
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//We'll include this only in FS so we don't need the SparcSystem type around
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//in SE.
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#if FULL_SYSTEM
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case MISCREG_STICK:
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SparcSystem *sys;
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sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
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assert(sys != NULL);
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return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
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#endif
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case MISCREG_HVER:
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return NWindows | MaxTL << 8 | MaxGL << 16;
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}
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}
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return readReg(miscReg);
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return readReg(miscReg);
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}
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}
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@ -350,6 +322,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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const MiscReg &val, ThreadContext * tc)
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const MiscReg &val, ThreadContext * tc)
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{
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{
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const uint64_t Bit64 = (1ULL << 63);
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const uint64_t Bit64 = (1ULL << 63);
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uint64_t time;
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#if FULL_SYSTEM
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SparcSystem *sys;
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#endif
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switch (miscReg) {
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switch (miscReg) {
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case MISCREG_TICK:
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case MISCREG_TICK:
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tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
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tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
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@ -375,6 +351,68 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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case MISCREG_GL:
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case MISCREG_GL:
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tc->changeRegFileContext(CONTEXT_GLOBALS, val);
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tc->changeRegFileContext(CONTEXT_GLOBALS, val);
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break;
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break;
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case MISCREG_SOFTINT:
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//We need to inject interrupts, and or notify the interrupt
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//object that it needs to use a different interrupt level.
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//Any newly appropriate interrupts will happen when the cpu gets
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//around to checking for them. This might not be quite what we
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//want.
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break;
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case MISCREG_SOFTINT_CLR:
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//Do whatever this is supposed to do...
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break;
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case MISCREG_SOFTINT_SET:
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//Do whatever this is supposed to do...
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break;
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case MISCREG_TICK_CMPR:
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if (tickCompare == NULL)
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tickCompare = new TickCompareEvent(this, tc);
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setReg(miscReg, val);
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if (tick_cmprFields.int_dis && tickCompare->scheduled())
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tickCompare->deschedule();
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time = tick_cmprFields.tick_cmpr - tickFields.counter;
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if (!tick_cmprFields.int_dis && time > 0)
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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break;
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case MISCREG_PIL:
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//We need to inject interrupts, and or notify the interrupt
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//object that it needs to use a different interrupt level.
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//Any newly appropriate interrupts will happen when the cpu gets
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//around to checking for them. This might not be quite what we
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//want.
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break;
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//We'll include this only in FS so we don't need the SparcSystem type around
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//in SE.
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#if FULL_SYSTEM
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case MISCREG_STICK:
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sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
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assert(sys != NULL);
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sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
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stickFields.npt = val & Bit64 ? 1 : 0;
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break;
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case MISCREG_STICK_CMPR:
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if (sTickCompare == NULL)
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sTickCompare = new STickCompareEvent(this, tc);
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sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
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assert(sys != NULL);
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if (stick_cmprFields.int_dis && sTickCompare->scheduled())
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sTickCompare->deschedule();
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time = stick_cmprFields.tick_cmpr - sys->sysTick;
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if (!stick_cmprFields.int_dis && time > 0)
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sTickCompare->schedule(time * Clock::Int::ns);
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break;
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case MISCREG_HSTICK_CMPR:
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if (hSTickCompare == NULL)
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hSTickCompare = new HSTickCompareEvent(this, tc);
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sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
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assert(sys != NULL);
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if (hstick_cmprFields.int_dis && hSTickCompare->scheduled())
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hSTickCompare->deschedule();
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int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
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if (!hstick_cmprFields.int_dis && time > 0)
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hSTickCompare->schedule(time * Clock::Int::ns);
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break;
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#endif
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}
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}
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setReg(miscReg, val);
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setReg(miscReg, val);
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}
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}
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@ -444,3 +482,20 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
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implicitDataAsi = (ASI)temp;
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implicitDataAsi = (ASI)temp;
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}
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}
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void
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MiscRegFile::processTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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}
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void
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MiscRegFile::processSTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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}
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void
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MiscRegFile::processHSTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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}
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@ -354,12 +354,6 @@ namespace SparcISA
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typedef CpuEventWrapper<MiscRegFile,
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
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&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
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HSTickCompareEvent *hSTickCompare;
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HSTickCompareEvent *hSTickCompare;
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/** Fullsystem only register version of ReadRegWithEffect() */
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MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
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/** Fullsystem only register version of SetRegWithEffect() */
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Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext * tc);
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#endif
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#endif
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public:
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public:
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