ARM: Implement zero/sign extend instructions.
This commit is contained in:
Gabe Black
parent
554fb3774e
commit
69365876d8
1 changed files with 142 additions and 0 deletions
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@ -227,4 +227,146 @@ let {{
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header_output += RegImmRegOpDeclare.subst(usat16Iop)
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header_output += RegImmRegOpDeclare.subst(usat16Iop)
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decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
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decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
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exec_output += PredOpExecute.subst(usat16Iop)
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exec_output += PredOpExecute.subst(usat16Iop)
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sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
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{ "code":
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"Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxtbIop)
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decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
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exec_output += PredOpExecute.subst(sxtbIop)
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sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
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{ "code":
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'''
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Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
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Op1;
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''',
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
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exec_output += PredOpExecute.subst(sxtabIop)
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sxtb16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
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replaceBits(resTemp, 31, 16,
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sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
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Dest = resTemp;
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'''
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sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
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{ "code": sxtb16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
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decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
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exec_output += PredOpExecute.subst(sxtb16Iop)
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sxtab16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
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bits(Op1, 15, 0));
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replaceBits(resTemp, 31, 16,
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sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
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bits(Op1, 31, 16));
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Dest = resTemp;
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'''
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sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
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{ "code": sxtab16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
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exec_output += PredOpExecute.subst(sxtab16Iop)
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sxthCode = '''
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uint64_t rotated = (uint32_t)Op1;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = sext<16>((uint16_t)rotated);
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'''
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sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
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{ "code": sxthCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxthIop)
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decoder_output += RegImmRegOpConstructor.subst(sxthIop)
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exec_output += PredOpExecute.subst(sxthIop)
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sxtahCode = '''
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uint64_t rotated = (uint32_t)Op2;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = sext<16>((uint16_t)rotated) + Op1;
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'''
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sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
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{ "code": sxtahCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
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exec_output += PredOpExecute.subst(sxtahIop)
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uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
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{ "code": "Dest = (uint8_t)(Op1.ud >> imm);",
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(uxtbIop)
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decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
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exec_output += PredOpExecute.subst(uxtbIop)
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uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
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{ "code":
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"Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
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decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
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exec_output += PredOpExecute.subst(uxtabIop)
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uxtb16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
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replaceBits(resTemp, 31, 16,
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(uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
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Dest = resTemp;
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'''
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uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
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{ "code": uxtb16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
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decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
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exec_output += PredOpExecute.subst(uxtb16Iop)
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uxtab16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
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bits(Op1, 15, 0));
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replaceBits(resTemp, 31, 16,
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(uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
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bits(Op1, 31, 16));
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Dest = resTemp;
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'''
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uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
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{ "code": uxtab16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
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decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
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exec_output += PredOpExecute.subst(uxtab16Iop)
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uxthCode = '''
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uint64_t rotated = (uint32_t)Op1;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = (uint16_t)rotated;
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'''
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uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
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{ "code": uxthCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(uxthIop)
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decoder_output += RegImmRegOpConstructor.subst(uxthIop)
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exec_output += PredOpExecute.subst(uxthIop)
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uxtahCode = '''
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uint64_t rotated = (uint32_t)Op2;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = (uint16_t)rotated + Op1;
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'''
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uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
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{ "code": uxtahCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
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decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
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exec_output += PredOpExecute.subst(uxtahIop)
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}};
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}};
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