Ruby Memory Controller: Fix clocking
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494f6a858e
commit
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6 changed files with 20 additions and 17 deletions
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@ -42,7 +42,7 @@
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#include "mem/ruby/system/System.hh"
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using namespace std;
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MemoryControl::MemoryControl(const Params *p) : SimObject(p), m_event(this)
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MemoryControl::MemoryControl(const Params *p) : ClockedObject(p), m_event(this)
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{
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g_system_ptr->registerMemController(this);
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}
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@ -34,24 +34,29 @@
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#include <list>
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#include <string>
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#include "mem/protocol/MemoryMsg.hh"
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#include "mem/protocol/MemoryControlRequestType.hh"
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#include "mem/protocol/MemoryMsg.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/profiler/MemCntrlProfiler.hh"
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#include "mem/ruby/slicc_interface/Message.hh"
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#include "mem/ruby/system/AbstractMemOrCache.hh"
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#include "mem/ruby/system/MemoryNode.hh"
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#include "mem/ruby/system/System.hh"
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#include "sim/sim_object.hh"
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#include "params/MemoryControl.hh"
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#include "sim/clocked_object.hh"
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//////////////////////////////////////////////////////////////////////////////
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class Consumer;
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class MemoryControl :
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public SimObject, public Consumer, public AbstractMemOrCache
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public ClockedObject, public Consumer, public AbstractMemOrCache
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{
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public:
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typedef MemoryControlParams Params;
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const Params *params() const
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{ return dynamic_cast<const Params *>(_params); }
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MemoryControl(const Params *p);
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virtual void init() = 0;
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virtual void reset() = 0;
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@ -28,13 +28,11 @@
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# Brad Beckmann
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from m5.params import *
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from m5.SimObject import SimObject
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from ClockedObject import ClockedObject
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class MemoryControl(SimObject):
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class MemoryControl(ClockedObject):
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abstract = True
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type = 'MemoryControl'
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cxx_class = 'MemoryControl'
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version = Param.Int("");
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ruby_system = Param.RubySystem("")
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mem_bus_cycle_multiplier = Param.Int(10, "");
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@ -149,7 +149,6 @@ operator<<(ostream& out, const RubyMemoryControl& obj)
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RubyMemoryControl::RubyMemoryControl(const Params *p)
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: MemoryControl(p)
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{
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m_mem_bus_cycle_multiplier = p->mem_bus_cycle_multiplier;
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m_banks_per_rank = p->banks_per_rank;
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m_ranks_per_dimm = p->ranks_per_dimm;
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m_dimms_per_channel = p->dimms_per_channel;
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@ -309,7 +308,7 @@ RubyMemoryControl::enqueueMemRef(MemoryNode& memRef)
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m_input_queue.push_back(memRef);
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if (!m_event.scheduled()) {
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schedule(m_event, curTick() + 1);
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schedule(m_event, nextCycle());
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}
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}
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@ -377,17 +376,17 @@ RubyMemoryControl::printStats(ostream& out) const
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void
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RubyMemoryControl::enqueueToDirectory(MemoryNode req, int latency)
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{
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Time arrival_time = g_system_ptr->getTime()
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+ (latency * m_mem_bus_cycle_multiplier);
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req.m_time = arrival_time;
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Time arrival_time = curTick() + (latency * clock);
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Time ruby_arrival_time = arrival_time / g_system_ptr->getClock();
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req.m_time = ruby_arrival_time;
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m_response_queue.push_back(req);
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DPRINTF(RubyMemory, "Enqueueing msg %#08x %c back to directory at %15d\n",
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req.m_addr, req.m_is_mem_read ? 'R':'W',
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arrival_time * g_system_ptr->getClock());
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arrival_time);
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// schedule the wake up
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m_consumer_ptr->scheduleEventAbsolute(arrival_time);
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m_consumer_ptr->scheduleEventAbsolute(ruby_arrival_time);
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}
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// getBank returns an integer that is unique for each
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@ -705,7 +704,7 @@ RubyMemoryControl::wakeup()
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m_idleCount--;
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if (m_idleCount > 0) {
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assert(!m_event.scheduled());
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schedule(m_event, curTick() + m_mem_bus_cycle_multiplier);
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schedule(m_event, curTick() + clock);
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}
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}
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@ -116,7 +116,6 @@ class RubyMemoryControl : public MemoryControl
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std::string m_description;
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int m_msg_counter;
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int m_mem_bus_cycle_multiplier;
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int m_banks_per_rank;
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int m_ranks_per_dimm;
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int m_dimms_per_channel;
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@ -36,6 +36,8 @@ class RubyMemoryControl(MemoryControl):
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cxx_class = 'RubyMemoryControl'
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version = Param.Int("");
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# Override the default clock
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clock = '400MHz'
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banks_per_rank = Param.Int(8, "");
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ranks_per_dimm = Param.Int(2, "");
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dimms_per_channel = Param.Int(2, "");
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