Eliminated TARGET_ALPHA, since THE_ISA provides the same function.
--HG-- extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
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4 changed files with 6 additions and 8 deletions
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@ -43,8 +43,6 @@ class FastCPU;
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class FullCPU;
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class Checkpoint;
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#define TARGET_ALPHA
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class StaticInst;
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class StaticInstPtr;
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@ -284,7 +284,7 @@ class CPUExecContext
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template <class T>
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Fault read(CpuRequestPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
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if (req->flags & LOCKED) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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@ -300,7 +300,7 @@ class CPUExecContext
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template <class T>
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Fault write(CpuRequestPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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@ -208,7 +208,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
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if (req->flags & LOCKED) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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@ -230,7 +230,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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@ -941,9 +941,9 @@ SimpleCPU::tick()
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// maintain $r0 semantics
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cpuXC->setIntReg(ZeroReg, 0);
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#ifdef TARGET_ALPHA
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#if THE_ISA == ALPHA_ISA
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cpuXC->setFloatRegDouble(ZeroReg, 0.0);
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#endif // TARGET_ALPHA
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#endif // ALPHA_ISA
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if (status() == IcacheAccessComplete) {
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// We've already fetched an instruction and were stalled on an
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