sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Eliminated TARGET_ALPHA, since THE_ISA provides the same function.

Browse source 
--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
This commit is contained in:
Gabe Black 2006-03-10 16:26:31 -05:00
parent e3d96aa889
commit 68d7382cf3
4 changed files with 6 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/alpha/isa_traits.hh
View file

@ -43,8 +43,6 @@ class FastCPU;
class FullCPU; class FullCPU;
class Checkpoint; class Checkpoint;
#define TARGET_ALPHA
class StaticInst; class StaticInst;
class StaticInstPtr; class StaticInstPtr;

4
cpu/cpu_exec_context.hh
View file

@ -284,7 +284,7 @@ class CPUExecContext
template <class T> template <class T>
Fault read(CpuRequestPtr &req, T &data) Fault read(CpuRequestPtr &req, T &data)
{ {
#if FULL_SYSTEM && defined(TARGET_ALPHA) #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
if (req->flags & LOCKED) { if (req->flags & LOCKED) {
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
@ -300,7 +300,7 @@ class CPUExecContext
template <class T> template <class T>
Fault write(CpuRequestPtr &req, T &data) Fault write(CpuRequestPtr &req, T &data)
{ {
#if FULL_SYSTEM && defined(TARGET_ALPHA) #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
ExecContext *xc; ExecContext *xc;
// If this is a store conditional, act appropriately // If this is a store conditional, act appropriately

4
cpu/o3/alpha_cpu.hh
View file

@ -208,7 +208,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T> template <class T>
Fault read(MemReqPtr &req, T &data) Fault read(MemReqPtr &req, T &data)
{ {
#if FULL_SYSTEM && defined(TARGET_ALPHA) #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
if (req->flags & LOCKED) { if (req->flags & LOCKED) {
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
@ -230,7 +230,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T> template <class T>
Fault write(MemReqPtr &req, T &data) Fault write(MemReqPtr &req, T &data)
{ {
#if FULL_SYSTEM && defined(TARGET_ALPHA) #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
ExecContext *xc; ExecContext *xc;
// If this is a store conditional, act appropriately // If this is a store conditional, act appropriately

4
cpu/simple/cpu.cc
View file

@ -941,9 +941,9 @@ SimpleCPU::tick()
// maintain $r0 semantics // maintain $r0 semantics
cpuXC->setIntReg(ZeroReg, 0); cpuXC->setIntReg(ZeroReg, 0);
#ifdef TARGET_ALPHA #if THE_ISA == ALPHA_ISA
cpuXC->setFloatRegDouble(ZeroReg, 0.0); cpuXC->setFloatRegDouble(ZeroReg, 0.0);
#endif // TARGET_ALPHA #endif // ALPHA_ISA
if (status() == IcacheAccessComplete) { if (status() == IcacheAccessComplete) {
// We've already fetched an instruction and were stalled on an // We've already fetched an instruction and were stalled on an