sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

move the twinx loads to the correct opcode and add asis 0x24 and 0x27

Browse source 
Make the TLB ok to translate QUAD_LDD

src/arch/sparc/isa/decoder.isa:
    move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
    Make QUAD_LDD asi ok to execute

--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
This commit is contained in:
Ali Saidi 2006-12-18 03:37:52 -05:00
parent e65544b88b
commit 6841f863c5
2 changed files with 28 additions and 17 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

42
src/arch/sparc/isa/decoder.isa
View file

@ -1060,11 +1060,31 @@ decode OP default Unknown::unknown()
0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
0x13: ldtwa({{ 0x13: decode EXT_ASI {
uint64_t val = Mem.udw; //ASI_QUAD_LDD
RdLow = val<31:0>; 0x24: TwinLoad::ldtx_quad_ldd(
RdHigh = val<63:32>; {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
}}, {{EXT_ASI}}); //ASI_LDTX_REAL
0x26: TwinLoad::ldtx_real(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_N
0x27: TwinLoad::ldtx_n(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_L
0x2C: TwinLoad::ldtx_l(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_REAL_L
0x2E: TwinLoad::ldtx_real_l(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_N_L
0x2F: TwinLoad::ldtx_n_l(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
default: ldtwa({{
uint64_t val = Mem.udw;
RdLow = val<31:0>;
RdHigh = val<63:32>;
}}, {{EXT_ASI}});
}
} }
format StoreAlt { format StoreAlt {
0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
@ -1126,18 +1146,6 @@ decode OP default Unknown::unknown()
0x15: FailUnimpl::lddfa_real_io(); 0x15: FailUnimpl::lddfa_real_io();
//ASI_REAL_IO_LITTLE //ASI_REAL_IO_LITTLE
0x1D: FailUnimpl::lddfa_real_io_l(); 0x1D: FailUnimpl::lddfa_real_io_l();
//ASI_LDTX_REAL
0x26: TwinLoad::ldtx_real(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_N
0x27: TwinLoad::ldtx_n(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_REAL_L
0x2E: TwinLoad::ldtx_real_l(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_LDTX_N_L
0x2F: TwinLoad::ldtx_n_l(
{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_PRIMARY //ASI_PRIMARY
0x80: FailUnimpl::lddfa_p(); 0x80: FailUnimpl::lddfa_p();
//ASI_PRIMARY_LITTLE //ASI_PRIMARY_LITTLE

3
src/arch/sparc/tlb.cc
View file

@ -575,6 +575,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (write && asi == ASI_LDTX_P) if (write && asi == ASI_LDTX_P)
// block init store (like write hint64) // block init store (like write hint64)
goto continueDtbFlow; goto continueDtbFlow;
if (!write && asi == ASI_QUAD_LDD)
goto continueDtbFlow;
if (AsiIsTwin(asi)) if (AsiIsTwin(asi))
panic("Twin ASIs not supported\n"); panic("Twin ASIs not supported\n");
if (AsiIsPartialStore(asi)) if (AsiIsPartialStore(asi))