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Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy.

Browse source 
src/cpu/o3/alpha/cpu.hh:
    Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
    Moved the tlbs to the base o3 cpu.

--HG--
extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
This commit is contained in:
Gabe Black 2006-12-06 11:36:40 -05:00
parent 0ed6c52c1e
commit 6826ee53db
5 changed files with 35 additions and 69 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
src/cpu/o3/alpha/cpu.hh
View file

@ -37,12 +37,6 @@
#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
namespace TheISA
{
class ITB;
class DTB;
}
class EndQuiesceEvent;
namespace Kernel {
class Statistics;
@ -61,14 +55,6 @@ class TranslatingPort;
template <class Impl>
class AlphaO3CPU : public FullO3CPU<Impl>
{
protected:
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::RegFile RegFile;
typedef TheISA::MiscRegFile MiscRegFile;
public:
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;
@ -77,13 +63,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
/** Constructs an AlphaO3CPU with the given parameters. */
AlphaO3CPU(Params *params);
#if FULL_SYSTEM
/** ITB pointer. */
AlphaISA::ITB *itb;
/** DTB pointer. */
AlphaISA::DTB *dtb;
#endif
/** Registers statistics. */
void regStats();
@ -91,19 +70,19 @@ class AlphaO3CPU : public FullO3CPU<Impl>
/** Translates instruction requestion. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return itb->translate(req, thread->getTC());
return this->itb->translate(req, thread->getTC());
}
/** Translates data read request. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return dtb->translate(req, thread->getTC(), false);
return this->dtb->translate(req, thread->getTC(), false);
}
/** Translates data write request. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return dtb->translate(req, thread->getTC(), true);
return this->dtb->translate(req, thread->getTC(), true);
}
#else
@ -127,20 +106,22 @@ class AlphaO3CPU : public FullO3CPU<Impl>
#endif
/** Reads a miscellaneous register. */
MiscReg readMiscReg(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
@ -175,10 +156,10 @@ class AlphaO3CPU : public FullO3CPU<Impl>
*/
void syscall(int64_t callnum, int tid);
/** Gets a syscall argument. */
IntReg getSyscallArg(int i, int tid);
TheISA::IntReg getSyscallArg(int i, int tid);
/** Used to shift args for indirect syscall. */
void setSyscallArg(int i, IntReg val, int tid);
void setSyscallArg(int i, TheISA::IntReg val, int tid);
/** Sets the return value of a syscall. */
void setSyscallReturn(SyscallReturn return_value, int tid);

29
src/cpu/o3/alpha/cpu_impl.hh
View file

@ -55,12 +55,7 @@
#endif
template <class Impl>
AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
#if FULL_SYSTEM
: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
#else
: FullO3CPU<Impl>(params)
#endif
AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(params)
{
DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
@ -173,15 +168,16 @@ AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
template <class Impl>
void
AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val,
unsigned tid)
{
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>
void
AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
unsigned tid)
AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
const TheISA::MiscReg &val, unsigned tid)
{
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
}
@ -315,7 +311,7 @@ AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
template <class Impl>
void
AlphaO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
{
this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
}
@ -324,17 +320,6 @@ template <class Impl>
void
AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
{
// check for error condition. Alpha syscall convention is to
// indicate success/failure in reg a3 (r19) and put the
// return value itself in the standard return value reg (v0).
if (return_value.successful()) {
// no error
this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
} else {
// got an error, return details
this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid);
this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
}
TheISA::setSyscallReturn(return_value, this->tcBase(tid));
}
#endif

6
src/cpu/o3/alpha/thread_context.hh
View file

@ -36,12 +36,6 @@ class AlphaTC : public O3ThreadContext<Impl>
{
public:
#if FULL_SYSTEM
/** Returns a pointer to the ITB. */
virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; }
/** Returns a pointer to the DTB. */
virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; }
/** Returns pointer to the quiesce event. */
virtual EndQuiesceEvent *getQuiesceEvent()
{

4
src/cpu/o3/cpu.cc
View file

@ -149,6 +149,10 @@ FullO3CPU<Impl>::DeallocateContextEvent::description()
template <class Impl>
FullO3CPU<Impl>::FullO3CPU(Params *params)
: BaseO3CPU(params),
#if FULL_SYSTEM
itb(params->itb),
dtb(params->dtb),
#endif
tickEvent(this),
removeInstsThisCycle(false),
fetch(params),

24
src/cpu/o3/cpu.hh
View file

@ -91,9 +91,6 @@ template <class Impl>
class FullO3CPU : public BaseO3CPU
{
public:
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
// Typedefs from the Impl here.
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
@ -114,6 +111,11 @@ class FullO3CPU : public BaseO3CPU
SwitchedOut
};
#if FULL_SYSTEM
TheISA::ITB * itb;
TheISA::DTB * dtb;
#endif
/** Overall CPU status. */
Status _status;
@ -382,23 +384,23 @@ class FullO3CPU : public BaseO3CPU
/** Register accessors. Index refers to the physical register index. */
uint64_t readIntReg(int reg_idx);
FloatReg readFloatReg(int reg_idx);
TheISA::FloatReg readFloatReg(int reg_idx);
FloatReg readFloatReg(int reg_idx, int width);
TheISA::FloatReg readFloatReg(int reg_idx, int width);
FloatRegBits readFloatRegBits(int reg_idx);
TheISA::FloatRegBits readFloatRegBits(int reg_idx);
FloatRegBits readFloatRegBits(int reg_idx, int width);
TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, FloatReg val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
void setFloatReg(int reg_idx, FloatReg val, int width);
void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
void setFloatRegBits(int reg_idx, FloatRegBits val);
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
uint64_t readArchIntReg(int reg_idx, unsigned tid);