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Updated refs for calculating IPC/CPI.

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--HG--
extra : convert_revision : ee8dfee5eaa345dcb08f5d06d054655b1f6f79da
This commit is contained in:
Kevin Lim 2007-04-22 15:29:59 -04:00
parent 8c7a6e1654
commit 67a37e83f3
3 changed files with 23 additions and 23 deletions
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14
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 415 # Nu
global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted
global.BPredUnit.lookups 2195 # Number of BP lookups
global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
host_inst_rate 5017 # Simulator instruction rate (inst/s)
host_inst_rate 22780 # Simulator instruction rate (inst/s)
host_mem_usage 154084 # Number of bytes of host memory used
host_seconds 1.12 # Real time elapsed on the host
host_tick_rate 3160160 # Simulator tick rate (ticks/s)
host_seconds 0.25 # Real time elapsed on the host
host_tick_rate 14337041 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 138 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit.
@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 17 # Th
system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 630.179619 # CPI: Cycles Per Instruction
system.cpu.cpi_total 630.179619 # CPI: Total CPI of All Threads
system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency
@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 418 #
system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.001587 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.001587 # IPC: Total IPC of All Threads
system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.02% # Type of FU issued

16
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 220 # Nu
global.BPredUnit.condPredicted 427 # Number of conditional branches predicted
global.BPredUnit.lookups 860 # Number of BP lookups
global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target.
host_inst_rate 32334 # Simulator instruction rate (inst/s)
host_mem_usage 153596 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 21839716 # Simulator tick rate (ticks/s)
host_inst_rate 31252 # Simulator instruction rate (inst/s)
host_mem_usage 153592 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_tick_rate 21107113 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit.
@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4 # Th
system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 678.257227 # CPI: Cycles Per Instruction
system.cpu.cpi_total 678.257227 # CPI: Total CPI of All Threads
system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency
@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 91 #
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.001474 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.001474 # IPC: Total IPC of All Threads
system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued

16
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1086 # Nu
global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted
global.BPredUnit.lookups 4062 # Number of BP lookups
global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target.
host_inst_rate 49499 # Simulator instruction rate (inst/s)
host_inst_rate 49679 # Simulator instruction rate (inst/s)
host_mem_usage 154724 # Number of bytes of host memory used
host_seconds 0.23 # Real time elapsed on the host
host_tick_rate 20219756 # Simulator tick rate (ticks/s)
host_tick_rate 20293608 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 59 # Number of conflicting stores.
@ -68,9 +68,9 @@ system.cpu.commit.commitSquashedInsts 7371 # Th
system.cpu.committedInsts_0 5623 # Number of Instructions Simulated
system.cpu.committedInsts_1 5624 # Number of Instructions Simulated
system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
system.cpu.cpi_0 818.157567 # CPI: Cycles Per Instruction
system.cpu.cpi_1 818.012091 # CPI: Cycles Per Instruction
system.cpu.cpi_total 409.042411 # CPI: Total CPI of All Threads
system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction
system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency
@ -472,9 +472,9 @@ system.cpu.iew.lsq.thread.1.squashedStores 246 #
system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly
system.cpu.ipc_0 0.001222 # IPC: Instructions Per Cycle
system.cpu.ipc_1 0.001222 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.002445 # IPC: Total IPC of All Threads
system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle
system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.02% # Type of FU issued