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This commit is contained in:
Gabe Black 2010-12-20 16:24:40 -05:00
parent 89850d6370
commit 672d6a4b98
22 changed files with 292 additions and 292 deletions
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2
src/arch/SConscript
View file

@ -45,7 +45,7 @@ Import('*')
isa_switch_hdrs = Split(''' isa_switch_hdrs = Split('''
faults.hh faults.hh
interrupts.hh interrupts.hh
isa.hh isa.hh
isa_traits.hh isa_traits.hh
kernel_stats.hh kernel_stats.hh
locked_mem.hh locked_mem.hh

10
src/arch/alpha/isa/decoder.isa
View file

@ -100,7 +100,7 @@ decode OPCODE default Unknown::unknown() {
format IntegerOperate { format IntegerOperate {
0x10: decode INTFUNC { // integer arithmetic operations 0x10: decode INTFUNC { // integer arithmetic operations
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
0x40: addlv({{ 0x40: addlv({{
@ -173,7 +173,7 @@ decode OPCODE default Unknown::unknown() {
}}); }});
} }
0x11: decode INTFUNC { // integer logical operations 0x11: decode INTFUNC { // integer logical operations
0x00: and({{ Rc = Ra & Rb_or_imm; }}); 0x00: and({{ Rc = Ra & Rb_or_imm; }});
0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
@ -291,7 +291,7 @@ decode OPCODE default Unknown::unknown() {
}}); }});
} }
0x13: decode INTFUNC { // integer multiplies 0x13: decode INTFUNC { // integer multiplies
0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{ 0x30: umulh({{
@ -301,7 +301,7 @@ decode OPCODE default Unknown::unknown() {
}}, IntMultOp); }}, IntMultOp);
0x40: mullv({{ 0x40: mullv({{
// 32-bit multiply with trap on overflow // 32-bit multiply with trap on overflow
int64_t Rax = Ra.sl; // sign extended version of Ra.sl int64_t Rax = Ra.sl; // sign extended version of Ra.sl
int64_t Rbx = Rb_or_imm.sl; int64_t Rbx = Rb_or_imm.sl;
int64_t tmp = Rax * Rbx; int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match // To avoid overflow, all the upper 32 bits must match
@ -587,7 +587,7 @@ decode OPCODE default Unknown::unknown() {
format BasicOperateWithNopCheck { format BasicOperateWithNopCheck {
0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
0x014: FailUnimpl::itoff(); // VAX-format conversion 0x014: FailUnimpl::itoff(); // VAX-format conversion
} }
} }
} }

30
src/arch/alpha/isa/fp.isa
View file

@ -32,9 +32,9 @@
// //
// Floating-point instructions // Floating-point instructions
// //
// Note that many FP-type instructions which do not support all the // Note that many FP-type instructions which do not support all the
// various rounding & trapping modes use the simpler format // various rounding & trapping modes use the simpler format
// BasicOperateWithNopCheck. // BasicOperateWithNopCheck.
// //
output exec {{ output exec {{
@ -45,7 +45,7 @@ output exec {{
#if FULL_SYSTEM #if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
Fault fault = NoFault; // dummy... this ipr access should not fault Fault fault = NoFault; // dummy... this ipr access should not fault
if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault; fault = new FloatEnableFault;
} }
@ -71,11 +71,11 @@ output header {{
public: public:
/// Alpha FP rounding modes. /// Alpha FP rounding modes.
enum RoundingMode { enum RoundingMode {
Chopped = 0, ///< round toward zero Chopped = 0, ///< round toward zero
Minus_Infinity = 1, ///< round toward minus infinity Minus_Infinity = 1, ///< round toward minus infinity
Normal = 2, ///< round to nearest (default) Normal = 2, ///< round to nearest (default)
Dynamic = 3, ///< use FPCR setting (in instruction) Dynamic = 3, ///< use FPCR setting (in instruction)
Plus_Infinity = 3 ///< round to plus inifinity (in FPCR) Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
}; };
/// Alpha FP trapping modes. /// Alpha FP trapping modes.
@ -84,10 +84,10 @@ output header {{
/// the assembly modifier is V rather than U. /// the assembly modifier is V rather than U.
enum TrappingMode { enum TrappingMode {
/// default: nothing enabled /// default: nothing enabled
Imprecise = 0, ///< no modifier Imprecise = 0, ///< no modifier
/// underflow/overflow traps enabled, inexact disabled /// underflow/overflow traps enabled, inexact disabled
Underflow_Imprecise = 1, ///< /U or /V Underflow_Imprecise = 1, ///< /U or /V
Underflow_Precise = 5, ///< /SU or /SV Underflow_Precise = 5, ///< /SU or /SV
/// underflow/overflow and inexact traps enabled /// underflow/overflow and inexact traps enabled
Underflow_Inexact_Precise = 7 ///< /SUI or /SVI Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
}; };
@ -192,10 +192,10 @@ output decoder {{
} }
const int AlphaFP::alphaToC99RoundingMode[] = { const int AlphaFP::alphaToC99RoundingMode[] = {
M5_FE_TOWARDZERO, // Chopped M5_FE_TOWARDZERO, // Chopped
M5_FE_DOWNWARD, // Minus_Infinity M5_FE_DOWNWARD, // Minus_Infinity
M5_FE_TONEAREST, // Normal M5_FE_TONEAREST, // Normal
M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
}; };
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" }; const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };

28
src/arch/alpha/isa/main.isa
View file

@ -102,30 +102,30 @@ namespace AlphaISA;
// Universal (format-independent) fields // Universal (format-independent) fields
def bitfield PALMODE <32:32>; def bitfield PALMODE <32:32>;
def bitfield OPCODE <31:26>; def bitfield OPCODE <31:26>;
def bitfield RA <25:21>; def bitfield RA <25:21>;
def bitfield RB <20:16>; def bitfield RB <20:16>;
// Memory format // Memory format
def signed bitfield MEMDISP <15: 0>; // displacement def signed bitfield MEMDISP <15: 0>; // displacement
def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
// Memory-format jumps // Memory-format jumps
def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
// Branch format // Branch format
def signed bitfield BRDISP <20: 0>; // displacement def signed bitfield BRDISP <20: 0>; // displacement
// Integer operate format(s>; // Integer operate format(s>;
def bitfield INTIMM <20:13>; // integer immediate (literal) def bitfield INTIMM <20:13>; // integer immediate (literal)
def bitfield IMM <12:12>; // immediate flag def bitfield IMM <12:12>; // immediate flag
def bitfield INTFUNC <11: 5>; // function code def bitfield INTFUNC <11: 5>; // function code
def bitfield RC < 4: 0>; // dest reg def bitfield RC < 4: 0>; // dest reg
// Floating-point operate format // Floating-point operate format
def bitfield FA <25:21>; def bitfield FA <25:21>;
def bitfield FB <20:16>; def bitfield FB <20:16>;
def bitfield FP_FULLFUNC <15: 5>; // complete function code def bitfield FP_FULLFUNC <15: 5>; // complete function code
def bitfield FP_TRAPMODE <15:13>; // trapping mode def bitfield FP_TRAPMODE <15:13>; // trapping mode
def bitfield FP_ROUNDMODE <12:11>; // rounding mode def bitfield FP_ROUNDMODE <12:11>; // rounding mode
@ -133,10 +133,10 @@ def bitfield FP_FULLFUNC <15: 5>; // complete function code
def bitfield FP_SRCTYPE <10: 9>; // source reg type def bitfield FP_SRCTYPE <10: 9>; // source reg type
def bitfield FP_SHORTFUNC < 8: 5>; // short function code def bitfield FP_SHORTFUNC < 8: 5>; // short function code
def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
def bitfield FC < 4: 0>; // dest reg def bitfield FC < 4: 0>; // dest reg
// PALcode format // PALcode format
def bitfield PALFUNC <25: 0>; // function code def bitfield PALFUNC <25: 0>; // function code
// EV5 PAL instructions: // EV5 PAL instructions:
// HW_LD/HW_ST // HW_LD/HW_ST
@ -154,7 +154,7 @@ def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
def bitfield HW_REI_MBZ <13: 0>; // must be zero def bitfield HW_REI_MBZ <13: 0>; // must be zero
// HW_MTPR/MW_MFPR // HW_MTPR/MW_MFPR
def bitfield HW_IPR_IDX <15:0>; // IPR index def bitfield HW_IPR_IDX <15:0>; // IPR index
// M5 instructions // M5 instructions
def bitfield M5FUNC <7:0>; def bitfield M5FUNC <7:0>;

8
src/arch/alpha/isa/pal.isa
View file

@ -84,10 +84,10 @@ output header {{
class CallPalBase : public AlphaStaticInst class CallPalBase : public AlphaStaticInst
{ {
protected: protected:
int palFunc; ///< Function code part of instruction int palFunc; ///< Function code part of instruction
int palOffset; ///< Target PC, offset from IPR_PAL_BASE int palOffset; ///< Target PC, offset from IPR_PAL_BASE
bool palValid; ///< is the function code valid? bool palValid; ///< is the function code valid?
bool palPriv; ///< is this call privileged? bool palPriv; ///< is this call privileged?
/// Constructor. /// Constructor.
CallPalBase(const char *mnem, ExtMachInst _machInst, CallPalBase(const char *mnem, ExtMachInst _machInst,

2
src/arch/arm/isa_traits.hh
View file

@ -99,7 +99,7 @@ namespace ArmISA
// return a no-op instruction... used for instruction fetch faults // return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000; const ExtMachInst NoopMachInst = 0x00000000;
const int LogVMPageSize = 12; // 4K bytes const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize); const int VMPageSize = (1 << LogVMPageSize);
// Shouldn't this be 1 because of Thumb?! Dynamic? --Ali // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali

50
src/arch/arm/linux/linux.cc
View file

@ -36,49 +36,49 @@
// open(2) flags translation table // open(2) flags translation table
OpenFlagTransTable ArmLinux::openFlagTable[] = { OpenFlagTransTable ArmLinux::openFlagTable[] = {
#ifdef _MSC_VER #ifdef _MSC_VER
{ ArmLinux::TGT_O_RDONLY, _O_RDONLY }, { ArmLinux::TGT_O_RDONLY, _O_RDONLY },
{ ArmLinux::TGT_O_WRONLY, _O_WRONLY }, { ArmLinux::TGT_O_WRONLY, _O_WRONLY },
{ ArmLinux::TGT_O_RDWR, _O_RDWR }, { ArmLinux::TGT_O_RDWR, _O_RDWR },
{ ArmLinux::TGT_O_APPEND, _O_APPEND }, { ArmLinux::TGT_O_APPEND, _O_APPEND },
{ ArmLinux::TGT_O_CREAT, _O_CREAT }, { ArmLinux::TGT_O_CREAT, _O_CREAT },
{ ArmLinux::TGT_O_TRUNC, _O_TRUNC }, { ArmLinux::TGT_O_TRUNC, _O_TRUNC },
{ ArmLinux::TGT_O_EXCL, _O_EXCL }, { ArmLinux::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK #ifdef _O_NONBLOCK
{ ArmLinux::TGT_O_NONBLOCK, _O_NONBLOCK }, { ArmLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif #endif
#ifdef _O_NOCTTY #ifdef _O_NOCTTY
{ ArmLinux::TGT_O_NOCTTY, _O_NOCTTY }, { ArmLinux::TGT_O_NOCTTY, _O_NOCTTY },
#endif #endif
#ifdef _O_SYNC #ifdef _O_SYNC
{ ArmLinux::TGT_O_SYNC, _O_SYNC }, { ArmLinux::TGT_O_SYNC, _O_SYNC },
#endif #endif
#else /* !_MSC_VER */ #else /* !_MSC_VER */
{ ArmLinux::TGT_O_RDONLY, O_RDONLY }, { ArmLinux::TGT_O_RDONLY, O_RDONLY },
{ ArmLinux::TGT_O_WRONLY, O_WRONLY }, { ArmLinux::TGT_O_WRONLY, O_WRONLY },
{ ArmLinux::TGT_O_RDWR, O_RDWR }, { ArmLinux::TGT_O_RDWR, O_RDWR },
{ ArmLinux::TGT_O_CREAT, O_CREAT }, { ArmLinux::TGT_O_CREAT, O_CREAT },
{ ArmLinux::TGT_O_EXCL, O_EXCL }, { ArmLinux::TGT_O_EXCL, O_EXCL },
{ ArmLinux::TGT_O_NOCTTY, O_NOCTTY }, { ArmLinux::TGT_O_NOCTTY, O_NOCTTY },
{ ArmLinux::TGT_O_TRUNC, O_TRUNC }, { ArmLinux::TGT_O_TRUNC, O_TRUNC },
{ ArmLinux::TGT_O_APPEND, O_APPEND }, { ArmLinux::TGT_O_APPEND, O_APPEND },
{ ArmLinux::TGT_O_NONBLOCK, O_NONBLOCK }, { ArmLinux::TGT_O_NONBLOCK, O_NONBLOCK },
#ifdef O_SYNC #ifdef O_SYNC
{ ArmLinux::TGT_O_SYNC, O_SYNC }, { ArmLinux::TGT_O_SYNC, O_SYNC },
#endif #endif
#ifdef FASYNC #ifdef FASYNC
{ ArmLinux::TGT_FASYNC, FASYNC }, { ArmLinux::TGT_FASYNC, FASYNC },
#endif #endif
#ifdef O_DIRECT #ifdef O_DIRECT
{ ArmLinux::TGT_O_DIRECT, O_DIRECT }, { ArmLinux::TGT_O_DIRECT, O_DIRECT },
#endif #endif
#ifdef O_LARGEFILE #ifdef O_LARGEFILE
{ ArmLinux::TGT_O_LARGEFILE, O_LARGEFILE }, { ArmLinux::TGT_O_LARGEFILE, O_LARGEFILE },
#endif #endif
#ifdef O_DIRECTORY #ifdef O_DIRECTORY
{ ArmLinux::TGT_O_DIRECTORY, O_DIRECTORY }, { ArmLinux::TGT_O_DIRECTORY, O_DIRECTORY },
#endif #endif
#ifdef O_NOFOLLOW #ifdef O_NOFOLLOW
{ ArmLinux::TGT_O_NOFOLLOW, O_NOFOLLOW }, { ArmLinux::TGT_O_NOFOLLOW, O_NOFOLLOW },
#endif #endif
#endif /* _MSC_VER */ #endif /* _MSC_VER */
}; };

6
src/arch/arm/tlb.hh
View file

@ -84,10 +84,10 @@ class TLB : public BaseTLB
}; };
protected: protected:
TlbEntry *table; // the Page Table TlbEntry *table; // the Page Table
int size; // TLB Size int size; // TLB Size
uint32_t _attr; // Memory attributes for last accessed TLB entry uint32_t _attr; // Memory attributes for last accessed TLB entry
#if FULL_SYSTEM #if FULL_SYSTEM
TableWalker *tableWalker; TableWalker *tableWalker;

6
src/arch/mips/SConscript
View file

@ -44,15 +44,15 @@ if env['TARGET_ISA'] == 'mips':
TraceFlag('MipsPRA') TraceFlag('MipsPRA')
if env['FULL_SYSTEM']: if env['FULL_SYSTEM']:
SimObject('MipsSystem.py') SimObject('MipsSystem.py')
SimObject('MipsInterrupts.py') SimObject('MipsInterrupts.py')
Source('idle_event.cc') Source('idle_event.cc')
Source('mips_core_specific.cc') Source('mips_core_specific.cc')
Source('vtophys.cc') Source('vtophys.cc')
Source('system.cc') Source('system.cc')
Source('stacktrace.cc') Source('stacktrace.cc')
Source('linux/system.cc') Source('linux/system.cc')
Source('interrupts.cc') Source('interrupts.cc')
Source('bare_iron/system.cc') Source('bare_iron/system.cc')
else: else:
Source('process.cc') Source('process.cc')

22
src/arch/mips/isa/bitfields.isa
View file

@ -46,27 +46,27 @@ def bitfield FUNCTION < 5: 0>;
def bitfield FUNCTION_HI < 5: 3>; def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>; def bitfield FUNCTION_LO < 2: 0>;
def bitfield RS <25:21>; def bitfield RS <25:21>;
def bitfield RS_MSB <25:25>; def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>; def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>; def bitfield RS_LO <23:21>;
def bitfield RS_SRL <25:22>; def bitfield RS_SRL <25:22>;
def bitfield RS_RT <25:16>; def bitfield RS_RT <25:16>;
def bitfield RT <20:16>; def bitfield RT <20:16>;
def bitfield RT_HI <20:19>; def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>; def bitfield RT_LO <18:16>;
def bitfield RT_RD <20:11>; def bitfield RT_RD <20:11>;
def bitfield RD <15:11>; def bitfield RD <15:11>;
def bitfield INTIMM <15: 0>; def bitfield INTIMM <15: 0>;
def bitfield RS_RT_INTIMM <25: 0>; def bitfield RS_RT_INTIMM <25: 0>;
// Floating-point operate format // Floating-point operate format
def bitfield FMT <25:21>; def bitfield FMT <25:21>;
def bitfield FR <25:21>; def bitfield FR <25:21>;
def bitfield FT <20:16>; def bitfield FT <20:16>;
def bitfield FS <15:11>; def bitfield FS <15:11>;
def bitfield FD <10:6>; def bitfield FD <10:6>;
def bitfield ND <17:17>; def bitfield ND <17:17>;
def bitfield TF <16:16>; def bitfield TF <16:16>;
@ -90,15 +90,15 @@ def bitfield SC < 5: 5>;
def bitfield OFFSET <15: 0>; // displacement def bitfield OFFSET <15: 0>; // displacement
// Jmp format // Jmp format
def bitfield JMPTARG <25: 0>; def bitfield JMPTARG <25: 0>;
def bitfield HINT <10: 6>; def bitfield HINT <10: 6>;
def bitfield SYSCALLCODE <25: 6>; def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>; def bitfield TRAPCODE <15:13>;
// EXT/INS instructions // EXT/INS instructions
def bitfield MSB <15:11>; def bitfield MSB <15:11>;
def bitfield LSB <10: 6>; def bitfield LSB <10: 6>;
// M5 instructions // M5 instructions
def bitfield M5FUNC <7:0>; def bitfield M5FUNC <7:0>;

4
src/arch/mips/isa/decoder.isa
View file

@ -1131,7 +1131,7 @@ decode OPCODE_HI default Unknown::unknown() {
UnorderedFalse); UnorderedFalse);
0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
UnorderedTrue); UnorderedTrue);
0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }},
UnorderedFalse); UnorderedFalse);
0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
UnorderedTrue); UnorderedTrue);
@ -1252,7 +1252,7 @@ decode OPCODE_HI default Unknown::unknown() {
UnorderedFalse); UnorderedFalse);
0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
UnorderedTrue); UnorderedTrue);
0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }},
UnorderedFalse); UnorderedFalse);
0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
UnorderedTrue); UnorderedTrue);

2
src/arch/sparc/isa/base.isa
View file

@ -567,7 +567,7 @@ output exec {{
inline Fault inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc) checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
Fault fault = NoFault; // dummy... this ipr access should not fault Fault fault = NoFault; // dummy... this ipr access should not fault
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) { xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault; return NoFault;

72
src/arch/sparc/isa/bitfields.isa
View file

@ -36,48 +36,48 @@
// Bitfields are shared liberally between instruction formats, so they are // Bitfields are shared liberally between instruction formats, so they are
// simply defined alphabetically // simply defined alphabetically
def bitfield A <29>; def bitfield A <29>;
def bitfield BPCC <21:20>; // for BPcc & FBPcc def bitfield BPCC <21:20>; // for BPcc & FBPcc
def bitfield FCMPCC <26:25>; // for FCMP & FCMPEa def bitfield FCMPCC <26:25>; // for FCMP & FCMPEa
def bitfield FMOVCC <13:11>; // for FMOVcc def bitfield FMOVCC <13:11>; // for FMOVcc
def bitfield CC <12:11>; // for MOVcc & Tcc def bitfield CC <12:11>; // for MOVcc & Tcc
def bitfield MOVCC3 <18>; // also for MOVcc def bitfield MOVCC3 <18>; // also for MOVcc
def bitfield CMASK <6:4>; def bitfield CMASK <6:4>;
def bitfield COND2 <28:25>; def bitfield COND2 <28:25>;
def bitfield COND4 <17:14>; def bitfield COND4 <17:14>;
def bitfield D16HI <21:20>; def bitfield D16HI <21:20>;
def bitfield D16LO <13:0>; def bitfield D16LO <13:0>;
def bitfield DISP19 <18:0>; def bitfield DISP19 <18:0>;
def bitfield DISP22 <21:0>; def bitfield DISP22 <21:0>;
def bitfield DISP30 <29:0>; def bitfield DISP30 <29:0>;
def bitfield FCN <29:25>; def bitfield FCN <29:25>;
def bitfield I <13>; def bitfield I <13>;
def bitfield IMM_ASI <12:5>; def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>; def bitfield IMM22 <21:0>;
def bitfield M5FUNC <15:7>; def bitfield M5FUNC <15:7>;
def bitfield MMASK <3:0>; def bitfield MMASK <3:0>;
def bitfield OP <31:30>; def bitfield OP <31:30>;
def bitfield OP2 <24:22>; def bitfield OP2 <24:22>;
def bitfield OP3 <24:19>; def bitfield OP3 <24:19>;
def bitfield OPF <13:5>; def bitfield OPF <13:5>;
def bitfield OPF_CC <13:11>; def bitfield OPF_CC <13:11>;
def bitfield OPF_LOW5 <9:5>; def bitfield OPF_LOW5 <9:5>;
def bitfield OPF_LOW6 <10:5>; def bitfield OPF_LOW6 <10:5>;
def bitfield P <19>; def bitfield P <19>;
def bitfield RCOND2 <27:25>; def bitfield RCOND2 <27:25>;
def bitfield RCOND3 <12:10>; def bitfield RCOND3 <12:10>;
def bitfield RCOND4 <12:10>; def bitfield RCOND4 <12:10>;
def bitfield RD <29:25>; def bitfield RD <29:25>;
def bitfield RS1 <18:14>; def bitfield RS1 <18:14>;
def bitfield RS2 <4:0>; def bitfield RS2 <4:0>;
def bitfield SHCNT32 <4:0>; def bitfield SHCNT32 <4:0>;
def bitfield SHCNT64 <5:0>; def bitfield SHCNT64 <5:0>;
def bitfield SIMM10 <9:0>; def bitfield SIMM10 <9:0>;
def bitfield SIMM11 <10:0>; def bitfield SIMM11 <10:0>;
def bitfield SIMM13 <12:0>; def bitfield SIMM13 <12:0>;
def bitfield SW_TRAP <7:0>; def bitfield SW_TRAP <7:0>;
def bitfield X <12>; def bitfield X <12>;
// Extended bitfields which aren't part of the actual instruction. // Extended bitfields which aren't part of the actual instruction.
def bitfield EXT_ASI <39:32>; def bitfield EXT_ASI <39:32>;

2
src/arch/sparc/isa/formats/integerop.isa
View file

@ -259,7 +259,7 @@ let {{
def doIntFormat(code, ccCode, name, Name, opt_flags): def doIntFormat(code, ccCode, name, Name, opt_flags):
(usesImm, code, immCode, (usesImm, code, immCode,
rString, iString) = splitOutImm(code) rString, iString) = splitOutImm(code)
iop = InstObjParams(name, Name, 'IntOp', iop = InstObjParams(name, Name, 'IntOp',
{"code": code, "cc_code": ccCode}, {"code": code, "cc_code": ccCode},
opt_flags) opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)

186
src/arch/sparc/isa/operands.isa
View file

@ -72,71 +72,71 @@ def operands {{
# For clarity, descriptions that depend on unsigned behavior should # For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'. # explicitly specify '.uq'.
'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
# The Rd from the previous window # The Rd from the previous window
'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
# The Rd from the next window # The Rd from the next window
'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
# For microcoded twin load instructions, RdTwin appears in the "code" # For microcoded twin load instructions, RdTwin appears in the "code"
# for the instruction is replaced by RdLow or RdHigh by the format # for the instruction is replaced by RdLow or RdHigh by the format
# before it's processed by the iop. # before it's processed by the iop.
# The low (even) register of a two register pair # The low (even) register of a two register pair
'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
# The high (odd) register of a two register pair # The high (odd) register of a two register pair
'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
# A microcode register. Right now, this is the only one. # A microcode register. Right now, this is the only one.
'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
# Because double and quad precision register numbers are decoded # Because double and quad precision register numbers are decoded
# differently, they get different operands. The single precision versions # differently, they get different operands. The single precision versions
# have an s post pended to their name. # have an s post pended to their name.
'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
#'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
# Each Frd_N refers to the Nth double precision register from Frd. # Each Frd_N refers to the Nth double precision register from Frd.
# Note that this adds twice N to the register number. # Note that this adds twice N to the register number.
#'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
#'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
#'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
#'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
#'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
#'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
#'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
#'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
#'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
#'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),
'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),
'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),
# Registers which are used explicitly in instructions # Registers which are used explicitly in instructions
'R0': ('IntReg', 'udw', '0', None, 6), 'R0': ('IntReg', 'udw', '0', None, 6),
'R1': ('IntReg', 'udw', '1', None, 7), 'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9), 'R16': ('IntReg', 'udw', '16', None, 9),
'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
@ -145,55 +145,55 @@ def operands {{
'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),
# Control registers # Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), # 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), # 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), # 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), # 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), # 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), # 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), # 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), # 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
# Mem gets a large number so it's always last # Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}}; }};

4
src/arch/x86/bios/SConscript
View file

@ -48,12 +48,12 @@ if env['TARGET_ISA'] == 'x86':
# The DMI tables. # The DMI tables.
SimObject('SMBios.py') SimObject('SMBios.py')
Source('smbios.cc') Source('smbios.cc')
# Intel Multiprocessor Specification Configuration Table # Intel Multiprocessor Specification Configuration Table
SimObject('IntelMP.py') SimObject('IntelMP.py')
Source('intelmp.cc') Source('intelmp.cc')
# ACPI system description tables # ACPI system description tables
SimObject('ACPI.py') SimObject('ACPI.py')
Source('acpi.cc') Source('acpi.cc')

106
src/cpu/inorder/SConscript
View file

@ -31,60 +31,60 @@
Import('*') Import('*')
if 'InOrderCPU' in env['CPU_MODELS']: if 'InOrderCPU' in env['CPU_MODELS']:
SimObject('InOrderCPU.py') SimObject('InOrderCPU.py')
SimObject('InOrderTrace.py') SimObject('InOrderTrace.py')
TraceFlag('ResReqCount') TraceFlag('ResReqCount')
TraceFlag('InOrderStage') TraceFlag('InOrderStage')
TraceFlag('InOrderStall') TraceFlag('InOrderStall')
TraceFlag('InOrderCPU') TraceFlag('InOrderCPU')
TraceFlag('RegDepMap') TraceFlag('RegDepMap')
TraceFlag('InOrderDynInst') TraceFlag('InOrderDynInst')
TraceFlag('Resource') TraceFlag('Resource')
TraceFlag('InOrderAGEN') TraceFlag('InOrderAGEN')
TraceFlag('InOrderFetchSeq') TraceFlag('InOrderFetchSeq')
TraceFlag('InOrderTLB') TraceFlag('InOrderTLB')
TraceFlag('InOrderCachePort') TraceFlag('InOrderCachePort')
TraceFlag('InOrderBPred') TraceFlag('InOrderBPred')
TraceFlag('InOrderDecode') TraceFlag('InOrderDecode')
TraceFlag('InOrderExecute') TraceFlag('InOrderExecute')
TraceFlag('InOrderInstBuffer') TraceFlag('InOrderInstBuffer')
TraceFlag('InOrderUseDef') TraceFlag('InOrderUseDef')
TraceFlag('InOrderMDU') TraceFlag('InOrderMDU')
TraceFlag('InOrderGraduation') TraceFlag('InOrderGraduation')
TraceFlag('ThreadModel') TraceFlag('ThreadModel')
TraceFlag('RefCount') TraceFlag('RefCount')
TraceFlag('AddrDep') TraceFlag('AddrDep')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
'ThreadModel', 'AddrDep'])
Source('pipeline_traits.cc') CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
Source('inorder_dyn_inst.cc') 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
Source('inorder_cpu_builder.cc') 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
Source('inorder_trace.cc') 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
Source('pipeline_stage.cc') 'ThreadModel', 'AddrDep'])
Source('first_stage.cc')
Source('resource.cc') Source('pipeline_traits.cc')
Source('resources/agen_unit.cc') Source('inorder_dyn_inst.cc')
Source('resources/execution_unit.cc') Source('inorder_cpu_builder.cc')
Source('resources/bpred_unit.cc') Source('inorder_trace.cc')
Source('resources/branch_predictor.cc') Source('pipeline_stage.cc')
Source('resources/cache_unit.cc') Source('first_stage.cc')
Source('resources/use_def.cc') Source('resource.cc')
Source('resources/decode_unit.cc') Source('resources/agen_unit.cc')
Source('resources/inst_buffer.cc') Source('resources/execution_unit.cc')
Source('resources/graduation_unit.cc') Source('resources/bpred_unit.cc')
Source('resources/fetch_seq_unit.cc') Source('resources/branch_predictor.cc')
Source('resources/mult_div_unit.cc') Source('resources/cache_unit.cc')
Source('resource_pool.cc') Source('resources/use_def.cc')
Source('resource_sked.cc') Source('resources/decode_unit.cc')
Source('reg_dep_map.cc') Source('resources/inst_buffer.cc')
Source('thread_state.cc') Source('resources/graduation_unit.cc')
Source('thread_context.cc') Source('resources/fetch_seq_unit.cc')
Source('cpu.cc') Source('resources/mult_div_unit.cc')
Source('resource_pool.cc')
Source('resource_sked.cc')
Source('reg_dep_map.cc')
Source('thread_state.cc')
Source('thread_context.cc')
Source('cpu.cc')

2
src/cpu/inorder/first_stage.hh
View file

@ -64,7 +64,7 @@ class FirstStage : public PipelineStage {
void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid); void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid);
/** There are no insts. coming from previous stages, so there is /** There are no insts. coming from previous stages, so there is
* no need to sort insts here * no need to sort insts here
*/ */
void sortInsts() {} void sortInsts() {}

30
src/cpu/inorder/inorder_dyn_inst.hh
View file

@ -101,8 +101,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
typedef std::list<DynInstPtr>::iterator ListIt; typedef std::list<DynInstPtr>::iterator ListIt;
enum { enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
}; };
public: public:
@ -373,24 +373,24 @@ class InOrderDynInst : public FastAlloc, public RefCounted
// INSTRUCTION TYPES - Forward checks to StaticInst object. // INSTRUCTION TYPES - Forward checks to StaticInst object.
// //
//////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////
bool isNop() const { return staticInst->isNop(); } bool isNop() const { return staticInst->isNop(); }
bool isMemRef() const { return staticInst->isMemRef(); } bool isMemRef() const { return staticInst->isMemRef(); }
bool isLoad() const { return staticInst->isLoad(); } bool isLoad() const { return staticInst->isLoad(); }
bool isStore() const { return staticInst->isStore(); } bool isStore() const { return staticInst->isStore(); }
bool isStoreConditional() const bool isStoreConditional() const
{ return staticInst->isStoreConditional(); } { return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
bool isCopy() const { return staticInst->isCopy(); } bool isCopy() const { return staticInst->isCopy(); }
bool isInteger() const { return staticInst->isInteger(); } bool isInteger() const { return staticInst->isInteger(); }
bool isFloating() const { return staticInst->isFloating(); } bool isFloating() const { return staticInst->isFloating(); }
bool isControl() const { return staticInst->isControl(); } bool isControl() const { return staticInst->isControl(); }
bool isCall() const { return staticInst->isCall(); } bool isCall() const { return staticInst->isCall(); }
bool isReturn() const { return staticInst->isReturn(); } bool isReturn() const { return staticInst->isReturn(); }
bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
bool isCondCtrl() const { return staticInst->isCondCtrl(); } bool isCondCtrl() const { return staticInst->isCondCtrl(); }
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
bool isThreadSync() const { return staticInst->isThreadSync(); } bool isThreadSync() const { return staticInst->isThreadSync(); }
@ -674,7 +674,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
// //
////////////////////////////////////////////////// //////////////////////////////////////////////////
/** Returns the number of source registers. */ /** Returns the number of source registers. */
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
/** Returns the number of destination registers. */ /** Returns the number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); } int8_t numDestRegs() const { return staticInst->numDestRegs(); }

2
src/cpu/inorder/resource.hh
View file

@ -253,7 +253,7 @@ class ResourceEvent : public Event
/// (for InOrderCPU model). /// (for InOrderCPU model).
/// check src/sim/eventq.hh for more event priorities. /// check src/sim/eventq.hh for more event priorities.
enum InOrderPriority { enum InOrderPriority {
Resource_Event_Pri = 45, Resource_Event_Pri = 45,
}; };
/** The Resource Slot that this event is servicing */ /** The Resource Slot that this event is servicing */

2
src/cpu/inorder/resources/cache_unit.hh
View file

@ -258,7 +258,7 @@ class CacheRequest : public ResourceRequest
} }
virtual PacketDataPtr getData() virtual PacketDataPtr getData()
{ return reqData; } { return reqData; }
void void
setMemAccCompleted(bool completed = true) setMemAccCompleted(bool completed = true)

8
src/dev/x86/cmos.cc
View file

@ -87,11 +87,11 @@ X86ISA::Cmos::readRegister(uint8_t reg)
if (reg <= 0xD) { if (reg <= 0xD) {
val = rtc.readData(reg); val = rtc.readData(reg);
DPRINTF(CMOS, DPRINTF(CMOS,
"Reading CMOS RTC reg %x as %x.\n", reg, val); "Reading CMOS RTC reg %x as %x.\n", reg, val);
} else { } else {
val = regs[reg]; val = regs[reg];
DPRINTF(CMOS, DPRINTF(CMOS,
"Reading non-volitile CMOS address %x as %x.\n", reg, val); "Reading non-volitile CMOS address %x as %x.\n", reg, val);
} }
return val; return val;
} }
@ -102,11 +102,11 @@ X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
assert(reg < numRegs); assert(reg < numRegs);
if (reg <= 0xD) { if (reg <= 0xD) {
DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n", DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n",
reg, val); reg, val);
rtc.writeData(reg, val); rtc.writeData(reg, val);
} else { } else {
DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n", DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n",
reg, val); reg, val);
regs[reg] = val; regs[reg] = val;
} }
} }