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Merge zizzer:/bk/newmem

Browse source 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 43dc3a23758e7956572d59464ebddcc56e82728b
This commit is contained in:
Ali Saidi 2007-06-01 14:55:17 -04:00
commit 66ee27078e
2 changed files with 8 additions and 4 deletions
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4
src/cpu/o3/fetch_impl.hh
View file

@ -1151,10 +1151,14 @@ DefaultFetch<Impl>::fetch(bool &status_change)
DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
tid, instruction->staticInst->disassemble(fetch_PC));
#if TRACING_ON
instruction->traceData =
Trace::getInstRecord(curTick, cpu->tcBase(tid),
instruction->staticInst,
instruction->readPC());
#elif
instruction->traceData = NULL;
#endif
///FIXME This needs to be more robust in dealing with delay slots
#if !ISA_HAS_DELAY_SLOT

8
src/cpu/simple/base.cc
View file

@ -329,7 +329,7 @@ BaseSimpleCPU::checkForInterrupts()
Fault
BaseSimpleCPU::setupFetchRequest(Request *req)
{
uint64_t threadPC = thread->readPC();
Addr threadPC = thread->readPC();
// set up memory request for instruction fetch
#if ISA_HAS_DELAY_SLOT
@ -340,8 +340,8 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
thread->readNextPC());
#endif
const Addr PCMask = ~(sizeof(MachInst) - 1);
Addr fetchPC = thread->readPC() + fetchOffset;
const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
Addr fetchPC = threadPC + fetchOffset;
req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
Fault fault = thread->translateInstReq(req);
@ -380,7 +380,7 @@ BaseSimpleCPU::preExecute()
//This should go away once the constructor can be set up properly
predecoder.setTC(thread->getTC());
//If more fetch data is needed, pass it in.
const Addr PCMask = ~(sizeof(MachInst) - 1);
const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
if(predecoder.needMoreBytes())
predecoder.moreBytes((thread->readPC() & PCMask) + fetchOffset,
0, inst);