mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
Makes x86-style locked operations even more distinct from LLSC operations. Using "locked" by itself should be obviously ambiguous now.
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@ -409,7 +409,7 @@ let {{
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'(StoreCheck << FlagShift)')
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'(StoreCheck << FlagShift)')
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defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
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defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
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'Data = Mem & mask(dataSize * 8);',
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'Data = Mem & mask(dataSize * 8);',
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'(StoreCheck << FlagShift) | Request::LOCKED')
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'(StoreCheck << FlagShift) | Request::LOCKED_RMW')
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defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
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defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
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@ -461,7 +461,7 @@ let {{
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defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
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defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
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defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
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defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
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mem_flags="Request::LOCKED")
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mem_flags="Request::LOCKED_RMW")
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defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
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defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
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@ -373,7 +373,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
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//If we don't need to access a second cache line, stop now.
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//If we don't need to access a second cache line, stop now.
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if (secondAddr <= addr)
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if (secondAddr <= addr)
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{
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{
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if (req->isLocked() && fault == NoFault) {
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if (req->isLockedRMW() && fault == NoFault) {
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assert(!locked);
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assert(!locked);
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locked = true;
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locked = true;
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}
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}
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@ -480,7 +480,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
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//stop now.
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//stop now.
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if (fault != NoFault || secondAddr <= addr)
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if (fault != NoFault || secondAddr <= addr)
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{
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{
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if (req->isLocked() && fault == NoFault) {
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if (req->isLockedRMW() && fault == NoFault) {
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assert(locked);
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assert(locked);
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locked = false;
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locked = false;
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}
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}
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@ -127,7 +127,7 @@ class Request
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* made up of a locked load, some operation on the data, and then a locked
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* made up of a locked load, some operation on the data, and then a locked
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* store.
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* store.
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*/
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*/
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static const FlagsType LOCKED = 0x00100000;
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static const FlagsType LOCKED_RMW = 0x00100000;
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/** The request is a Load locked/store conditional. */
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/** The request is a Load locked/store conditional. */
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static const FlagsType LLSC = 0x00200000;
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static const FlagsType LLSC = 0x00200000;
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/** This request is for a memory swap. */
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/** This request is for a memory swap. */
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@ -626,7 +626,7 @@ class Request
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bool isPrefetch() const { return _flags.isSet(PREFETCH); }
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bool isPrefetch() const { return _flags.isSet(PREFETCH); }
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bool isLLSC() const { return _flags.isSet(LLSC); }
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bool isLLSC() const { return _flags.isSet(LLSC); }
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bool isPriv() const { return _flags.isSet(PRIVILEGED); }
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bool isPriv() const { return _flags.isSet(PRIVILEGED); }
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bool isLocked() const { return _flags.isSet(LOCKED); }
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bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
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bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
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bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
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bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
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bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
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bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
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bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
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@ -604,7 +604,7 @@ Sequencer::makeRequest(PacketPtr pkt)
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primary_type = RubyRequestType_Load_Linked;
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primary_type = RubyRequestType_Load_Linked;
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}
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}
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secondary_type = RubyRequestType_ATOMIC;
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secondary_type = RubyRequestType_ATOMIC;
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} else if (pkt->req->isLocked()) {
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} else if (pkt->req->isLockedRMW()) {
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//
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//
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// x86 locked instructions are translated to store cache coherence
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// x86 locked instructions are translated to store cache coherence
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// requests because these requests should always be treated as read
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// requests because these requests should always be treated as read
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