sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Take into account the regular registers and the microcode registers when decided whether or not to fold.

Browse source 
--HG--
extra : convert_revision : 26feec984dec61799c4afb03a4503a53c35872c5
This commit is contained in:
Gabe Black 2007-07-30 15:38:40 -07:00
parent 9536120845
commit 65db30992c
1 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/arch/x86/isa/operands.isa
View file

@ -96,12 +96,12 @@ def operand_types {{
}};
def operands {{
'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0xC) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0xC) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
'Base': ('IntReg', 'uqw', '(((base & 0xC) == 4 ? foldABit : 0) | base)', 'IsInteger', 3),
'Index': ('IntReg', 'uqw', '(((index & 0xC) == 4 ? foldABit : 0) | index)', 'IsInteger', 4),
'DestReg': ('IntReg', 'uqw', '(((dest & 0xC) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
'Data': ('IntReg', 'uqw', '(((data & 0xC) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0x1C) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0x1C) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
'Index': ('IntReg', 'uqw', '(((index & 0x1C) == 4 ? foldABit : 0) | index)', 'IsInteger', 3),
'Base': ('IntReg', 'uqw', '(((base & 0x1C) == 4 ? foldABit : 0) | base)', 'IsInteger', 4),
'DestReg': ('IntReg', 'uqw', '(((dest & 0x1C) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),