Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu
SConscript: Separate Alpha EIO from syscall building for other architectures arch/isa_specific.hh: change MIPS constant to 34k arch/mips/isa/decoder.isa: Allow sll,ssnop,nop, and ehb to be determined through decoder using the different types of default cases arch/mips/isa/formats/branch.isa: Delete debug code arch/mips/isa/formats/noop.isa: add a Nop format arch/mips/isa_traits.hh: use constants instead of enums arch/mips/process.cc: point to the correct header file cpu/simple/cpu.cc: Output the actual fault name sim/process.cc: Inititalize NNPC --HG-- extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
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9 changed files with 76 additions and 60 deletions
13
SConscript
13
SConscript
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@ -248,16 +248,21 @@ turbolaser_sources = Split('''
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# Syscall emulation (non-full-system) sources
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syscall_emulation_sources = Split('''
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encumbered/eio/exolex.cc
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encumbered/eio/libexo.cc
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encumbered/eio/eio.cc
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kern/linux/linux.cc
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kern/tru64/tru64.cc
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sim/process.cc
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sim/syscall_emul.cc
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''')
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alpha_eio_sources = Split('''
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encumbered/eio/exolex.cc
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encumbered/eio/libexo.cc
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encumbered/eio/eio.cc
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''')
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if env['TARGET_ISA'] == 'ALPHA_ISA':
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syscall_emulation_sources += alpha_eio_sources
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memtest_sources = Split('''
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cpu/memtest/memtest.cc
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''')
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@ -45,7 +45,7 @@
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//would treat them as 0 in comparisons.
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#define ALPHA_ISA 21064
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#define SPARC_ISA 42
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#define MIPS_ISA 1337
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#define MIPS_ISA 34000
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//These tell the preprocessor where to find the files of a particular
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//ISA, and set the "TheISA" macro for use elsewhere.
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@ -30,11 +30,17 @@ decode OPCODE_HI default Unknown::unknown() {
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//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
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//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
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0x0: decode RS {
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0x0: sll({{ Rd = Rt.uw << SA; }});
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//0x0:nop({{ ; }}); //really sll r0,r0,0
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// 0x1:ssnop({{ ; }});//really sll r0,r0,1
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// 0x3:ehb({{ ; }}); //really sll r0,r0,3
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0x0: decode RS {
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0x0: decode RT {
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0x0: decode RD default Nop::nop() {
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0x0: decode SA {
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0x1: ssnop({{ ; }}); //really sll r0,r0,1
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0x3: ehb({{ ; }}); //really sll r0,r0,3
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}
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}
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}
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default: sll({{ Rd = Rt.uw << SA; }});
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}
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0x2: decode SRL {
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@ -265,8 +265,6 @@ def format Branch(code,*flags) {{
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code += ' NNPC = NNPC;\n'
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code += '} \n'
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code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;'
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iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
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('IsDirectControl', 'IsCondControl'))
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@ -305,8 +303,6 @@ def format Jump(code,*flags) {{
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if strlen > 1 and name[1:] == 'al':
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code = 'r31 = NNPC;\n' + code
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#code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}'
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#code += 'target = NNPC;'
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iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
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('IsIndirectControl', 'IsUncondControl'))
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@ -88,3 +88,7 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
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exec_output = BasicExecute.subst(iop)
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}};
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def format Nop() {{
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decode_block = 'return new Nop(\"sll r0,r0,0\",machInst);\n'
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}};
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@ -96,46 +96,56 @@ namespace MipsISA
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typedef uint64_t ExtMachInst;
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typedef uint8_t RegIndex;
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// typedef uint64_t Addr;
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enum {
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MemoryEnd = 0xffffffffffffffffULL,
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NumIntRegs = 32,
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NumFloatRegs = 32,
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NumMiscRegs = 258, //account for hi,lo regs
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// Constants Related to the number of registers
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MaxRegsOfAnyType = 32,
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// Static instruction parameters
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MaxInstSrcRegs = 3,
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MaxInstDestRegs = 2,
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const int NumIntArchRegs = 32;
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const int NumPALShadowRegs = 8;
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const int NumFloatArchRegs = 32;
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// @todo: Figure out what this number really should be.
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const int NumMiscArchRegs = 32;
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// semantically meaningful register indices
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ZeroReg = 0, // architecturally meaningful
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// the rest of these depend on the ABI
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StackPointerReg = 30,
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GlobalPointerReg = 29,
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ProcedureValueReg = 27,
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ReturnAddressReg = 26,
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ReturnValueReg = 0,
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FramePointerReg = 15,
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ArgumentReg0 = 16,
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ArgumentReg1 = 17,
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ArgumentReg2 = 18,
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ArgumentReg3 = 19,
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ArgumentReg4 = 20,
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ArgumentReg5 = 21,
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SyscallNumReg = ReturnValueReg,
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SyscallPseudoReturnReg = ArgumentReg4,
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SyscallSuccessReg = 19,
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LogVMPageSize = 13, // 8K bytes
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VMPageSize = (1 << LogVMPageSize),
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const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
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const int NumFloatRegs = NumFloatArchRegs;
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const int NumMiscRegs = NumMiscArchRegs;
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BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
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const int TotalNumRegs = NumIntRegs + NumFloatRegs +
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NumMiscRegs + 0/*NumInternalProcRegs*/;
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const int TotalDataRegs = NumIntRegs + NumFloatRegs;
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// Static instruction parameters
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const int MaxInstSrcRegs = 3;
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const int MaxInstDestRegs = 2;
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// semantically meaningful register indices
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const int ZeroReg = 31; // architecturally meaningful
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// the rest of these depend on the ABI
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const int StackPointerReg = 30;
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const int GlobalPointerReg = 29;
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const int ProcedureValueReg = 27;
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const int ReturnAddressReg = 26;
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const int ReturnValueReg = 0;
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const int FramePointerReg = 15;
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const int ArgumentReg0 = 16;
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const int ArgumentReg1 = 17;
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const int ArgumentReg2 = 18;
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const int ArgumentReg3 = 19;
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const int ArgumentReg4 = 20;
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const int ArgumentReg5 = 21;
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const int SyscallNumReg = ReturnValueReg;
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const int SyscallPseudoReturnReg = ArgumentReg4;
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const int SyscallSuccessReg = 19;
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const int LogVMPageSize = 13; // 8K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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WordBytes = 4,
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HalfwordBytes = 2,
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ByteBytes = 1,
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DepNA = 0,
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};
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// These enumerate all the registers for dependence tracking.
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enum DependenceTags {
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@ -402,15 +412,6 @@ extern const Addr PageOffset;
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};
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#endif
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enum {
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TotalNumRegs =
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NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
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};
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enum {
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TotalDataRegs = NumIntRegs + NumFloatRegs
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};
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typedef union {
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IntReg intreg;
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FloatReg fpreg;
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@ -27,7 +27,7 @@
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*/
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#include "arch/mips/process.hh"
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#include "arch/mips/linux/process.hh"
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#include "arch/mips/linux_process.hh"
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#include "base/loader/object_file.hh"
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#include "base/misc.hh"
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@ -961,6 +961,9 @@ SimpleCPU::tick()
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#define IFETCH_FLAGS(pc) 0
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#endif
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DPRINTF(Fetch,"Fetching PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
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cpuXC->readNextPC(),cpuXC->readNextNPC());
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#if SIMPLE_CPU_MEM_TIMING
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CpuRequest *ifetch_req = new CpuRequest();
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ifetch_req->size = sizeof(MachInst);
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@ -1077,7 +1080,7 @@ SimpleCPU::tick()
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#if FULL_SYSTEM
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fault->invoke(xcProxy);
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#else // !FULL_SYSTEM
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fatal("fault (%d) detected @ PC %08p", fault, cpuXC->readPC());
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fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
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#endif // FULL_SYSTEM
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}
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else {
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@ -363,6 +363,7 @@ LiveProcess::startup()
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Addr prog_entry = objFile->entryPoint();
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execContexts[0]->setPC(prog_entry);
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execContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
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execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
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num_processes++;
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}
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