Clean up clock phase drift code a bit.
src/cpu/base.cc: Move clock phase drift code to the base CPU so that any CPU model can use it. src/cpu/base.hh: Added two functions to help get the next cycle the CPU should be scheduled. src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Use the function now in BaseCPU. --HG-- extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
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4 changed files with 45 additions and 19 deletions
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@ -259,6 +259,26 @@ BaseCPU::regStats()
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#endif
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}
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Tick
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BaseCPU::nextCycle()
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{
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Tick next_tick = curTick + clock - 1;
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next_tick -= (next_tick % clock);
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return next_tick;
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}
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Tick
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BaseCPU::nextCycle(Tick begin_tick)
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{
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Tick next_tick = begin_tick;
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while (next_tick < curTick)
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next_tick += clock;
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next_tick -= (next_tick % clock);
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assert(next_tick >= curTick);
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return next_tick;
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}
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void
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BaseCPU::registerThreadContexts()
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@ -73,6 +73,20 @@ class BaseCPU : public MemObject
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inline Tick cycles(int numCycles) const { return clock * numCycles; }
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inline Tick curCycle() const { return curTick / clock; }
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/** The next cycle the CPU should be scheduled, given a cache
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* access or quiesce event returning on this cycle. This function
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* may return curTick if the CPU should run on the current cycle.
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*/
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Tick nextCycle();
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/** The next cycle the CPU should be scheduled, given a cache
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* access or quiesce event returning on the given Tick. This
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* function may return curTick if the CPU should run on the
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* current cycle.
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* @param begin_tick The tick that the event is completing on.
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*/
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Tick nextCycle(Tick begin_tick);
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#if FULL_SYSTEM
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protected:
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uint64_t interrupts[TheISA::NumInterruptLevels];
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@ -180,9 +180,7 @@ AtomicSimpleCPU::resume()
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changeState(SimObject::Running);
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if (thread->status() == ThreadContext::Active) {
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if (!tickEvent.scheduled()) {
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Tick nextTick = curTick + cycles(1) - 1;
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nextTick -= (nextTick % (cycles(1)));
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tickEvent.schedule(nextTick);
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tickEvent.schedule(nextCycle());
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}
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}
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}
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@ -211,9 +209,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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_status = Running;
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Tick nextTick = curTick + cycles(1) - 1;
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nextTick -= (nextTick % (cycles(1)));
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tickEvent.schedule(nextTick);
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tickEvent.schedule(nextCycle());
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break;
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}
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}
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@ -231,9 +227,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
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notIdleFraction++;
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//Make sure ticks are still on multiples of cycles
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Tick nextTick = curTick + cycles(delay + 1) - 1;
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nextTick -= (nextTick % (cycles(1)));
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tickEvent.schedule(nextTick);
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tickEvent.schedule(nextCycle(curTick + cycles(delay)));
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_status = Running;
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}
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@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isResponse()) {
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// delay processing of returned data until next CPU clock edge
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Tick time = pkt->req->getTime();
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while (time < curTick)
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time += lat;
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Tick mem_time = pkt->req->getTime();
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Tick next_tick = cpu->nextCycle(mem_time);
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if (time == curTick)
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if (next_tick == curTick)
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cpu->completeIfetch(pkt);
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else
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tickEvent.schedule(pkt, time);
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tickEvent.schedule(pkt, next_tick);
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return true;
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}
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@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isResponse()) {
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// delay processing of returned data until next CPU clock edge
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Tick time = pkt->req->getTime();
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while (time < curTick)
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time += lat;
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Tick mem_time = pkt->req->getTime();
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Tick next_tick = cpu->nextCycle(mem_time);
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if (time == curTick)
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if (next_tick == curTick)
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cpu->completeDataAccess(pkt);
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else
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tickEvent.schedule(pkt, time);
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tickEvent.schedule(pkt, next_tick);
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return true;
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}
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