sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Hook up 16 bit thumb load/store multiple.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:02 -05:00
parent 51bde086d5
commit 64d6b6ebfd
2 changed files with 14 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/arch/arm/isa/decoder/thumb.isa
View file

@ -137,8 +137,7 @@
} }
} }
0x6: decode TOPCODE_12_11 { 0x6: decode TOPCODE_12_11 {
0x0: WarnUnimpl::stm(); // also stmia, stmea 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem();
0x1: WarnUnimpl::ldm(); // also ldmia, ldmea
default: decode TOPCODE_11_8 { default: decode TOPCODE_11_8 {
0xe: WarnUnimpl::undefined(); // permanently undefined 0xe: WarnUnimpl::undefined(); // permanently undefined
0xf: WarnUnimpl::svc(); // formerly swi 0xf: WarnUnimpl::svc(); // formerly swi

13
src/arch/arm/isa/formats/macromem.isa
View file

@ -43,3 +43,16 @@ def format ArmMacroMem() {{
PSRUSER, WRITEBACK, LOADOP, machInst.regList); PSRUSER, WRITEBACK, LOADOP, machInst.regList);
''' '''
}}; }};
def format Thumb16MacroMem() {{
decode_block = '''
{
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
const bool load = (bits(machInst, 11) == 1);
const uint32_t regList = bits(machInst, 7, 0);
const bool writeback = (!load || bits(regList, rn) == 0);
return new LdmStm(machInst, rn, true, true, false,
writeback, load, regList);
}
'''
}};