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Need config read/write latency.

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--HG--
extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
This commit is contained in:
Kevin Lim 2006-07-27 16:43:02 -04:00
parent f9729e999f
commit 64b7213046
5 changed files with 13 additions and 0 deletions
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3
src/dev/ide_ctrl.cc
View file

@ -756,6 +756,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
Param<uint32_t> pci_dev; Param<uint32_t> pci_dev;
Param<uint32_t> pci_func; Param<uint32_t> pci_func;
Param<Tick> pio_latency; Param<Tick> pio_latency;
Param<Tick> config_latency;
SimObjectVectorParam<IdeDisk *> disks; SimObjectVectorParam<IdeDisk *> disks;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController) END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
@ -769,6 +770,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(pci_dev, "PCI device number"), INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(disks, "IDE disks attached to this controller") INIT_PARAM(disks, "IDE disks attached to this controller")
END_INIT_SIM_OBJECT_PARAMS(IdeController) END_INIT_SIM_OBJECT_PARAMS(IdeController)
@ -784,6 +786,7 @@ CREATE_SIM_OBJECT(IdeController)
params->deviceNum = pci_dev; params->deviceNum = pci_dev;
params->functionNum = pci_func; params->functionNum = pci_func;
params->pio_delay = pio_latency; params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->disks = disks; params->disks = disks;
return new IdeController(params); return new IdeController(params);
} }

3
src/dev/ns_gige.cc
View file

@ -2815,6 +2815,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<uint32_t> pci_dev; Param<uint32_t> pci_dev;
Param<uint32_t> pci_func; Param<uint32_t> pci_func;
Param<Tick> pio_latency; Param<Tick> pio_latency;
Param<Tick> config_latency;
Param<Tick> clock; Param<Tick> clock;
Param<bool> dma_desc_free; Param<bool> dma_desc_free;
@ -2848,6 +2849,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(pci_dev, "PCI device number"), INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(clock, "State machine cycle time"), INIT_PARAM(clock, "State machine cycle time"),
INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"), INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
@ -2885,6 +2887,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->deviceNum = pci_dev; params->deviceNum = pci_dev;
params->functionNum = pci_func; params->functionNum = pci_func;
params->pio_delay = pio_latency; params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->clock = clock; params->clock = clock;
params->dma_desc_free = dma_desc_free; params->dma_desc_free = dma_desc_free;

3
src/dev/sinic.cc
View file

@ -1639,6 +1639,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<uint32_t> pci_dev; Param<uint32_t> pci_dev;
Param<uint32_t> pci_func; Param<uint32_t> pci_func;
Param<Tick> pio_latency; Param<Tick> pio_latency;
Param<Tick> config_latency;
Param<Tick> intr_delay; Param<Tick> intr_delay;
Param<Tick> clock; Param<Tick> clock;
@ -1681,6 +1682,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(pci_dev, "PCI device number"), INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(intr_delay, "Interrupt Delay"), INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(clock, "State machine cycle time"), INIT_PARAM(clock, "State machine cycle time"),
@ -1725,6 +1727,7 @@ CREATE_SIM_OBJECT(Device)
params->deviceNum = pci_dev; params->deviceNum = pci_dev;
params->functionNum = pci_func; params->functionNum = pci_func;
params->pio_delay = pio_latency; params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->intr_delay = intr_delay; params->intr_delay = intr_delay;
params->clock = clock; params->clock = clock;

2
src/python/m5/objects/Ethernet.py
View file

@ -68,6 +68,8 @@ class EtherDevBase(PciDevice):
clock = Param.Clock('0ns', "State machine processor frequency") clock = Param.Clock('0ns', "State machine processor frequency")
config_latency = Param.Latency('20ns', "Config read or write latency")
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")

2
src/python/m5/objects/Ide.py
View file

@ -36,4 +36,6 @@ class IdeController(PciDevice):
type = 'IdeController' type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller") disks = VectorParam.IdeDisk("IDE disks attached to this controller")
config_latency = Param.Latency('20ns', "Config read or write latency")
configdata =IdeControllerPciData() configdata =IdeControllerPciData()