tests: Reflect name change in DRAM tests
This patch reflects the recent name change in the DRAM TrafficGen tests and also tidies up the test directory. --HG-- rename : tests/configs/tgen-simple-dram.py => tests/configs/tgen-dram-ctrl.py rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt rename : tests/quick/se/70.tgen/tgen-simple-dram.cfg => tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
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f800f268db
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64806c4c13
14 changed files with 14 additions and 63 deletions
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@ -334,7 +334,7 @@ if env['TARGET_ISA'] == 'x86':
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configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
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'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
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'inorder-timing', 'rubytest', 'tgen-simple-mem',
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'tgen-simple-dram']
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'tgen-dram-ctrl']
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if env['PROTOCOL'] != 'None':
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if env['PROTOCOL'] == 'MI_example':
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@ -45,7 +45,7 @@ require_sim_object("CommMonitor")
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# even if this is only a traffic generator, call it cpu to make sure
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# the scripts are happy
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cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
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cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-dram-ctrl.cfg")
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# system simulated
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system = System(cpu = cpu, physmem = DDR3_1600_x64(),
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@ -1,7 +0,0 @@
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r,64,64,4000
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r,128,64,5000
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r,196,64,6000
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r,256,64,7000
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r,3453276,64,8000
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r,320,64,9000
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r,232123,64,500000
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@ -1,6 +0,0 @@
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r,64,64,4000
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r,2048,64,5000
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r,128,64,6000
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r,196,64,7000
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r,12433,64,8000
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r,23223,64,1000000
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@ -1,3 +0,0 @@
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r,64,64,4000
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r, 128, 64, 7800001
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r, 196, 64, 100000000
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@ -1,5 +0,0 @@
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r, 64, 64, 4000
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w, 128, 64, 6000
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r, 196, 64, 8000
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r, 128, 64, 10000
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r, 123143,64,100000
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@ -1,26 +0,0 @@
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w,64,64,4000
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w,128,64,5000
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w,196,64,6000
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w,256,64,7000
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w,345376,64,8000
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w,23223,64,10000
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w,12367,64,11000
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w,15328,64,12000
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w,19346,64,13000
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w,26456,64,14000
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w,34576,64,15000
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w,33620,64,16000
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w,2323,64,17000
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w,67354,64,18000
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w,1258,64,19000
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w,196,64,20000
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w,256,64,21000
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w,3276,64,22000
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w,14234,64,23000
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w,23123,64,24000
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w,23333,64,25000
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w,35318,64,26000
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w,32542,64,27000
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w,8576,64,28000
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w,34576,64,29000
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w,326660,64,30000000
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@ -22,6 +22,10 @@
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# be set to the same value.
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STATE 0 100 IDLE
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STATE 1 1000000000 LINEAR 100 0 134217728 64 30000 30000 0
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STATE 2 1000000 IDLE
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STATE 3 1000000000 RANDOM 50 0 134217728 64 28000 32000 0
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INIT 0
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TRANSITION 0 1 1
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TRANSITION 1 1 1
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TRANSITION 1 2 1
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TRANSITION 2 3 1
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TRANSITION 3 3 1
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@ -1,6 +0,0 @@
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r,64,64,4000
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r,2048,64,5000
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r,128,64,6000
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r,196,64,7000
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r,12433,64,8000
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r,23223,64,1000000
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