merge
--HG-- extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
This commit is contained in:
Nathan Binkert
commit
64295b800f
68 changed files with 1968 additions and 963 deletions
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@ -43,3 +43,10 @@ class L2Cache(BaseCache):
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mshrs = 20
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tgts_per_mshr = 12
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class IOCache(BaseCache):
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assoc = 8
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block_size = 64
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latency = '10ns'
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mshrs = 20
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size = '1kB'
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tgts_per_mshr = 12
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@ -53,7 +53,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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@ -32,6 +32,7 @@ parser.add_option("-t", "--timing", action="store_true")
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parser.add_option("-n", "--num_cpus", type="int", default=1)
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parser.add_option("--caches", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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parser.add_option("--fastmem", action="store_true")
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# Run duration options
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parser.add_option("-m", "--maxtick", type="int")
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@ -121,12 +121,20 @@ for i in xrange(np):
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if options.caches:
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test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
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test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
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test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
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cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
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test_sys.iocache.cpu_side = test_sys.iobus.port
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test_sys.iocache.mem_side = test_sys.membus.port
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if options.l2cache:
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test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
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else:
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test_sys.cpu[i].connectMemPorts(test_sys.membus)
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if options.fastmem:
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test_sys.cpu[i].physmem_port = test_sys.physmem.port
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if len(bm) == 2:
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if m5.build_env['TARGET_ISA'] == 'alpha':
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drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
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@ -134,6 +142,8 @@ if len(bm) == 2:
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drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.connectMemPorts(drive_sys.membus)
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if options.fastmem:
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drive_sys.cpu.physmem_port = drive_sys.physmem.port
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if options.kernel is not None:
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drive_sys.kernel = binary(options.kernel)
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@ -114,6 +114,9 @@ for i in xrange(np):
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system.cpu[i].connectMemPorts(system.membus)
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system.cpu[i].workload = process
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if options.fastmem:
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system.cpu[0].physmem_port = system.physmem.port
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root = Root(system = system)
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Simulation.run(options, root, system, FutureClass)
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@ -64,6 +64,7 @@ TLB::TLB(const string &name, int s)
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{
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table = new PTE[size];
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memset(table, 0, sizeof(PTE[size]));
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flushCache();
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}
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TLB::~TLB()
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@ -74,11 +75,26 @@ TLB::~TLB()
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// look up an entry in the TLB
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PTE *
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TLB::lookup(Addr vpn, uint8_t asn) const
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TLB::lookup(Addr vpn, uint8_t asn)
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{
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// assume not found...
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PTE *retval = NULL;
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if (PTECache[0]) {
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if (vpn == PTECache[0]->tag &&
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(PTECache[0]->asma || PTECache[0]->asn == asn))
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retval = PTECache[0];
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else if (PTECache[1]) {
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if (vpn == PTECache[1]->tag &&
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(PTECache[1]->asma || PTECache[1]->asn == asn))
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retval = PTECache[1];
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else if (PTECache[2] && vpn == PTECache[2]->tag &&
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(PTECache[2]->asma || PTECache[2]->asn == asn))
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retval = PTECache[2];
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}
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}
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if (retval == NULL) {
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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@ -86,13 +102,14 @@ TLB::lookup(Addr vpn, uint8_t asn) const
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PTE *pte = &table[index];
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assert(pte->valid);
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if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
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retval = pte;
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retval = updateCache(pte);
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break;
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}
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++i;
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}
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}
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}
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DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
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retval ? "hit" : "miss", retval ? retval->ppn : 0);
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@ -142,6 +159,7 @@ TLB::checkCacheability(RequestPtr &req)
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void
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TLB::insert(Addr addr, PTE &pte)
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{
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flushCache();
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VAddr vaddr = addr;
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if (table[nlu].valid) {
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Addr oldvpn = table[nlu].tag;
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@ -178,6 +196,7 @@ TLB::flushAll()
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{
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DPRINTF(TLB, "flushAll\n");
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memset(table, 0, sizeof(PTE[size]));
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flushCache();
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lookupTable.clear();
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nlu = 0;
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}
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@ -185,6 +204,7 @@ TLB::flushAll()
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void
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TLB::flushProcesses()
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{
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flushCache();
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PageTable::iterator i = lookupTable.begin();
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PageTable::iterator end = lookupTable.end();
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while (i != end) {
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@ -208,6 +228,7 @@ TLB::flushProcesses()
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void
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TLB::flushAddr(Addr addr, uint8_t asn)
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{
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flushCache();
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VAddr vaddr = addr;
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PageTable::iterator i = lookupTable.find(vaddr.vpn());
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@ -291,7 +312,7 @@ ITB::regStats()
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Fault
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ITB::translate(RequestPtr &req, ThreadContext *tc) const
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ITB::translate(RequestPtr &req, ThreadContext *tc)
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{
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//If this is a pal pc, then set PHYSICAL
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if(FULL_SYSTEM && PcPAL(req->getPC()))
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@ -453,7 +474,7 @@ DTB::regStats()
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}
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Fault
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DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
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DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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{
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Addr pc = tc->readPC();
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@ -61,7 +61,7 @@ namespace AlphaISA
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int nlu; // not last used entry (for replacement)
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void nextnlu() { if (++nlu >= size) nlu = 0; }
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PTE *lookup(Addr vpn, uint8_t asn) const;
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PTE *lookup(Addr vpn, uint8_t asn);
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public:
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TLB(const std::string &name, int size);
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@ -88,6 +88,16 @@ namespace AlphaISA
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// Checkpointing
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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// Most recently used page table entries
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PTE *PTECache[3];
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inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); }
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inline PTE* updateCache(PTE *pte) {
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PTECache[2] = PTECache[1];
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PTECache[1] = PTECache[0];
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PTECache[0] = pte;
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return pte;
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}
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};
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class ITB : public TLB
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@ -102,7 +112,7 @@ namespace AlphaISA
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ITB(const std::string &name, int size);
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virtual void regStats();
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Fault translate(RequestPtr &req, ThreadContext *tc) const;
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Fault translate(RequestPtr &req, ThreadContext *tc);
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};
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class DTB : public TLB
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@ -125,7 +135,7 @@ namespace AlphaISA
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DTB(const std::string &name, int size);
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virtual void regStats();
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Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
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Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
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};
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}
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@ -1464,6 +1464,25 @@ class MemOperand(Operand):
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def makeAccSize(self):
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return self.size
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class UPCOperand(Operand):
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def makeConstructor(self):
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return ''
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def makeRead(self):
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return '%s = xc->readMicroPC();\n' % self.base_name
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def makeWrite(self):
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return 'xc->setMicroPC(%s);\n' % self.base_name
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class NUPCOperand(Operand):
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def makeConstructor(self):
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return ''
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def makeRead(self):
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return '%s = xc->readNextMicroPC();\n' % self.base_name
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def makeWrite(self):
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return 'xc->setNextMicroPC(%s);\n' % self.base_name
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class NPCOperand(Operand):
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def makeConstructor(self):
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@ -69,19 +69,23 @@ namespace X86ISA
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DPRINTF(Sparc, "flagMask = %#x\n", flagMask);
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uint64_t flags = oldFlags & ~flagMask;
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if(flagMask & CFBit)
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{
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if(findCarry(dataSize*8, _dest, _src1, _src2))
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flags |= CFBit;
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if(subtract)
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flags ^= CFBit;
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}
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if(flagMask & PFBit && findParity(dataSize*8, _dest))
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flags |= PFBit;
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if(flagMask & ECFBit && findCarry(dataSize*8, _dest, _src1, _src2))
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flags |= ECFBit;
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if(flagMask & AFBit)
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{
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if(findCarry(4, _dest, _src1, _src2))
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flags |= AFBit;
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if(subtract)
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flags ^= AFBit;
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}
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if(flagMask & EZFBit && findZero(dataSize*8, _dest))
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flags |= EZFBit;
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if(flagMask & ZFBit && findZero(dataSize*8, _dest))
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@ -112,8 +116,9 @@ namespace X86ISA
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panic("This condition is not implemented!");
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case ConditionTests::MSTRC:
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panic("This condition is not implemented!");
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case ConditionTests::STRZnZF:
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panic("This condition is not implemented!");
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case ConditionTests::STRZnEZF:
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return !ccflags.EZF & ccflags.ZF;
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//And no interrupts or debug traps are waiting
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case ConditionTests::OF:
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return ccflags.OF;
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case ConditionTests::CF:
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|
@ -144,8 +149,9 @@ namespace X86ISA
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panic("This condition is not implemented!");
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case ConditionTests::NotMSTRC:
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panic("This condition is not implemented!");
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case ConditionTests::NotSTRZnZF:
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panic("This condition is not implemented!");
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case ConditionTests::STRnZnEZF:
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return !ccflags.EZF & !ccflags.ZF;
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//And no interrupts or debug traps are waiting
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case ConditionTests::NotOF:
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return !ccflags.OF;
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case ConditionTests::NotCF:
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|
|
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|
@ -73,7 +73,7 @@ namespace X86ISA
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MSTRZ,
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STRZ,
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MSTRC,
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STRZnZF,
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STRZnEZF,
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OF,
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CF,
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ZF,
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|
@ -91,7 +91,7 @@ namespace X86ISA
|
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NotMSTRZ,
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NotSTRZ,
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NotMSTRC,
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NotSTRZnZF,
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STRnZnEZF,
|
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NotOF,
|
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NotCF,
|
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NotZF,
|
||||
|
|
|
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|
|
@ -342,8 +342,8 @@
|
|||
0x3: stos_Yv_rAX();
|
||||
0x4: lods_Al_Xb();
|
||||
0x5: lods_rAX_Xv();
|
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0x6: scas_Yb_Al();
|
||||
0x7: scas_Yv_rAX();
|
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0x6: StringInst::SCAS(Yb);
|
||||
0x7: StringInst::SCAS(Yv);
|
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}
|
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format Inst {
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0x16: MOV(Bb,Ib);
|
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|
|
|
|||
|
|
@ -99,6 +99,10 @@
|
|||
//thing on a variety of inputs
|
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##include "multi.isa"
|
||||
|
||||
//Include a format which implements an extra layer of decoding to handle the
|
||||
//repe and repne prefixes
|
||||
##include "string.isa"
|
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|
||||
//Include a format which makes instructions who's sole purpose is to generate
|
||||
//a syscall.
|
||||
##include "syscall.isa"
|
||||
|
|
|
|||
88
src/arch/x86/isa/formats/string.isa
Normal file
88
src/arch/x86/isa/formats/string.isa
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 The Hewlett-Packard Development Company
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use of this software in source and binary forms,
|
||||
// with or without modification, are permitted provided that the
|
||||
// following conditions are met:
|
||||
//
|
||||
// The software must be used only for Non-Commercial Use which means any
|
||||
// use which is NOT directed to receiving any direct monetary
|
||||
// compensation for, or commercial advantage from such use. Illustrative
|
||||
// examples of non-commercial use are academic research, personal study,
|
||||
// teaching, education and corporate research & development.
|
||||
// Illustrative examples of commercial use are distributing products for
|
||||
// commercial advantage and providing services using the software for
|
||||
// commercial advantage.
|
||||
//
|
||||
// If you wish to use this software or functionality therein that may be
|
||||
// covered by patents for commercial use, please contact:
|
||||
// Director of Intellectual Property Licensing
|
||||
// Office of Strategy and Technology
|
||||
// Hewlett-Packard Company
|
||||
// 1501 Page Mill Road
|
||||
// Palo Alto, California 94304
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer. Redistributions
|
||||
// in binary form must reproduce the above copyright notice, this list of
|
||||
// conditions and the following disclaimer in the documentation and/or
|
||||
// other materials provided with the distribution. Neither the name of
|
||||
// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission. No right of
|
||||
// sublicense is granted herewith. Derivatives of the software and
|
||||
// output created using the software may be prepared, but only for
|
||||
// Non-Commercial Uses. Derivatives of the software may be shared with
|
||||
// others provided: (i) the others agree to abide by the list of
|
||||
// conditions herein which includes the Non-Commercial Use restrictions;
|
||||
// and (ii) such Derivatives of the software include the above copyright
|
||||
// notice to acknowledge the contribution from this software where
|
||||
// applicable, this list of conditions and the disclaimer below.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Gabe Black
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// String Instructions
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
|
||||
def format StringInst(*opTypeSet) {{
|
||||
allBlocks = OutputBlocks()
|
||||
|
||||
regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv())
|
||||
eBlocks = specializeInst(Name + "_E", list(opTypeSet), EmulEnv())
|
||||
nBlocks = specializeInst(Name + "_N", list(opTypeSet), EmulEnv())
|
||||
|
||||
for blocks in (regBlocks, eBlocks, nBlocks):
|
||||
allBlocks.header_output += blocks.header_output
|
||||
allBlocks.decoder_output += blocks.decoder_output
|
||||
allBlocks.exec_output += blocks.exec_output
|
||||
|
||||
allBlocks.decode_block = '''
|
||||
if (LEGACY_REP) {
|
||||
%s
|
||||
} else if (LEGACY_REPNE) {
|
||||
%s
|
||||
} else {
|
||||
%s
|
||||
}
|
||||
''' % (eBlocks.decode_block, nBlocks.decode_block, regBlocks.decode_block)
|
||||
|
||||
(header_output, decoder_output,
|
||||
decode_block, exec_output) = allBlocks.makeList()
|
||||
}};
|
||||
|
|
@ -53,16 +53,55 @@
|
|||
#
|
||||
# Authors: Gabe Black
|
||||
|
||||
microcode = ""
|
||||
#let {{
|
||||
# class SCAS(Inst):
|
||||
# "GenFault ${new UnimpInstFault}"
|
||||
# class SCASB(Inst):
|
||||
# "GenFault ${new UnimpInstFault}"
|
||||
# class SCASW(Inst):
|
||||
# "GenFault ${new UnimpInstFault}"
|
||||
# class SCASD(Inst):
|
||||
# "GenFault ${new UnimpInstFault}"
|
||||
# class SCASQ(Inst):
|
||||
# "GenFault ${new UnimpInstFault}"
|
||||
#}};
|
||||
microcode = '''
|
||||
def macroop SCAS_M {
|
||||
# Find the constant we need to either add or subtract from rdi
|
||||
ruflag t0, 10
|
||||
movi t2, t2, dsz, flags=(CEZF,), dataSize=asz
|
||||
subi t3, t0, dsz, dataSize=asz
|
||||
mov t2, t2, t3, flags=(nCEZF,), dataSize=asz
|
||||
|
||||
ld t1, es, [1, t0, rdi]
|
||||
sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF)
|
||||
|
||||
add rdi, rdi, t2, dataSize=asz
|
||||
};
|
||||
|
||||
#
|
||||
# Versions which have the rep prefix. These could benefit from some loop
|
||||
# unrolling.
|
||||
#
|
||||
|
||||
def macroop SCAS_E_M {
|
||||
# Find the constant we need to either add or subtract from rdi
|
||||
ruflag t0, 10
|
||||
movi t2, t2, dsz, flags=(CEZF,), dataSize=asz
|
||||
subi t3, t0, dsz, dataSize=asz
|
||||
mov t2, t2, t3, flags=(nCEZF,), dataSize=asz
|
||||
|
||||
ld t1, es, [1, t0, rdi]
|
||||
sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF)
|
||||
|
||||
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
|
||||
add rdi, rdi, t2, dataSize=asz
|
||||
bri t0, 4, flags=(CSTRZnEZF,)
|
||||
fault "NoFault"
|
||||
};
|
||||
|
||||
def macroop SCAS_N_M {
|
||||
# Find the constant we need to either add or subtract from rdi
|
||||
ruflag t0, 10
|
||||
movi t2, t2, dsz, flags=(CEZF,), dataSize=asz
|
||||
subi t3, t0, dsz, dataSize=asz
|
||||
mov t2, t2, t3, flags=(nCEZF,), dataSize=asz
|
||||
|
||||
ld t1, es, [1, t0, rdi]
|
||||
sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF)
|
||||
|
||||
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
|
||||
add rdi, rdi, t2, dataSize=asz
|
||||
bri t0, 4, flags=(CSTRnZnEZF,)
|
||||
fault "NoFault"
|
||||
};
|
||||
|
||||
'''
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ let {{
|
|||
"index" : "env.index",
|
||||
"base" : "env.base",
|
||||
"dsz" : "env.dataSize",
|
||||
"osz" : "env.operandSize",
|
||||
"asz" : "env.addressSize",
|
||||
"ssz" : "env.stackSize"
|
||||
}
|
||||
assembler.symbols.update(symbols)
|
||||
|
|
@ -107,11 +107,13 @@ let {{
|
|||
assembler.symbols[flag] = flag + "Bit"
|
||||
|
||||
for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
|
||||
'MSTRZ', 'STRZ', 'MSTRC', 'STRZnZF',
|
||||
'MSTRZ', 'STRZ', 'MSTRC',
|
||||
'OF', 'CF', 'ZF', 'CvZF',
|
||||
'SF', 'PF', 'SxOF', 'SxOvZF'):
|
||||
assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
|
||||
assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
|
||||
assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
|
||||
assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
|
||||
|
||||
assembler.symbols["CTrue"] = "ConditionTests::True"
|
||||
assembler.symbols["CFalse"] = "ConditionTests::False"
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ def template MicroRegOpExecute {{
|
|||
}};
|
||||
|
||||
def template MicroRegOpImmExecute {{
|
||||
Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
|
@ -140,21 +140,21 @@ def template MicroRegOpDeclare {{
|
|||
|
||||
def template MicroRegOpImmDeclare {{
|
||||
|
||||
class %(class_name)sImm : public %(base_class)s
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
protected:
|
||||
void buildMe();
|
||||
|
||||
public:
|
||||
%(class_name)sImm(ExtMachInst _machInst,
|
||||
%(class_name)s(ExtMachInst _machInst,
|
||||
const char * instMnem,
|
||||
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
|
||||
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
|
||||
RegIndex _src1, uint16_t _imm8, RegIndex _dest,
|
||||
uint8_t _dataSize, uint16_t _ext);
|
||||
|
||||
%(class_name)sImm(ExtMachInst _machInst,
|
||||
%(class_name)s(ExtMachInst _machInst,
|
||||
const char * instMnem,
|
||||
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
|
||||
RegIndex _src1, uint16_t _imm8, RegIndex _dest,
|
||||
uint8_t _dataSize, uint16_t _ext);
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
|
@ -196,14 +196,14 @@ def template MicroRegOpConstructor {{
|
|||
|
||||
def template MicroRegOpImmConstructor {{
|
||||
|
||||
inline void %(class_name)sImm::buildMe()
|
||||
inline void %(class_name)s::buildMe()
|
||||
{
|
||||
%(constructor)s;
|
||||
}
|
||||
|
||||
inline %(class_name)sImm::%(class_name)sImm(
|
||||
inline %(class_name)s::%(class_name)s(
|
||||
ExtMachInst machInst, const char * instMnem,
|
||||
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
|
||||
RegIndex _src1, uint16_t _imm8, RegIndex _dest,
|
||||
uint8_t _dataSize, uint16_t _ext) :
|
||||
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
|
||||
false, false, false, false,
|
||||
|
|
@ -213,10 +213,10 @@ def template MicroRegOpImmConstructor {{
|
|||
buildMe();
|
||||
}
|
||||
|
||||
inline %(class_name)sImm::%(class_name)sImm(
|
||||
inline %(class_name)s::%(class_name)s(
|
||||
ExtMachInst machInst, const char * instMnem,
|
||||
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
|
||||
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
|
||||
RegIndex _src1, uint16_t _imm8, RegIndex _dest,
|
||||
uint8_t _dataSize, uint16_t _ext) :
|
||||
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
|
||||
isMicro, isDelayed, isFirst, isLast,
|
||||
|
|
@ -310,7 +310,7 @@ let {{
|
|||
exec_output = ""
|
||||
|
||||
# A function which builds the C++ classes that implement the microops
|
||||
def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
|
||||
def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";", imm=False):
|
||||
global header_output
|
||||
global decoder_output
|
||||
global exec_output
|
||||
|
|
@ -321,6 +321,11 @@ let {{
|
|||
"flag_code" : flagCode,
|
||||
"cond_check" : condCheck,
|
||||
"else_code" : elseCode})
|
||||
if imm:
|
||||
header_output += MicroRegOpImmDeclare.subst(iop)
|
||||
decoder_output += MicroRegOpImmConstructor.subst(iop)
|
||||
exec_output += MicroRegOpImmExecute.subst(iop)
|
||||
else:
|
||||
header_output += MicroRegOpDeclare.subst(iop)
|
||||
decoder_output += MicroRegOpConstructor.subst(iop)
|
||||
exec_output += MicroRegOpExecute.subst(iop)
|
||||
|
|
@ -397,10 +402,11 @@ let {{
|
|||
|
||||
microopClasses[name + 'i'] = RegOpChildImm
|
||||
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
|
||||
immCode, imm=True);
|
||||
setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
|
||||
immCode, flagCode=immFlagCode,
|
||||
condCheck=condCode, elseCode=elseCode);
|
||||
condCheck=condCode, elseCode=elseCode, imm=True);
|
||||
|
||||
# This has it's own function because Wr ops have implicit destinations
|
||||
def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
|
||||
|
|
@ -434,9 +440,11 @@ let {{
|
|||
|
||||
microopClasses[name + 'i'] = RegOpChildImm
|
||||
|
||||
setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
|
||||
setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
|
||||
condCheck = checkCCFlagBits, elseCode = elseCode);
|
||||
setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", \
|
||||
immCode, imm=True);
|
||||
setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", \
|
||||
immCode, condCheck = checkCCFlagBits, elseCode = elseCode, \
|
||||
imm=True);
|
||||
|
||||
# This has it's own function because Rd ops don't always have two parameters
|
||||
def defineMicroRegOpRd(mnemonic, code):
|
||||
|
|
@ -444,29 +452,52 @@ let {{
|
|||
name = mnemonic.lower()
|
||||
|
||||
class RegOpChild(RegOp):
|
||||
className = Name
|
||||
mnemonic = name
|
||||
def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
|
||||
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
|
||||
|
||||
def defineMicroRegOpImm(mnemonic, code):
|
||||
def defineMicroRegOpImm(mnemonic, code, flagCode=""):
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
code = immPick + code
|
||||
|
||||
class RegOpChild(RegOpImm):
|
||||
def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
className = Name
|
||||
mnemonic = name
|
||||
def __init__(self, dest, src1, src2, \
|
||||
flags=None, dataSize="env.dataSize"):
|
||||
super(RegOpChild, self).__init__(dest, \
|
||||
src1, src2, flags, dataSize)
|
||||
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
|
||||
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
|
||||
code, flagCode=flagCode, imm=True);
|
||||
|
||||
def defineMicroRegOpRdImm(mnemonic, code, flagCode=""):
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
code = immPick + code
|
||||
|
||||
class RegOpChildRdImm(RegOpImm):
|
||||
className = Name
|
||||
mnemonic = name
|
||||
def __init__(self, dest, imm, flags=None, \
|
||||
dataSize="env.dataSize"):
|
||||
super(RegOpChildRdImm, self).__init__(dest, \
|
||||
"NUM_INTREGS", imm, flags, dataSize)
|
||||
|
||||
microopClasses[name] = RegOpChildRdImm
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
|
||||
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
|
||||
code, flagCode=flagCode, imm=True);
|
||||
|
||||
defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)')
|
||||
defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);',
|
||||
|
|
@ -615,12 +646,17 @@ let {{
|
|||
''')
|
||||
|
||||
defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
|
||||
defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;')
|
||||
defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
|
||||
|
||||
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
|
||||
defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
|
||||
defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
|
||||
flagCode = genCCFlagBitsLogic)
|
||||
defineMicroRegOpRdImm('Ruflag', '''
|
||||
int flag = bits(ccFlagBits, (1 << imm8) + 0*psrc1);
|
||||
DestReg = merge(DestReg, flag, dataSize);
|
||||
ccFlagBits = ccFlagBits & ~EZFBit;
|
||||
ccFlagBits = ccFlagBits | ((flag == 0) ? EZFBit : 0);
|
||||
''')
|
||||
|
||||
defineMicroRegOpImm('Sext', '''
|
||||
IntReg val = psrc1;
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@ def operands {{
|
|||
'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
|
||||
'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
|
||||
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
|
||||
'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
|
||||
'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
|
||||
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
|
||||
'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
|
||||
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
|
||||
|
|
|
|||
|
|
@ -40,11 +40,13 @@
|
|||
#define M5_ATTR_NORETURN __attribute__((noreturn))
|
||||
#define M5_PRAGMA_NORETURN(x)
|
||||
#define M5_DUMMY_RETURN
|
||||
#define M5_VAR_USED __attribute__((unused))
|
||||
#elif defined(__SUNPRO_CC)
|
||||
// this doesn't do anything with sun cc, but why not
|
||||
#define M5_ATTR_NORETURN __sun_attr__((__noreturn__))
|
||||
#define M5_DUMMY_RETURN return (0);
|
||||
#define DO_PRAGMA(x) _Pragma(#x)
|
||||
#define M5_VAR_USED
|
||||
#define M5_PRAGMA_NORETURN(x) DO_PRAGMA(does_not_return(x))
|
||||
#else
|
||||
#error "Need to define compiler options in base/compiler.hh"
|
||||
|
|
|
|||
55
src/base/range_ops.hh
Normal file
55
src/base/range_ops.hh
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2007 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Ali Saidi
|
||||
*/
|
||||
|
||||
#ifndef __BASE_RANGE_OPS_HH__
|
||||
#define __BASE_RANGE_OPS_HH__
|
||||
#include <list>
|
||||
#include <vector>
|
||||
|
||||
#include "base/range.hh"
|
||||
|
||||
template <class T>
|
||||
inline void
|
||||
FilterRangeList(std::vector<Range<T> > filter_list, std::list<Range<T> >
|
||||
&range_list) {
|
||||
typename std::list<Range<T> >::iterator i;
|
||||
for (int x = 0; x < filter_list.size(); x++) {
|
||||
for (i = range_list.begin(); i != range_list.end(); ) {
|
||||
// Is the range within one of our filter ranges?
|
||||
if (filter_list[x] == i->start || filter_list[x] == i->end)
|
||||
range_list.erase(i++);
|
||||
else
|
||||
i++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif //__BASE_RANGE_OPS_HH__
|
||||
|
||||
|
|
@ -93,10 +93,11 @@ class BaseCPU(SimObject):
|
|||
|
||||
def connectMemPorts(self, bus):
|
||||
for p in self._mem_ports:
|
||||
if p != 'physmem_port':
|
||||
exec('self.%s = bus.port' % p)
|
||||
|
||||
def addPrivateSplitL1Caches(self, ic, dc):
|
||||
assert(len(self._mem_ports) == 2)
|
||||
assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
|
||||
self.icache = ic
|
||||
self.dcache = dc
|
||||
self.icache_port = ic.cpu_side
|
||||
|
|
|
|||
|
|
@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU):
|
|||
profile = Param.Latency('0ns', "trace the kernel stack")
|
||||
icache_port = Port("Instruction Port")
|
||||
dcache_port = Port("Data Port")
|
||||
_mem_ports = ['icache_port', 'dcache_port']
|
||||
physmem_port = Port("Physical Memory Port")
|
||||
_mem_ports = ['icache_port', 'dcache_port', 'physmem_port']
|
||||
|
|
|
|||
|
|
@ -67,6 +67,10 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
|
|||
return &dcachePort;
|
||||
else if (if_name == "icache_port")
|
||||
return &icachePort;
|
||||
else if (if_name == "physmem_port") {
|
||||
hasPhysMemPort = true;
|
||||
return &physmemPort;
|
||||
}
|
||||
else
|
||||
panic("No Such Port\n");
|
||||
}
|
||||
|
|
@ -83,6 +87,12 @@ AtomicSimpleCPU::init()
|
|||
TheISA::initCPU(tc, tc->readCpuId());
|
||||
}
|
||||
#endif
|
||||
if (hasPhysMemPort) {
|
||||
bool snoop = false;
|
||||
AddrRangeList pmAddrList;
|
||||
physmemPort.getPeerAddressRanges(pmAddrList, snoop);
|
||||
physMemAddr = *pmAddrList.begin();
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
|
|
@ -141,7 +151,8 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
|
|||
AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
|
||||
: BaseSimpleCPU(p), tickEvent(this),
|
||||
width(p->width), simulate_stalls(p->simulate_stalls),
|
||||
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
|
||||
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
|
||||
physmemPort(name() + "-iport", this), hasPhysMemPort(false)
|
||||
{
|
||||
_status = Idle;
|
||||
|
||||
|
|
@ -293,8 +304,12 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
|
|||
|
||||
if (req->isMmapedIpr())
|
||||
dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
|
||||
else {
|
||||
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
|
||||
dcache_latency = physmemPort.sendAtomic(&pkt);
|
||||
else
|
||||
dcache_latency = dcachePort.sendAtomic(&pkt);
|
||||
}
|
||||
dcache_access = true;
|
||||
assert(!pkt.isError());
|
||||
|
||||
|
|
@ -402,6 +417,9 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|||
dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
|
||||
} else {
|
||||
data = htog(data);
|
||||
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
|
||||
dcache_latency = physmemPort.sendAtomic(&pkt);
|
||||
else
|
||||
dcache_latency = dcachePort.sendAtomic(&pkt);
|
||||
}
|
||||
dcache_access = true;
|
||||
|
|
@ -513,7 +531,12 @@ AtomicSimpleCPU::tick()
|
|||
Packet::Broadcast);
|
||||
ifetch_pkt.dataStatic(&inst);
|
||||
|
||||
if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
|
||||
icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
|
||||
else
|
||||
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
|
||||
|
||||
|
||||
// ifetch_req is initialized to read the instruction directly
|
||||
// into the CPU object's inst field.
|
||||
//}
|
||||
|
|
|
|||
|
|
@ -121,6 +121,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
|
|||
};
|
||||
DcachePort dcachePort;
|
||||
|
||||
CpuPort physmemPort;
|
||||
bool hasPhysMemPort;
|
||||
Request ifetch_req;
|
||||
Request data_read_req;
|
||||
Request data_write_req;
|
||||
|
|
@ -128,6 +130,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
|
|||
bool dcache_access;
|
||||
Tick dcache_latency;
|
||||
|
||||
Range<Addr> physMemAddr;
|
||||
|
||||
public:
|
||||
|
||||
virtual Port *getPort(const std::string &if_name, int idx = -1);
|
||||
|
|
|
|||
|
|
@ -291,11 +291,15 @@ class BaseSimpleCPU : public BaseCPU
|
|||
}
|
||||
|
||||
uint64_t readPC() { return thread->readPC(); }
|
||||
uint64_t readMicroPC() { return thread->readMicroPC(); }
|
||||
uint64_t readNextPC() { return thread->readNextPC(); }
|
||||
uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
|
||||
uint64_t readNextNPC() { return thread->readNextNPC(); }
|
||||
|
||||
void setPC(uint64_t val) { thread->setPC(val); }
|
||||
void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
|
||||
void setNextPC(uint64_t val) { thread->setNextPC(val); }
|
||||
void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
|
||||
void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
|
||||
|
||||
MiscReg readMiscRegNoEffect(int misc_reg)
|
||||
|
|
|
|||
|
|
@ -353,9 +353,7 @@ class StaticInst : public StaticInstBase
|
|||
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
|
||||
: StaticInstBase(__opClass),
|
||||
machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
|
||||
{
|
||||
memset(&recentDecodes, 0, 2 * sizeof(cacheElement));
|
||||
}
|
||||
{ }
|
||||
|
||||
public:
|
||||
|
||||
|
|
@ -459,6 +457,9 @@ class StaticInst : public StaticInstBase
|
|||
struct cacheElement {
|
||||
Addr page_addr;
|
||||
AddrDecodePage *decodePage;
|
||||
|
||||
cacheElement()
|
||||
:decodePage(NULL) { }
|
||||
} ;
|
||||
|
||||
/// An array of recently decoded instructions.
|
||||
|
|
|
|||
|
|
@ -266,8 +266,7 @@ class DmaDevice : public PioDevice
|
|||
|
||||
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
|
||||
{
|
||||
dmaPort->dmaAction(MemCmd::WriteInvalidateReq,
|
||||
addr, size, event, data);
|
||||
dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data);
|
||||
}
|
||||
|
||||
void dmaRead(Addr addr, int size, Event *event, uint8_t *data)
|
||||
|
|
|
|||
|
|
@ -40,5 +40,7 @@ class Bridge(MemObject):
|
|||
delay = Param.Latency('0ns', "The latency of this bridge")
|
||||
nack_delay = Param.Latency('0ns', "The latency of this bridge")
|
||||
write_ack = Param.Bool(False, "Should this bridge ack writes")
|
||||
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
|
||||
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
|
||||
filter_ranges_a = VectorParam.AddrRange([],
|
||||
"What addresses shouldn't be passed through the side of the bridge")
|
||||
filter_ranges_b = VectorParam.AddrRange([],
|
||||
"What addresses shouldn't be passed through the side of the bridge")
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
|
||||
#include <algorithm>
|
||||
|
||||
#include "base/range_ops.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "mem/bridge.hh"
|
||||
#include "params/Bridge.hh"
|
||||
|
|
@ -44,9 +45,10 @@
|
|||
Bridge::BridgePort::BridgePort(const std::string &_name,
|
||||
Bridge *_bridge, BridgePort *_otherPort,
|
||||
int _delay, int _nack_delay, int _req_limit,
|
||||
int _resp_limit, bool fix_partial_write)
|
||||
int _resp_limit,
|
||||
std::vector<Range<Addr> > filter_ranges)
|
||||
: Port(_name), bridge(_bridge), otherPort(_otherPort),
|
||||
delay(_delay), nackDelay(_nack_delay), fixPartialWrite(fix_partial_write),
|
||||
delay(_delay), nackDelay(_nack_delay), filterRanges(filter_ranges),
|
||||
outstandingResponses(0), queuedRequests(0), inRetry(false),
|
||||
reqQueueLimit(_req_limit), respQueueLimit(_resp_limit), sendEvent(this)
|
||||
{
|
||||
|
|
@ -55,9 +57,9 @@ Bridge::BridgePort::BridgePort(const std::string &_name,
|
|||
Bridge::Bridge(Params *p)
|
||||
: MemObject(p->name),
|
||||
portA(p->name + "-portA", this, &portB, p->delay, p->nack_delay,
|
||||
p->req_size_a, p->resp_size_a, p->fix_partial_write_a),
|
||||
p->req_size_a, p->resp_size_a, p->filter_ranges_a),
|
||||
portB(p->name + "-portB", this, &portA, p->delay, p->nack_delay,
|
||||
p->req_size_b, p->resp_size_b, p->fix_partial_write_b),
|
||||
p->req_size_b, p->resp_size_b, p->filter_ranges_b),
|
||||
ackWrites(p->write_ack), _params(p)
|
||||
{
|
||||
if (ackWrites)
|
||||
|
|
@ -243,17 +245,6 @@ Bridge::BridgePort::trySend()
|
|||
|
||||
PacketPtr pkt = buf->pkt;
|
||||
|
||||
// Ugly! @todo When multilevel coherence works this will be removed
|
||||
if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite &&
|
||||
!pkt->wasNacked()) {
|
||||
PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
|
||||
Packet::Broadcast);
|
||||
funcPkt->dataStatic(pkt->getPtr<uint8_t>());
|
||||
sendFunctional(funcPkt);
|
||||
pkt->cmd = MemCmd::WriteReq;
|
||||
delete funcPkt;
|
||||
}
|
||||
|
||||
DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
|
||||
buf->origSrc, pkt->getDest(), pkt->getAddr());
|
||||
|
||||
|
|
@ -313,17 +304,6 @@ Bridge::BridgePort::recvRetry()
|
|||
Tick
|
||||
Bridge::BridgePort::recvAtomic(PacketPtr pkt)
|
||||
{
|
||||
// fix partial atomic writes... similar to the timing code that does the
|
||||
// same... will be removed once our code gets this right
|
||||
if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) {
|
||||
|
||||
PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
|
||||
Packet::Broadcast);
|
||||
funcPkt->dataStatic(pkt->getPtr<uint8_t>());
|
||||
otherPort->sendFunctional(funcPkt);
|
||||
delete funcPkt;
|
||||
pkt->cmd = MemCmd::WriteReq;
|
||||
}
|
||||
return delay + otherPort->sendAtomic(pkt);
|
||||
}
|
||||
|
||||
|
|
@ -355,6 +335,7 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp,
|
|||
bool &snoop)
|
||||
{
|
||||
otherPort->getPeerAddressRanges(resp, snoop);
|
||||
FilterRangeList(filterRanges, resp);
|
||||
// we don't allow snooping across bridges
|
||||
snoop = false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,7 +70,8 @@ class Bridge : public MemObject
|
|||
/** Min delay to respond to a nack. */
|
||||
Tick nackDelay;
|
||||
|
||||
bool fixPartialWrite;
|
||||
/** Pass ranges from one side of the bridge to the other? */
|
||||
std::vector<Range<Addr> > filterRanges;
|
||||
|
||||
class PacketBuffer : public Packet::SenderState {
|
||||
|
||||
|
|
@ -156,7 +157,8 @@ class Bridge : public MemObject
|
|||
/** Constructor for the BusPort.*/
|
||||
BridgePort(const std::string &_name, Bridge *_bridge,
|
||||
BridgePort *_otherPort, int _delay, int _nack_delay,
|
||||
int _req_limit, int _resp_limit, bool fix_partial_write);
|
||||
int _req_limit, int _resp_limit,
|
||||
std::vector<Range<Addr> > filter_ranges);
|
||||
|
||||
protected:
|
||||
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ Bus::deletePortRefs(Port *p)
|
|||
if (funcPort == bp)
|
||||
return;
|
||||
interfaces.erase(bp->getId());
|
||||
clearBusCache();
|
||||
delete bp;
|
||||
}
|
||||
|
||||
|
|
@ -176,7 +177,16 @@ Bus::recvTiming(PacketPtr pkt)
|
|||
DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
|
||||
src, pkt->getDest(), pkt->getAddr(), pkt->cmdString());
|
||||
|
||||
BusPort *src_port = (src == defaultId) ? defaultPort : interfaces[src];
|
||||
BusPort *src_port;
|
||||
if (src == defaultId)
|
||||
src_port = defaultPort;
|
||||
else {
|
||||
src_port = checkBusCache(src);
|
||||
if (src_port == NULL) {
|
||||
src_port = interfaces[src];
|
||||
updateBusCache(src, src_port);
|
||||
}
|
||||
}
|
||||
|
||||
// If the bus is busy, or other devices are in line ahead of the current
|
||||
// one, put this device on the retry list.
|
||||
|
|
@ -201,25 +211,28 @@ Bus::recvTiming(PacketPtr pkt)
|
|||
dest_port_id = findPort(pkt->getAddr());
|
||||
dest_port = (dest_port_id == defaultId) ?
|
||||
defaultPort : interfaces[dest_port_id];
|
||||
for (SnoopIter s_iter = snoopPorts.begin();
|
||||
s_iter != snoopPorts.end();
|
||||
s_iter++) {
|
||||
SnoopIter s_end = snoopPorts.end();
|
||||
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
|
||||
BusPort *p = *s_iter;
|
||||
if (p != dest_port && p != src_port) {
|
||||
#ifndef NDEBUG
|
||||
// cache is not allowed to refuse snoop
|
||||
bool success = p->sendTiming(pkt);
|
||||
bool success M5_VAR_USED = p->sendTiming(pkt);
|
||||
assert(success);
|
||||
#else
|
||||
// avoid unused variable warning
|
||||
p->sendTiming(pkt);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
} else {
|
||||
assert(dest >= 0 && dest < maxId);
|
||||
assert(dest != src); // catch infinite loops
|
||||
dest_port_id = dest;
|
||||
if (dest_port_id == defaultId)
|
||||
dest_port = defaultPort;
|
||||
else {
|
||||
dest_port = checkBusCache(dest);
|
||||
if (dest_port == NULL) {
|
||||
dest_port = interfaces[dest_port_id];
|
||||
// updateBusCache(dest_port_id, dest_port);
|
||||
}
|
||||
}
|
||||
dest_port = (dest_port_id == defaultId) ?
|
||||
defaultPort : interfaces[dest_port_id];
|
||||
}
|
||||
|
|
@ -291,15 +304,19 @@ Bus::findPort(Addr addr)
|
|||
/* An interval tree would be a better way to do this. --ali. */
|
||||
int dest_id = -1;
|
||||
|
||||
dest_id = checkPortCache(addr);
|
||||
if (dest_id == -1) {
|
||||
PortIter i = portMap.find(RangeSize(addr,1));
|
||||
if (i != portMap.end())
|
||||
dest_id = i->second;
|
||||
updatePortCache(dest_id, i->first.start, i->first.end);
|
||||
}
|
||||
|
||||
// Check if this matches the default range
|
||||
if (dest_id == -1) {
|
||||
for (AddrRangeIter iter = defaultRange.begin();
|
||||
iter != defaultRange.end(); iter++) {
|
||||
if (*iter == addr) {
|
||||
AddrRangeIter a_end = defaultRange.end();
|
||||
for (AddrRangeIter i = defaultRange.begin(); i != a_end; i++) {
|
||||
if (*i == addr) {
|
||||
DPRINTF(Bus, " found addr %#llx on default\n", addr);
|
||||
return defaultId;
|
||||
}
|
||||
|
|
@ -340,8 +357,16 @@ Bus::recvAtomic(PacketPtr pkt)
|
|||
int orig_src = pkt->getSrc();
|
||||
|
||||
int target_port_id = findPort(pkt->getAddr());
|
||||
Port *target_port = (target_port_id == defaultId) ?
|
||||
defaultPort : interfaces[target_port_id];
|
||||
BusPort *target_port;
|
||||
if (target_port_id == defaultId)
|
||||
target_port = defaultPort;
|
||||
else {
|
||||
target_port = checkBusCache(target_port_id);
|
||||
if (target_port == NULL) {
|
||||
target_port = interfaces[target_port_id];
|
||||
updateBusCache(target_port_id, target_port);
|
||||
}
|
||||
}
|
||||
|
||||
SnoopIter s_end = snoopPorts.end();
|
||||
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
|
||||
|
|
@ -406,9 +431,8 @@ Bus::recvFunctional(PacketPtr pkt)
|
|||
|
||||
assert(pkt->isRequest()); // hasn't already been satisfied
|
||||
|
||||
for (SnoopIter s_iter = snoopPorts.begin();
|
||||
s_iter != snoopPorts.end();
|
||||
s_iter++) {
|
||||
SnoopIter s_end = snoopPorts.end();
|
||||
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
|
||||
BusPort *p = *s_iter;
|
||||
if (p != port && p->getId() != src_id) {
|
||||
p->sendFunctional(pkt);
|
||||
|
|
@ -433,11 +457,16 @@ Bus::recvStatusChange(Port::Status status, int id)
|
|||
bool snoops;
|
||||
AddrRangeIter iter;
|
||||
|
||||
if (inRecvStatusChange.count(id))
|
||||
return;
|
||||
inRecvStatusChange.insert(id);
|
||||
|
||||
assert(status == Port::RangeChange &&
|
||||
"The other statuses need to be implemented.");
|
||||
|
||||
DPRINTF(BusAddrRanges, "received RangeChange from device id %d\n", id);
|
||||
|
||||
clearPortCache();
|
||||
if (id == defaultId) {
|
||||
defaultRange.clear();
|
||||
// Only try to update these ranges if the user set a default responder.
|
||||
|
|
@ -499,6 +528,7 @@ Bus::recvStatusChange(Port::Status status, int id)
|
|||
|
||||
if (id != defaultId && defaultPort)
|
||||
defaultPort->sendStatusChange(Port::RangeChange);
|
||||
inRecvStatusChange.erase(id);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -557,14 +587,14 @@ Bus::findBlockSize(int id)
|
|||
|
||||
int max_bs = -1;
|
||||
|
||||
for (PortIter portIter = portMap.begin();
|
||||
portIter != portMap.end(); portIter++) {
|
||||
int tmp_bs = interfaces[portIter->second]->peerBlockSize();
|
||||
PortIter p_end = portMap.end();
|
||||
for (PortIter p_iter = portMap.begin(); p_iter != p_end; p_iter++) {
|
||||
int tmp_bs = interfaces[p_iter->second]->peerBlockSize();
|
||||
if (tmp_bs > max_bs)
|
||||
max_bs = tmp_bs;
|
||||
}
|
||||
for (SnoopIter s_iter = snoopPorts.begin();
|
||||
s_iter != snoopPorts.end(); s_iter++) {
|
||||
SnoopIter s_end = snoopPorts.end();
|
||||
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
|
||||
int tmp_bs = (*s_iter)->peerBlockSize();
|
||||
if (tmp_bs > max_bs)
|
||||
max_bs = tmp_bs;
|
||||
|
|
|
|||
106
src/mem/bus.hh
106
src/mem/bus.hh
|
|
@ -38,6 +38,7 @@
|
|||
#define __MEM_BUS_HH__
|
||||
|
||||
#include <string>
|
||||
#include <set>
|
||||
#include <list>
|
||||
#include <inttypes.h>
|
||||
|
||||
|
|
@ -180,6 +181,60 @@ class Bus : public MemObject
|
|||
*/
|
||||
int findPort(Addr addr);
|
||||
|
||||
// Cache for the findPort function storing recently used ports from portMap
|
||||
struct PortCache {
|
||||
bool valid;
|
||||
int id;
|
||||
Addr start;
|
||||
Addr end;
|
||||
};
|
||||
|
||||
PortCache portCache[3];
|
||||
|
||||
// Checks the cache and returns the id of the port that has the requested
|
||||
// address within its range
|
||||
inline int checkPortCache(Addr addr) {
|
||||
if (portCache[0].valid && addr >= portCache[0].start &&
|
||||
addr < portCache[0].end) {
|
||||
return portCache[0].id;
|
||||
}
|
||||
if (portCache[1].valid && addr >= portCache[1].start &&
|
||||
addr < portCache[1].end) {
|
||||
return portCache[1].id;
|
||||
}
|
||||
if (portCache[2].valid && addr >= portCache[2].start &&
|
||||
addr < portCache[2].end) {
|
||||
return portCache[2].id;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Clears the earliest entry of the cache and inserts a new port entry
|
||||
inline void updatePortCache(short id, Addr start, Addr end) {
|
||||
portCache[2].valid = portCache[1].valid;
|
||||
portCache[2].id = portCache[1].id;
|
||||
portCache[2].start = portCache[1].start;
|
||||
portCache[2].end = portCache[1].end;
|
||||
|
||||
portCache[1].valid = portCache[0].valid;
|
||||
portCache[1].id = portCache[0].id;
|
||||
portCache[1].start = portCache[0].start;
|
||||
portCache[1].end = portCache[0].end;
|
||||
|
||||
portCache[0].valid = true;
|
||||
portCache[0].id = id;
|
||||
portCache[0].start = start;
|
||||
portCache[0].end = end;
|
||||
}
|
||||
|
||||
// Clears the cache. Needs to be called in constructor.
|
||||
inline void clearPortCache() {
|
||||
portCache[2].valid = false;
|
||||
portCache[1].valid = false;
|
||||
portCache[0].valid = false;
|
||||
}
|
||||
|
||||
/** Process address range request.
|
||||
* @param resp addresses that we can respond to
|
||||
* @param snoop addresses that we would like to snoop
|
||||
|
|
@ -199,6 +254,7 @@ class Bus : public MemObject
|
|||
BusFreeEvent busIdle;
|
||||
|
||||
bool inRetry;
|
||||
std::set<int> inRecvStatusChange;
|
||||
|
||||
/** max number of bus ids we've handed out so far */
|
||||
short maxId;
|
||||
|
|
@ -246,6 +302,54 @@ class Bus : public MemObject
|
|||
int cachedBlockSize;
|
||||
bool cachedBlockSizeValid;
|
||||
|
||||
// Cache for the peer port interfaces
|
||||
struct BusCache {
|
||||
bool valid;
|
||||
short id;
|
||||
BusPort *port;
|
||||
};
|
||||
|
||||
BusCache busCache[3];
|
||||
|
||||
// Checks the peer port interfaces cache for the port id and returns
|
||||
// a pointer to the matching port
|
||||
inline BusPort* checkBusCache(short id) {
|
||||
if (busCache[0].valid && id == busCache[0].id) {
|
||||
return busCache[0].port;
|
||||
}
|
||||
if (busCache[1].valid && id == busCache[1].id) {
|
||||
return busCache[1].port;
|
||||
}
|
||||
if (busCache[2].valid && id == busCache[2].id) {
|
||||
return busCache[2].port;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
// Replaces the earliest entry in the cache with a new entry
|
||||
inline void updateBusCache(short id, BusPort *port) {
|
||||
busCache[2].valid = busCache[1].valid;
|
||||
busCache[2].id = busCache[1].id;
|
||||
busCache[2].port = busCache[1].port;
|
||||
|
||||
busCache[1].valid = busCache[0].valid;
|
||||
busCache[1].id = busCache[0].id;
|
||||
busCache[1].port = busCache[0].port;
|
||||
|
||||
busCache[0].valid = true;
|
||||
busCache[0].id = id;
|
||||
busCache[0].port = port;
|
||||
}
|
||||
|
||||
// Invalidates the cache. Needs to be called in constructor.
|
||||
inline void clearBusCache() {
|
||||
busCache[2].valid = false;
|
||||
busCache[1].valid = false;
|
||||
busCache[0].valid = false;
|
||||
}
|
||||
|
||||
|
||||
public:
|
||||
|
||||
/** A function used to return the port associated with this bus object. */
|
||||
|
|
@ -270,6 +374,8 @@ class Bus : public MemObject
|
|||
fatal("Bus width must be positive\n");
|
||||
if (clock <= 0)
|
||||
fatal("Bus clock period must be positive\n");
|
||||
clearBusCache();
|
||||
clearPortCache();
|
||||
}
|
||||
|
||||
};
|
||||
|
|
|
|||
4
src/mem/cache/BaseCache.py
vendored
4
src/mem/cache/BaseCache.py
vendored
|
|
@ -81,4 +81,8 @@ class BaseCache(MemObject):
|
|||
"Only prefetch on data not on instruction accesses")
|
||||
cpu_side = Port("Port on side closer to CPU")
|
||||
mem_side = Port("Port on side closer to MEM")
|
||||
cpu_side_filter_ranges = VectorParam.AddrRange([],
|
||||
"What addresses shouldn't be passed through the side of the bridge")
|
||||
mem_side_filter_ranges = VectorParam.AddrRange([],
|
||||
"What addresses shouldn't be passed through the side of the bridge")
|
||||
addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
|
||||
|
|
|
|||
5
src/mem/cache/base_cache.cc
vendored
5
src/mem/cache/base_cache.cc
vendored
|
|
@ -40,9 +40,10 @@
|
|||
|
||||
using namespace std;
|
||||
|
||||
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
|
||||
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
|
||||
std::vector<Range<Addr> > filter_ranges)
|
||||
: SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
|
||||
blocked(false), mustSendRetry(false)
|
||||
blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
|||
16
src/mem/cache/base_cache.hh
vendored
16
src/mem/cache/base_cache.hh
vendored
|
|
@ -98,7 +98,8 @@ class BaseCache : public MemObject
|
|||
BaseCache *cache;
|
||||
|
||||
protected:
|
||||
CachePort(const std::string &_name, BaseCache *_cache);
|
||||
CachePort(const std::string &_name, BaseCache *_cache,
|
||||
std::vector<Range<Addr> > filter_ranges);
|
||||
|
||||
virtual void recvStatusChange(Status status);
|
||||
|
||||
|
|
@ -124,6 +125,9 @@ class BaseCache : public MemObject
|
|||
|
||||
bool mustSendRetry;
|
||||
|
||||
/** filter ranges */
|
||||
std::vector<Range<Addr> > filterRanges;
|
||||
|
||||
void requestBus(RequestCause cause, Tick time)
|
||||
{
|
||||
DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
|
||||
|
|
@ -367,15 +371,21 @@ class BaseCache : public MemObject
|
|||
*/
|
||||
Counter maxMisses;
|
||||
|
||||
std::vector<Range<Addr> > cpuSideFilterRanges;
|
||||
std::vector<Range<Addr> > memSideFilterRanges;
|
||||
/**
|
||||
* Construct an instance of this parameter class.
|
||||
*/
|
||||
Params(int _hitLatency, int _blkSize,
|
||||
int _numMSHRs, int _numTargets, int _numWriteBuffers,
|
||||
Counter _maxMisses)
|
||||
Counter _maxMisses,
|
||||
std::vector<Range<Addr> > cpu_side_filter_ranges,
|
||||
std::vector<Range<Addr> > mem_side_filter_ranges)
|
||||
: hitLatency(_hitLatency), blkSize(_blkSize),
|
||||
numMSHRs(_numMSHRs), numTargets(_numTargets),
|
||||
numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses)
|
||||
numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses),
|
||||
cpuSideFilterRanges(cpu_side_filter_ranges),
|
||||
memSideFilterRanges(mem_side_filter_ranges)
|
||||
{
|
||||
}
|
||||
};
|
||||
|
|
|
|||
6
src/mem/cache/cache.hh
vendored
6
src/mem/cache/cache.hh
vendored
|
|
@ -72,7 +72,8 @@ class Cache : public BaseCache
|
|||
{
|
||||
public:
|
||||
CpuSidePort(const std::string &_name,
|
||||
Cache<TagStore> *_cache);
|
||||
Cache<TagStore> *_cache,
|
||||
std::vector<Range<Addr> > filterRanges);
|
||||
|
||||
// BaseCache::CachePort just has a BaseCache *; this function
|
||||
// lets us get back the type info we lost when we stored the
|
||||
|
|
@ -95,7 +96,8 @@ class Cache : public BaseCache
|
|||
{
|
||||
public:
|
||||
MemSidePort(const std::string &_name,
|
||||
Cache<TagStore> *_cache);
|
||||
Cache<TagStore> *_cache,
|
||||
std::vector<Range<Addr> > filterRanges);
|
||||
|
||||
// BaseCache::CachePort just has a BaseCache *; this function
|
||||
// lets us get back the type info we lost when we stored the
|
||||
|
|
|
|||
3
src/mem/cache/cache_builder.cc
vendored
3
src/mem/cache/cache_builder.cc
vendored
|
|
@ -241,7 +241,8 @@ BaseCacheParams::create()
|
|||
// Build BaseCache param object
|
||||
BaseCache::Params base_params(latency, block_size,
|
||||
mshrs, tgts_per_mshr, write_buffers,
|
||||
max_miss_count);
|
||||
max_miss_count, cpu_side_filter_ranges,
|
||||
mem_side_filter_ranges);
|
||||
|
||||
//Warnings about prefetcher policy
|
||||
if (prefetch_policy == Enums::none) {
|
||||
|
|
|
|||
23
src/mem/cache/cache_impl.hh
vendored
23
src/mem/cache/cache_impl.hh
vendored
|
|
@ -39,6 +39,7 @@
|
|||
|
||||
#include "sim/host.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/range_ops.hh"
|
||||
|
||||
#include "mem/cache/cache.hh"
|
||||
#include "mem/cache/cache_blk.hh"
|
||||
|
|
@ -61,8 +62,10 @@ Cache<TagStore>::Cache(const std::string &_name,
|
|||
tempBlock = new BlkType();
|
||||
tempBlock->data = new uint8_t[blkSize];
|
||||
|
||||
cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this);
|
||||
memSidePort = new MemSidePort(_name + "-mem_side_port", this);
|
||||
cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this,
|
||||
params.baseParams.cpuSideFilterRanges);
|
||||
memSidePort = new MemSidePort(_name + "-mem_side_port", this,
|
||||
params.baseParams.memSideFilterRanges);
|
||||
cpuSidePort->setOtherPort(memSidePort);
|
||||
memSidePort->setOtherPort(cpuSidePort);
|
||||
|
||||
|
|
@ -88,7 +91,8 @@ Cache<TagStore>::getPort(const std::string &if_name, int idx)
|
|||
} else if (if_name == "mem_side") {
|
||||
return memSidePort;
|
||||
} else if (if_name == "functional") {
|
||||
return new CpuSidePort(name() + "-cpu_side_funcport", this);
|
||||
return new CpuSidePort(name() + "-cpu_side_funcport", this,
|
||||
std::vector<Range<Addr> >());
|
||||
} else {
|
||||
panic("Port name %s unrecognized\n", if_name);
|
||||
}
|
||||
|
|
@ -1221,6 +1225,7 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
|
|||
// CPU side port doesn't snoop; it's a target only.
|
||||
bool dummy;
|
||||
otherPort->getPeerAddressRanges(resp, dummy);
|
||||
FilterRangeList(filterRanges, resp);
|
||||
snoop = false;
|
||||
}
|
||||
|
||||
|
|
@ -1262,8 +1267,9 @@ Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
|
|||
template<class TagStore>
|
||||
Cache<TagStore>::
|
||||
CpuSidePort::CpuSidePort(const std::string &_name,
|
||||
Cache<TagStore> *_cache)
|
||||
: BaseCache::CachePort(_name, _cache)
|
||||
Cache<TagStore> *_cache, std::vector<Range<Addr> >
|
||||
filterRanges)
|
||||
: BaseCache::CachePort(_name, _cache, filterRanges)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -1279,6 +1285,8 @@ Cache<TagStore>::MemSidePort::
|
|||
getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
|
||||
{
|
||||
otherPort->getPeerAddressRanges(resp, snoop);
|
||||
FilterRangeList(filterRanges, resp);
|
||||
|
||||
// Memory-side port always snoops, so unconditionally set flag for
|
||||
// caller.
|
||||
snoop = true;
|
||||
|
|
@ -1416,8 +1424,9 @@ Cache<TagStore>::MemSidePort::processSendEvent()
|
|||
|
||||
template<class TagStore>
|
||||
Cache<TagStore>::
|
||||
MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache)
|
||||
: BaseCache::CachePort(_name, _cache)
|
||||
MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
|
||||
std::vector<Range<Addr> > filterRanges)
|
||||
: BaseCache::CachePort(_name, _cache, filterRanges)
|
||||
{
|
||||
// override default send event from SimpleTimingPort
|
||||
delete sendEvent;
|
||||
|
|
|
|||
|
|
@ -52,10 +52,28 @@ class L2(BaseCache):
|
|||
tgts_per_mshr = 16
|
||||
write_buffers = 8
|
||||
|
||||
# ---------------------
|
||||
# I/O Cache
|
||||
# ---------------------
|
||||
class IOCache(BaseCache):
|
||||
assoc = 8
|
||||
block_size = 64
|
||||
latency = '50ns'
|
||||
mshrs = 20
|
||||
size = '1kB'
|
||||
tgts_per_mshr = 12
|
||||
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
|
||||
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
|
||||
|
||||
#cpu
|
||||
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('atomic')
|
||||
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
|
||||
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
|
||||
system.iocache = IOCache()
|
||||
system.iocache.cpu_side = system.iobus.port
|
||||
system.iocache.mem_side = system.membus.port
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
|
|
|
|||
|
|
@ -52,10 +52,28 @@ class L2(BaseCache):
|
|||
tgts_per_mshr = 16
|
||||
write_buffers = 8
|
||||
|
||||
# ---------------------
|
||||
# I/O Cache
|
||||
# ---------------------
|
||||
class IOCache(BaseCache):
|
||||
assoc = 8
|
||||
block_size = 64
|
||||
latency = '50ns'
|
||||
mshrs = 20
|
||||
size = '1kB'
|
||||
tgts_per_mshr = 12
|
||||
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
|
||||
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
|
||||
|
||||
#cpu
|
||||
cpu = AtomicSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('atomic')
|
||||
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
|
||||
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
|
||||
system.iocache = IOCache()
|
||||
system.iocache.cpu_side = system.iobus.port
|
||||
system.iocache.mem_side = system.membus.port
|
||||
|
||||
system.cpu = cpu
|
||||
#create the l1/l2 bus
|
||||
|
|
|
|||
|
|
@ -52,10 +52,28 @@ class L2(BaseCache):
|
|||
tgts_per_mshr = 16
|
||||
write_buffers = 8
|
||||
|
||||
# ---------------------
|
||||
# I/O Cache
|
||||
# ---------------------
|
||||
class IOCache(BaseCache):
|
||||
assoc = 8
|
||||
block_size = 64
|
||||
latency = '50ns'
|
||||
mshrs = 20
|
||||
size = '1kB'
|
||||
tgts_per_mshr = 12
|
||||
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
|
||||
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
|
||||
|
||||
#cpu
|
||||
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('timing')
|
||||
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
|
||||
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
|
||||
system.iocache = IOCache()
|
||||
system.iocache.cpu_side = system.iobus.port
|
||||
system.iocache.mem_side = system.membus.port
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
|
|
|
|||
|
|
@ -53,6 +53,19 @@ class L2(BaseCache):
|
|||
tgts_per_mshr = 16
|
||||
write_buffers = 8
|
||||
|
||||
# ---------------------
|
||||
# I/O Cache
|
||||
# ---------------------
|
||||
class IOCache(BaseCache):
|
||||
assoc = 8
|
||||
block_size = 64
|
||||
latency = '50ns'
|
||||
mshrs = 20
|
||||
size = '1kB'
|
||||
tgts_per_mshr = 12
|
||||
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
|
||||
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
|
||||
|
||||
#cpu
|
||||
cpu = TimingSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
|
|
@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
|
|||
system.cpu = cpu
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = Bus()
|
||||
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
|
||||
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
|
||||
system.iocache = IOCache()
|
||||
system.iocache.cpu_side = system.iobus.port
|
||||
system.iocache.mem_side = system.membus.port
|
||||
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2(size='4MB', assoc=8)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
|
|
@ -22,8 +22,8 @@ system_type=34
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
fix_partial_write_a=false
|
||||
fix_partial_write_b=true
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:8589934591
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
|
|
@ -65,10 +65,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -103,10 +105,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -171,10 +175,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -209,10 +215,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -295,17 +303,55 @@ clock=1000
|
|||
responder_set=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=549755813888:18446744073709551615
|
||||
hash_delay=1
|
||||
latency=50000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=0:18446744073709551615
|
||||
mshrs=20
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
split=false
|
||||
split_size=0
|
||||
subblock_size=0
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=10000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=92
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -329,7 +375,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[2]
|
||||
mem_side=system.membus.port[3]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -340,7 +386,7 @@ clock=1000
|
|||
responder_set=false
|
||||
width=64
|
||||
default=system.membus.responder.pio
|
||||
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
|
||||
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.responder]
|
||||
type=IsaFake
|
||||
|
|
@ -474,8 +520,8 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[28]
|
||||
dma=system.iobus.port[29]
|
||||
config=system.iobus.port[29]
|
||||
dma=system.iobus.port[30]
|
||||
pio=system.iobus.port[27]
|
||||
|
||||
[system.tsunami.ethernet.configdata]
|
||||
|
|
@ -840,8 +886,8 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
config=system.iobus.port[31]
|
||||
dma=system.iobus.port[32]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.tsunami.ide.configdata]
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
|
|||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x8410-0x8417,0x8422 on irq 31
|
||||
hda: max request size: 128KiB
|
||||
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
|
||||
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
|
||||
hda: cache flushes not supported
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
|
|
@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
|
|||
All bugs added by David S. Miller <davem@redhat.com>
|
||||
VFS: Mounted root (ext2 filesystem) readonly.
|
||||
Freeing unused kernel memory: 224k freed
|
||||
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
|
||||
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
|
||||
mounting filesystems...
|
||||
EXT2-fs warning: checktime reached, running e2fsck is recommended
|
||||
loading script...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1258571 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 256444 # Number of bytes of host memory used
|
||||
host_seconds 50.16 # Real time elapsed on the host
|
||||
host_tick_rate 37289409683 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2271343 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 326380 # Number of bytes of host memory used
|
||||
host_seconds 27.79 # Real time elapsed on the host
|
||||
host_tick_rate 67296173797 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 63125943 # Number of instructions simulated
|
||||
sim_seconds 1.870335 # Number of seconds simulated
|
||||
|
|
@ -471,6 +471,64 @@ system.disk2.dma_read_txs 0 # Nu
|
|||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_misses 175 # number of ReadReq misses
|
||||
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
||||
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
|
||||
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.iocache.demand_misses 41727 # number of demand (read+write) misses
|
||||
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
|
||||
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.iocache.overall_hits 0 # number of overall hits
|
||||
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.iocache.overall_misses 41727 # number of overall misses
|
||||
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.iocache.replacements 41695 # number of replacements
|
||||
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
|
||||
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.iocache.tagsinuse 0.435433 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.writebacks 41520 # number of writebacks
|
||||
system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Listening for system connection on port 3457
|
||||
Listening for system connection on port 3456
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: 97861500: Trying to launch CPU number 1!
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2007 04:02:11
|
||||
M5 started Fri Aug 3 04:22:43 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Aug 10 2007 16:03:34
|
||||
M5 started Fri Aug 10 16:04:07 2007
|
||||
M5 executing on zeep
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1870335101500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
|
|
@ -22,8 +22,8 @@ system_type=34
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
fix_partial_write_a=false
|
||||
fix_partial_write_b=true
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:8589934591
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
|
|
@ -65,10 +65,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -103,10 +105,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -189,17 +193,55 @@ clock=1000
|
|||
responder_set=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=549755813888:18446744073709551615
|
||||
hash_delay=1
|
||||
latency=50000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=0:18446744073709551615
|
||||
mshrs=20
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
split=false
|
||||
split_size=0
|
||||
subblock_size=0
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=10000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=92
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -223,7 +265,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[2]
|
||||
mem_side=system.membus.port[3]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -234,7 +276,7 @@ clock=1000
|
|||
responder_set=false
|
||||
width=64
|
||||
default=system.membus.responder.pio
|
||||
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
|
||||
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.responder]
|
||||
type=IsaFake
|
||||
|
|
@ -368,8 +410,8 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[28]
|
||||
dma=system.iobus.port[29]
|
||||
config=system.iobus.port[29]
|
||||
dma=system.iobus.port[30]
|
||||
pio=system.iobus.port[27]
|
||||
|
||||
[system.tsunami.ethernet.configdata]
|
||||
|
|
@ -734,8 +776,8 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
config=system.iobus.port[31]
|
||||
dma=system.iobus.port[32]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.tsunami.ide.configdata]
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x8410-0x8417,0x8422 on irq 31
|
||||
hda: max request size: 128KiB
|
||||
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
|
||||
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
|
||||
hda: cache flushes not supported
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
|
|
@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
All bugs added by David S. Miller <davem@redhat.com>
|
||||
VFS: Mounted root (ext2 filesystem) readonly.
|
||||
Freeing unused kernel memory: 224k freed
|
||||
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
|
||||
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
|
||||
mounting filesystems...
|
||||
EXT2-fs warning: checktime reached, running e2fsck is recommended
|
||||
loading script...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1294756 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 255900 # Number of bytes of host memory used
|
||||
host_seconds 46.35 # Real time elapsed on the host
|
||||
host_tick_rate 39449403667 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2322212 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 325356 # Number of bytes of host memory used
|
||||
host_seconds 25.84 # Real time elapsed on the host
|
||||
host_tick_rate 70754225205 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 60007317 # Number of instructions simulated
|
||||
sim_seconds 1.828355 # Number of seconds simulated
|
||||
|
|
@ -249,6 +249,64 @@ system.disk2.dma_read_txs 0 # Nu
|
|||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_misses 174 # number of ReadReq misses
|
||||
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
||||
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.demand_accesses 41726 # number of demand (read+write) accesses
|
||||
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.iocache.demand_misses 41726 # number of demand (read+write) misses
|
||||
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_accesses 41726 # number of overall (read+write) accesses
|
||||
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.iocache.overall_hits 0 # number of overall hits
|
||||
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.iocache.overall_misses 41726 # number of overall misses
|
||||
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.iocache.replacements 41686 # number of replacements
|
||||
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.iocache.tagsinuse 1.226223 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.writebacks 41512 # number of writebacks
|
||||
system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
Listening for system connection on port 3457
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
Listening for system connection on port 3456
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2007 04:02:11
|
||||
M5 started Fri Aug 3 04:21:55 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Aug 10 2007 16:03:34
|
||||
M5 started Fri Aug 10 16:03:39 2007
|
||||
M5 executing on zeep
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1828355476000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
|
|
@ -22,8 +22,8 @@ system_type=34
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
fix_partial_write_a=false
|
||||
fix_partial_write_b=true
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:8589934591
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
|
|
@ -63,10 +63,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -101,10 +103,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -167,10 +171,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -205,10 +211,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -291,17 +299,55 @@ clock=1000
|
|||
responder_set=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=549755813888:18446744073709551615
|
||||
hash_delay=1
|
||||
latency=50000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=0:18446744073709551615
|
||||
mshrs=20
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
split=false
|
||||
split_size=0
|
||||
subblock_size=0
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=10000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=92
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -325,7 +371,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[2]
|
||||
mem_side=system.membus.port[3]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -336,7 +382,7 @@ clock=1000
|
|||
responder_set=false
|
||||
width=64
|
||||
default=system.membus.responder.pio
|
||||
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
|
||||
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.responder]
|
||||
type=IsaFake
|
||||
|
|
@ -470,8 +516,8 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[28]
|
||||
dma=system.iobus.port[29]
|
||||
config=system.iobus.port[29]
|
||||
dma=system.iobus.port[30]
|
||||
pio=system.iobus.port[27]
|
||||
|
||||
[system.tsunami.ethernet.configdata]
|
||||
|
|
@ -836,8 +882,8 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
config=system.iobus.port[31]
|
||||
dma=system.iobus.port[32]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.tsunami.ide.configdata]
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
unix_boot_mem ends at FFFFFC0000078000
|
||||
k_argc = 0
|
||||
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
|
||||
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
|
||||
CallbackFixup 0 18000, t7=FFFFFC000070C000
|
||||
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
|
||||
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
|
||||
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
|
||||
Major Options: SMP LEGACY_START VERBOSE_MCHECK
|
||||
|
|
@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
|
|||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x8410-0x8417,0x8422 on irq 31
|
||||
hda: max request size: 128KiB
|
||||
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
|
||||
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
|
||||
hda: cache flushes not supported
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
|
|
@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
|
|||
All bugs added by David S. Miller <davem@redhat.com>
|
||||
VFS: Mounted root (ext2 filesystem) readonly.
|
||||
Freeing unused kernel memory: 224k freed
|
||||
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
|
||||
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
|
||||
mounting filesystems...
|
||||
EXT2-fs warning: checktime reached, running e2fsck is recommended
|
||||
loading script...
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,5 @@
|
|||
Listening for system connection on port 3457
|
||||
Listening for system connection on port 3456
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: 427086000: Trying to launch CPU number 1!
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2007 04:02:11
|
||||
M5 started Fri Aug 3 04:25:10 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Aug 10 2007 16:03:34
|
||||
M5 started Fri Aug 10 16:05:34 2007
|
||||
M5 executing on zeep
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1951367346000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1950343222000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/dist/m5/system/binaries/console
|
||||
|
|
@ -22,8 +22,8 @@ system_type=34
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
fix_partial_write_a=false
|
||||
fix_partial_write_b=true
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:8589934591
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
|
|
@ -63,10 +63,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -101,10 +103,12 @@ type=BaseCache
|
|||
addr_range=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=1000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=4
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -187,17 +191,55 @@ clock=1000
|
|||
responder_set=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=549755813888:18446744073709551615
|
||||
hash_delay=1
|
||||
latency=50000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=0:18446744073709551615
|
||||
mshrs=20
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
split=false
|
||||
split_size=0
|
||||
subblock_size=0
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
cpu_side_filter_ranges=
|
||||
hash_delay=1
|
||||
latency=10000
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mem_side_filter_ranges=
|
||||
mshrs=92
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
|
|
@ -221,7 +263,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[2]
|
||||
mem_side=system.membus.port[3]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -232,7 +274,7 @@ clock=1000
|
|||
responder_set=false
|
||||
width=64
|
||||
default=system.membus.responder.pio
|
||||
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
|
||||
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.responder]
|
||||
type=IsaFake
|
||||
|
|
@ -366,8 +408,8 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[28]
|
||||
dma=system.iobus.port[29]
|
||||
config=system.iobus.port[29]
|
||||
dma=system.iobus.port[30]
|
||||
pio=system.iobus.port[27]
|
||||
|
||||
[system.tsunami.ethernet.configdata]
|
||||
|
|
@ -732,8 +774,8 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
config=system.iobus.port[31]
|
||||
dma=system.iobus.port[32]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.tsunami.ide.configdata]
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x8410-0x8417,0x8422 on irq 31
|
||||
hda: max request size: 128KiB
|
||||
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
|
||||
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
|
||||
hda: cache flushes not supported
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
|
|
@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
All bugs added by David S. Miller <davem@redhat.com>
|
||||
VFS: Mounted root (ext2 filesystem) readonly.
|
||||
Freeing unused kernel memory: 224k freed
|
||||
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
|
||||
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
|
||||
mounting filesystems...
|
||||
EXT2-fs warning: checktime reached, running e2fsck is recommended
|
||||
loading script...
|
||||
|
|
|
|||
|
|
@ -1,92 +1,92 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 631972 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 219140 # Number of bytes of host memory used
|
||||
host_seconds 95.00 # Real time elapsed on the host
|
||||
host_tick_rate 20109299069 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1028480 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 285368 # Number of bytes of host memory used
|
||||
host_seconds 58.37 # Real time elapsed on the host
|
||||
host_tick_rate 32711130426 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 60034774 # Number of instructions simulated
|
||||
sim_seconds 1.910310 # Number of seconds simulated
|
||||
sim_ticks 1910309711000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 200211 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 182851 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 242357000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.086709 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 17360 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224997000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086709 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 17360 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 9525872 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719 # average ReadReq mshr miss latency
|
||||
sim_insts 60031203 # Number of instructions simulated
|
||||
sim_seconds 1.909320 # Number of seconds simulated
|
||||
sim_ticks 1909320028000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 200196 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13961.565057 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12961.565057 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 182842 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 242289000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.086685 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 17354 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224935000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086685 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 17354 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 9525051 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13247.769109 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12247.742435 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_hits 7801048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 22837453500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.181067 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1724824 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 21112583500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.181067 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1724824 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_hits 7800516 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 22846241500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.181053 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1724535 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 21121660500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.181053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1724535 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses 199189 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_accesses 199174 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency 14002.263422 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13002.263422 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_hits 169131 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_miss_latency 420836000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_rate 0.150902 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_misses 30058 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency 390778000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150902 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses 30058 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6151132 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_miss_latency 420670000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_rate 0.150838 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_misses 30043 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency 390627000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150838 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses 30043 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6150630 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 14004.147760 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13004.147760 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_hits 5750801 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5605013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.065082 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 400331 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5204682500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065082 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 400331 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164414500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_hits 5750414 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5604684000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.065069 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 400216 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5204468000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065069 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 400216 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164291500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 6.854770 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.855501 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 15677004 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 13383.714129 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 13551849 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 28442467000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.135559 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2125155 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_accesses 15675681 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 13390.239845 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12390.218195 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 13550930 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 28450925500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.135544 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2124751 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 26317266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.135559 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2125155 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 26326128500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.135544 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2124751 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 15677004 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 13383.714129 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 15675681 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 13390.239845 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12390.218195 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 13551849 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 28442467000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.135559 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2125155 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 13550930 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 28450925500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.135544 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2124751 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 26317266000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.135559 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2125155 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 1995240500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 26326128500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.135544 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2124751 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 1995117500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
|
|
@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 2046194 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2046706 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2045831 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2046343 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 511.987834 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14029698 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 511.987794 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14028706 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58297000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 429991 # number of writebacks
|
||||
system.cpu.dcache.writebacks 429859 # number of writebacks
|
||||
system.cpu.dtb.accesses 1020787 # DTB accesses
|
||||
system.cpu.dtb.acv 367 # DTB access violations
|
||||
system.cpu.dtb.hits 16056951 # DTB hits
|
||||
system.cpu.dtb.hits 16055629 # DTB hits
|
||||
system.cpu.dtb.misses 11471 # DTB misses
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 9706492 # DTB read hits
|
||||
system.cpu.dtb.read_hits 9705676 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 6350459 # DTB write hits
|
||||
system.cpu.dtb.write_hits 6349953 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 60034775 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 12033.060657 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 59106935 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 11164755000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.015455 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 927840 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10236233500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.015455 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 927840 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 60031204 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 12033.101057 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.368005 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 59103575 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 11162253500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.015452 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 927629 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10233944500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.015452 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 927629 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 63.714789 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 63.725661 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 60034775 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 12033.060657 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 59106935 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 11164755000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.015455 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 927840 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_accesses 60031204 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 12033.101057 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11032.368005 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 59103575 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 11162253500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.015452 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 927629 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10236233500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.015455 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 927840 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_miss_latency 10233944500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.015452 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 927629 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 60034775 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 12033.060657 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 60031204 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 12033.101057 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11032.368005 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 59106935 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 11164755000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.015455 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 927840 # number of overall misses
|
||||
system.cpu.icache.overall_hits 59103575 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 11162253500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.015452 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 927629 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10236233500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.015455 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 927840 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_miss_latency 10233944500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.015452 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 927629 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 927169 # number of replacements
|
||||
system.cpu.icache.sampled_refs 927680 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 926958 # number of replacements
|
||||
system.cpu.icache.sampled_refs 927469 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 508.749374 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59106935 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 508.747859 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59103575 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 35000367000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0.939637 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 4978395 # ITB accesses
|
||||
system.cpu.idle_fraction 0.939605 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 4978081 # ITB accesses
|
||||
system.cpu.itb.acv 184 # ITB acv
|
||||
system.cpu.itb.hits 4973389 # ITB hits
|
||||
system.cpu.itb.hits 4973075 # ITB hits
|
||||
system.cpu.itb.misses 5006 # ITB misses
|
||||
system.cpu.kern.callpal 192813 # number of callpals executed
|
||||
system.cpu.kern.callpal 192799 # number of callpals executed
|
||||
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
|
||||
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpctx 4172 2.16% 2.17% # number of callpals executed
|
||||
system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpipl 175877 91.22% 93.42% # number of callpals executed
|
||||
system.cpu.kern.callpal_rdps 6828 3.54% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpipl 175869 91.22% 93.42% # number of callpals executed
|
||||
system.cpu.kern.callpal_rdps 6827 3.54% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed
|
||||
system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
|
||||
system.cpu.kern.callpal_rti 5152 2.67% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal_rti 5151 2.67% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.hwrei 211901 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed
|
||||
system.cpu.kern.ipl_count 183088 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_0 74875 40.90% 40.90% # number of times we switched to this ipl
|
||||
system.cpu.kern.inst.hwrei 211886 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.quiesce 6177 # number of quiesce instructions executed
|
||||
system.cpu.kern.ipl_count 183078 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_0 74873 40.90% 40.90% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_22 1927 1.05% 42.02% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_31 106155 57.98% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good 149074 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_0 73508 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_count_22 1926 1.05% 42.02% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_31 106148 57.98% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good 149069 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_0 73506 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_22 1927 1.29% 50.69% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_31 73508 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks 1910308997000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_0 1853401678500 97.02% 97.02% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_21 78202500 0.00% 97.03% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_22 538133000 0.03% 97.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_31 56290983000 2.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used_0 0.981743 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_good_22 1926 1.29% 50.69% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_31 73506 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks 1909319316000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_0 1852420057000 97.02% 97.02% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_21 77949500 0.00% 97.02% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_22 537776500 0.03% 97.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_31 56283533000 2.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used_0 0.981742 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used_31 0.692459 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.mode_good_kernel 1908
|
||||
system.cpu.kern.mode_good_user 1738
|
||||
system.cpu.kern.mode_good_idle 170
|
||||
system.cpu.kern.mode_switch_kernel 5896 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_idle 2098 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_good 1.404639 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_kernel 0.323609 # fraction of useful protection mode switches
|
||||
system.cpu.kern.ipl_used_31 0.692486 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.mode_good_kernel 1907
|
||||
system.cpu.kern.mode_good_user 1739
|
||||
system.cpu.kern.mode_good_idle 168
|
||||
system.cpu.kern.mode_switch_kernel 5895 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_user 1739 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_idle 2094 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_good 1.403724 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_kernel 0.323494 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_idle 0.081030 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks_kernel 43115749000 2.26% 2.26% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_user 4716926000 0.25% 2.50% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_idle 1862476320000 97.50% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
||||
system.cpu.kern.mode_switch_good_idle 0.080229 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks_kernel 43141321000 2.26% 2.26% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_user 4716637000 0.25% 2.51% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_idle 1861461356000 97.49% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4173 # number of times the context was actually changed
|
||||
system.cpu.kern.syscall 326 # number of syscalls executed
|
||||
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
|
||||
|
|
@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu
|
|||
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
|
||||
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
|
||||
system.cpu.not_idle_fraction 0.060363 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1910309711000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 60034774 # Number of instructions executed
|
||||
system.cpu.num_refs 16305091 # Number of memory references
|
||||
system.cpu.not_idle_fraction 0.060395 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1909320028000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 60031203 # Number of instructions executed
|
||||
system.cpu.num_refs 16303737 # Number of memory references
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -283,78 +283,148 @@ system.disk2.dma_read_txs 0 # Nu
|
|||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.l2c.ReadExReq_accesses 304522 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_avg_miss_latency 12000.719160 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_miss_latency 3654483000 # number of ReadExReq miss cycles
|
||||
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_avg_miss_latency 61832.358382 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency 60832.358382 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_miss_latency 10696998 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_misses 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_mshr_miss_latency 10523998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_avg_miss_latency 55508.947969 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency 54508.947969 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_miss_latency 2306507806 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_mshr_miss_latency 2264955806 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.avg_blocked_cycles_no_mshrs 4134.747706 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.blocked_no_mshrs 10464 # number of cycles access was blocked
|
||||
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_mshrs 43266000 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_avg_miss_latency 55535.166064 # average overall miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency 54535.166064 # average overall mshr miss latency
|
||||
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_miss_latency 2317204804 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.iocache.demand_misses 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.iocache.demand_mshr_miss_latency 2275479804 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_avg_miss_latency 55535.166064 # average overall miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency 54535.166064 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.iocache.overall_hits 0 # number of overall hits
|
||||
system.iocache.overall_miss_latency 2317204804 # number of overall miss cycles
|
||||
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.iocache.overall_misses 41725 # number of overall misses
|
||||
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.iocache.overall_mshr_miss_latency 2275479804 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.iocache.tagsinuse 1.326249 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1746583798000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.writebacks 41512 # number of writebacks
|
||||
system.l2c.ReadExReq_accesses 304456 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_avg_miss_latency 12004.125391 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 11004.125391 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_miss_latency 3654728000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses 304522 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 3349961000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_misses 304456 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 3350272000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_misses 304522 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses 2670005 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency 12000.233269 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadExReq_mshr_misses 304456 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses 2669499 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency 12011.481535 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 11011.481535 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_hits 1568273 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 13221041000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate 0.412633 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses 1101732 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 12119309000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate 0.412633 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 1101732 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_hits 1567817 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 13232833000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate 0.412692 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses 1101682 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 12131151000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate 0.412692 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 1101682 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_accesses 125867 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency 11999.892744 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_miss_latency 1510390500 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_accesses 125803 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency 12002.178008 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.036494 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_miss_latency 1509910000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses 125867 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 1384631500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_misses 125803 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 1384215000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_misses 125867 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses 125803 # number of UpgradeReq MSHR misses
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 1051110500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses 429991 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 1050999500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses 429859 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
||||
system.l2c.Writeback_misses 429991 # number of Writeback misses
|
||||
system.l2c.Writeback_misses 429859 # number of Writeback misses
|
||||
system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
||||
system.l2c.Writeback_mshr_misses 429991 # number of Writeback MSHR misses
|
||||
system.l2c.Writeback_mshr_misses 429859 # number of Writeback MSHR misses
|
||||
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 1.660842 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 1.660129 # Average number of references to valid blocks.
|
||||
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses 2974527 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency 12000.338488 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
|
||||
system.l2c.demand_hits 1568273 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 16875524000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate 0.472766 # miss rate for demand accesses
|
||||
system.l2c.demand_misses 1406254 # number of demand (read+write) misses
|
||||
system.l2c.demand_accesses 2973955 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency 12009.888788 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 11009.888788 # average overall mshr miss latency
|
||||
system.l2c.demand_hits 1567817 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 16887561000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate 0.472818 # miss rate for demand accesses
|
||||
system.l2c.demand_misses 1406138 # number of demand (read+write) misses
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_miss_latency 15469270000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate 0.472766 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 1406254 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_miss_latency 15481423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate 0.472818 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 1406138 # number of demand (read+write) MSHR misses
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_accesses 2974527 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency 12000.338488 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
|
||||
system.l2c.overall_accesses 2973955 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency 12009.888788 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 11009.888788 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits 1568273 # number of overall hits
|
||||
system.l2c.overall_miss_latency 16875524000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate 0.472766 # miss rate for overall accesses
|
||||
system.l2c.overall_misses 1406254 # number of overall misses
|
||||
system.l2c.overall_hits 1567817 # number of overall hits
|
||||
system.l2c.overall_miss_latency 16887561000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate 0.472818 # miss rate for overall accesses
|
||||
system.l2c.overall_misses 1406138 # number of overall misses
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_miss_latency 15469270000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate 0.472766 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 1406254 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 1801212500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_miss_latency 15481423000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate 0.472818 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 1406138 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 1801101500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
|
|
@ -365,11 +435,11 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
|
|||
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.l2c.replacements 947259 # number of replacements
|
||||
system.l2c.sampled_refs 965538 # Sample count of references to valid blocks.
|
||||
system.l2c.replacements 947227 # number of replacements
|
||||
system.l2c.sampled_refs 965496 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 15874.904757 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1603606 # Total number of references to valid blocks.
|
||||
system.l2c.tagsinuse 15873.138648 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1602848 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 4106790000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 0 # number of writebacks
|
||||
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
Listening for system connection on port 3457
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
Listening for system connection on port 3456
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2007 04:02:11
|
||||
M5 started Fri Aug 3 04:23:34 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Aug 10 2007 16:03:34
|
||||
M5 started Fri Aug 10 16:04:35 2007
|
||||
M5 executing on zeep
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1910309711000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1909320028000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
|
|||
mem_mode=atomic
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=drivesys.physmem
|
||||
readfile=/z/stever/hg/m5.stever/configs/boot/netperf-server.rcS
|
||||
readfile=/z/saidi/work/m5.bb/configs/boot/netperf-server.rcS
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
|
|
@ -22,8 +22,8 @@ system_type=34
|
|||
[drivesys.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
fix_partial_write_a=false
|
||||
fix_partial_write_b=true
|
||||
filter_ranges_a=
|
||||
filter_ranges_b=
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
|
|
@ -708,7 +708,7 @@ kernel=/dist/m5/system/binaries/vmlinux
|
|||
mem_mode=atomic
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=testsys.physmem
|
||||
readfile=/z/stever/hg/m5.stever/configs/boot/netperf-stream-client.rcS
|
||||
readfile=/z/saidi/work/m5.bb/configs/boot/netperf-stream-client.rcS
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
|
|
@ -716,8 +716,8 @@ system_type=34
|
|||
[testsys.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
fix_partial_write_a=false
|
||||
fix_partial_write_b=true
|
||||
filter_ranges_a=
|
||||
filter_ranges_b=
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
|
||||
eth0: enabling optical transceiver
|
||||
eth0: using 64 bit addressing.
|
||||
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg
|
||||
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
|
|
@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x8410-0x8417,0x8422 on irq 31
|
||||
hda: max request size: 128KiB
|
||||
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
|
||||
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
|
||||
hda: cache flushes not supported
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
|
|
@ -99,8 +99,9 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
All bugs added by David S. Miller <davem@redhat.com>
|
||||
VFS: Mounted root (ext2 filesystem) readonly.
|
||||
Freeing unused kernel memory: 224k freed
|
||||
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
|
||||
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
|
||||
mounting filesystems...
|
||||
EXT2-fs warning: checktime reached, running e2fsck is recommended
|
||||
loading script...
|
||||
setting up network...
|
||||
eth0: link now 1000F mbps, full duplex and up.
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x8410-0x8417,0x8422 on irq 31
|
||||
hda: max request size: 128KiB
|
||||
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
|
||||
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
|
||||
hda: cache flushes not supported
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
|
|
@ -99,8 +99,9 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
All bugs added by David S. Miller <davem@redhat.com>
|
||||
VFS: Mounted root (ext2 filesystem) readonly.
|
||||
Freeing unused kernel memory: 224k freed
|
||||
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
|
||||
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
|
||||
mounting filesystems...
|
||||
EXT2-fs warning: checktime reached, running e2fsck is recommended
|
||||
loading script...
|
||||
setting up network...
|
||||
eth0: link now 1000F mbps, full duplex and up.
|
||||
|
|
|
|||
|
|
@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa
|
|||
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
|
||||
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
|
||||
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
host_inst_rate 51081325 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 406704 # Number of bytes of host memory used
|
||||
host_seconds 5.35 # Real time elapsed on the host
|
||||
host_tick_rate 37372483621 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 109126509 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 477016 # Number of bytes of host memory used
|
||||
host_seconds 2.51 # Real time elapsed on the host
|
||||
host_tick_rate 79838467246 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 273348482 # Number of instructions simulated
|
||||
sim_seconds 0.200001 # Number of seconds simulated
|
||||
|
|
@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to
|
|||
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
host_inst_rate 71036507796 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 406704 # Number of bytes of host memory used
|
||||
host_inst_rate 139108642239 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 477016 # Number of bytes of host memory used
|
||||
host_seconds 0.00 # Real time elapsed on the host
|
||||
host_tick_rate 191282064 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 375168496 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 273348482 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Listening for testsys connection on port 3457
|
||||
Listening for drivesys connection on port 3458
|
||||
0: testsys.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: drivesys.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
Listening for testsys connection on port 3456
|
||||
Listening for drivesys connection on port 3457
|
||||
0: testsys.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: drivesys.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Obsolete M5 instruction ivlb encountered.
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2007 04:02:11
|
||||
M5 started Fri Aug 3 04:26:58 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Aug 10 2007 16:03:34
|
||||
M5 started Fri Aug 10 16:06:35 2007
|
||||
M5 executing on zeep
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 4300235844056 because checkpoint
|
||||
|
|
|
|||
|
|
@ -317,7 +317,15 @@ bool AMD64TraceChild::step()
|
|||
ptrace(PTRACE_POKEDATA, pid, ripAfterSyscall, buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
//Get all the way past repe and repne string instructions in one shot.
|
||||
uint64_t newPC, origPC = getPC();
|
||||
do
|
||||
{
|
||||
ptraceSingleStep();
|
||||
newPC = getPC();
|
||||
} while(newPC == origPC);
|
||||
}
|
||||
}
|
||||
|
||||
TraceChild * genTraceChild()
|
||||
|
|
|
|||
Loading…
Reference in a new issue