X86: Make initCPU and startupCPU do something basic.
--HG-- extra : convert_revision : 1a04f4402f4f31e4e5cd482c7983d853fe117df5
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@ -102,6 +102,7 @@ if env['TARGET_ISA'] == 'x86':
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Source('regfile.cc')
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Source('remote_gdb.cc')
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Source('tlb.cc')
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Source('utility.cc')
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SimObject('X86TLB.py')
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@ -111,7 +112,6 @@ if env['TARGET_ISA'] == 'x86':
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# Full-system sources
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Source('system.cc')
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Source('stacktrace.cc')
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Source('utility.cc')
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Source('vtophys.cc')
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else:
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Source('process.cc')
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@ -117,6 +117,9 @@ namespace X86ISA
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// Flags register
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MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
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// Extended feature enable register
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MISCREG_EFER,
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// Segment selectors
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MISCREG_SEG_SEL_BASE,
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MISCREG_ES = MISCREG_SEG_SEL_BASE,
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@ -55,7 +55,11 @@
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* Authors: Gabe Black
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*/
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#include "arch/x86/intregs.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/segmentregs.hh"
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#include "arch/x86/utility.hh"
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#include "arch/x86/x86_traits.hh"
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namespace X86ISA {
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@ -67,4 +71,128 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
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M5_DUMMY_RETURN
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#endif
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}
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# if FULL_SYSTEM
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void initCPU(ThreadContext *tc, int cpuId)
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{
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// TODO Figure out what the attribute registers should be set to. How this
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// information is stored isn't specified, but it's values are in table
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// 14.2.
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// The otherwise unmodified integer registers should be set to 0.
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for (int index = 0; index < NUM_INTREGS; index++) {
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tc->setIntReg(index, 0);
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}
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// These next two loops zero internal microcode and implicit registers.
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// They aren't specified by the ISA but are used internally by M5's
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// implementation.
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for (int index = 0; index < NumMicroIntRegs; index++) {
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tc->setIntReg(INTREG_MICRO(index), 0);
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}
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for (int index = 0; index < NumImplicitIntRegs; index++) {
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tc->setIntReg(INTREG_IMPLICIT(index), 0);
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}
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// Set integer register EAX to 0 to indicate that the optional BIST
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// passed. No BIST actually runs, but software may still check this
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// register for errors.
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tc->setIntReg(INTREG_RAX, 0);
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//The following values are dictated by the architecture for after a RESET#
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tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
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tc->setMiscReg(MISCREG_CR2, 0);
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tc->setMiscReg(MISCREG_CR3, 0);
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tc->setMiscReg(MISCREG_CR4, 0);
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tc->setMiscReg(MISCREG_CR8, 0);
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tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
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tc->setMiscReg(MISCREG_EFER, 0);
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for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
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tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
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tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
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tc->setMiscReg(MISCREG_SEG_ATTR(seg), 0);
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}
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tc->setMiscReg(MISCREG_CS, 0xf000);
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tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
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// This has the base value pre-added.
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tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
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tc->setMiscReg(MISCREG_CS_ATTR, 0);
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tc->setPC(0x000000000000fff0 +
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tc->readMiscReg(MISCREG_CS_BASE));
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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tc->setMiscReg(MISCREG_GDTR_BASE, 0);
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tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_IDTR_BASE, 0);
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tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_LDTR, 0);
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tc->setMiscReg(MISCREG_LDTR_BASE, 0);
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tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
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tc->setMiscReg(MISCREG_TR, 0);
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tc->setMiscReg(MISCREG_TR_BASE, 0);
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tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_TR_ATTR, 0);
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// This value should be the family/model/stepping of the processor.
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// (page 418). It should be consistent with the value from CPUID, but the
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// actual value probably doesn't matter much.
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tc->setIntReg(INTREG_RDX, 0);
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// TODO initialize x87, 64 bit, and 128 bit media state
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// TODO Set up MTRRs (page 512)
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// TODO Set up machine check registers (page 515)
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tc->setMiscReg(MISCREG_DR0, 0);
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tc->setMiscReg(MISCREG_DR1, 0);
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tc->setMiscReg(MISCREG_DR2, 0);
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tc->setMiscReg(MISCREG_DR3, 0);
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tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
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tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
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// TODO Set time stamp counter to 0
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// TODO Set up performance monitoring registers (page 517)
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// TODO Set up the rest of the MSRs (page 507)
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// Invalidate the caches (this should already be done for us)
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// TODO Turn on the APIC. This should be handled elsewhere but it isn't
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// currently being handled at all.
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// Set the SMRAM base address (SMBASE) to 0x00030000
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}
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#endif
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void startupCPU(ThreadContext *tc, int cpuId)
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{
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if (cpuId == 0) {
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// This is the boot strap processor (BSP). Initialize it to look like
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// the boot loader has just turned control over to the 64 bit OS.
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// Enable paging, turn on long mode, etc.
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tc->activate(0);
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} else {
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// This is an application processor (AP). It should be initialized to
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// look like only the BIOS POST has run on it and put then put it into
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// a halted state.
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}
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}
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} //namespace X86_ISA
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@ -61,6 +61,7 @@
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#include "arch/x86/types.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "sim/host.hh"
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@ -140,15 +141,13 @@ namespace X86ISA
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template <class TC>
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void zeroRegisters(TC *tc);
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inline void initCPU(ThreadContext *tc, int cpuId)
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{
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panic("initCPU not implemented!\n");
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}
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#if FULL_SYSTEM
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inline void startupCPU(ThreadContext *tc, int cpuId)
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{
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tc->activate(0);
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}
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void initCPU(ThreadContext *tc, int cpuId);
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#endif
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void startupCPU(ThreadContext *tc, int cpuId);
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};
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#endif // __ARCH_X86_UTILITY_HH__
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