ARM: Seperate out the renamable bits in the FPSCR.
This commit is contained in:
parent
93ce7238bf
commit
63464d950e
5 changed files with 161 additions and 112 deletions
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@ -111,6 +111,7 @@ enum IntRegIndex
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INTREG_ZERO, // Dummy zero reg since there has to be one.
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INTREG_UREG0,
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INTREG_CONDCODES,
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INTREG_FPCONDCODES,
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NUM_INTREGS,
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NUM_ARCH_INTREGS = INTREG_PC + 1,
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@ -1969,7 +1969,11 @@ let {{
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default:
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return new Unknown(machInst);
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}
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return new Vmsr(machInst, (IntRegIndex)specReg, rt);
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if (specReg == MISCREG_FPSCR) {
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return new VmsrFpscr(machInst, (IntRegIndex)specReg, rt);
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} else {
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return new Vmsr(machInst, (IntRegIndex)specReg, rt);
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}
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}
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} else if (l == 0 && c == 1) {
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if (bits(a, 2) == 0) {
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@ -2061,8 +2065,15 @@ let {{
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cpsrMask.z = 1;
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cpsrMask.c = 1;
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cpsrMask.v = 1;
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return new VmrsApsr(machInst, INTREG_CONDCODES,
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(IntRegIndex)specReg, (uint32_t)cpsrMask);
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if (specReg == MISCREG_FPSCR) {
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return new VmrsApsrFpscr(machInst, INTREG_CONDCODES,
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(IntRegIndex)specReg, (uint32_t)cpsrMask);
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} else {
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return new VmrsApsr(machInst, INTREG_CONDCODES,
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(IntRegIndex)specReg, (uint32_t)cpsrMask);
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}
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} else if (specReg == MISCREG_FPSCR) {
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return new VmrsFpscr(machInst, rt, (IntRegIndex)specReg);
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} else {
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return new Vmrs(machInst, rt, (IntRegIndex)specReg);
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}
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@ -199,6 +199,17 @@ let {{
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decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
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exec_output += PredOpExecute.subst(vmsrIop);
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vmsrFpscrCode = vmsrrsEnabledCheckCode + '''
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Fpscr = Op1 & ~FpCondCodesMask;
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FpCondCodes = Op1 & FpCondCodesMask;
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'''
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vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp",
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{ "code": vmsrFpscrCode,
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"predicate_test": predicateTest }, [])
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header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
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decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
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exec_output += PredOpExecute.subst(vmsrFpscrIop);
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vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp",
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{ "code": vmsrrsEnabledCheckCode + \
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"Dest = MiscOp1;",
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@ -207,7 +218,17 @@ let {{
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decoder_output += FpRegRegOpConstructor.subst(vmrsIop);
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exec_output += PredOpExecute.subst(vmrsIop);
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vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"
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vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp",
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{ "code": vmsrrsEnabledCheckCode + \
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"Dest = Fpscr | FpCondCodes;",
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"predicate_test": predicateTest }, [])
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header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
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decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
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exec_output += PredOpExecute.subst(vmrsFpscrIop);
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vmrsApsrCode = vmsrrsEnabledCheckCode + '''
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Dest = (MiscOp1 & imm) | (Dest & ~imm);
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'''
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vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
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{ "code": vmrsApsrCode,
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"predicate_test": predicateTest }, [])
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@ -215,6 +236,17 @@ let {{
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decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
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exec_output += PredOpExecute.subst(vmrsApsrIop);
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vmrsApsrFpscrCode = vmsrrsEnabledCheckCode + '''
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assert((imm & ~FpCondCodesMask) == 0);
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Dest = (FpCondCodes & imm) | (Dest & ~imm);
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'''
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vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
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{ "code": vmrsApsrFpscrCode,
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"predicate_test": predicateTest }, [])
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header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
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decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);
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exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
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vmovImmSCode = vfpEnabledCheckCode + '''
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FpDest.uw = bits(imm, 31, 0);
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'''
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@ -397,17 +429,17 @@ let {{
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exec_output = ""
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singleCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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FpDest = %(op)s;
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \
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"%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
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singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
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doubleCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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double dest = %(op)s;
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(dest);
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FpDestP1.uw = dblHi(dest);
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'''
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@ -503,12 +535,12 @@ let {{
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exec_output = ""
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vmlaSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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float mid = binaryOp(fpscr, FpOp1, FpOp2,
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fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
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FpDest = binaryOp(fpscr, FpDest, mid, fpAddS,
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fpscr.fz, fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",
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{ "code": vmlaSCode,
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@ -518,14 +550,14 @@ let {{
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exec_output += PredOpExecute.subst(vmlaSIop);
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vmlaDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
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dbl(FpOp2P0.uw, FpOp2P1.uw),
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fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
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double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
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mid, fpAddD, fpscr.fz,
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fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(dest);
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FpDestP1.uw = dblHi(dest);
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'''
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@ -537,12 +569,12 @@ let {{
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exec_output += PredOpExecute.subst(vmlaDIop);
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vmlsSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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float mid = binaryOp(fpscr, FpOp1, FpOp2,
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fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
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FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS,
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fpscr.fz, fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",
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{ "code": vmlsSCode,
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@ -552,14 +584,14 @@ let {{
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exec_output += PredOpExecute.subst(vmlsSIop);
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vmlsDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
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dbl(FpOp2P0.uw, FpOp2P1.uw),
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fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
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double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
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-mid, fpAddD, fpscr.fz,
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fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(dest);
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FpDestP1.uw = dblHi(dest);
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'''
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@ -571,12 +603,12 @@ let {{
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exec_output += PredOpExecute.subst(vmlsDIop);
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vnmlaSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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float mid = binaryOp(fpscr, FpOp1, FpOp2,
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fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
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FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS,
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fpscr.fz, fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",
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{ "code": vnmlaSCode,
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@ -586,14 +618,14 @@ let {{
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exec_output += PredOpExecute.subst(vnmlaSIop);
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vnmlaDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
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dbl(FpOp2P0.uw, FpOp2P1.uw),
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fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
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double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
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-mid, fpAddD, fpscr.fz,
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fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(dest);
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FpDestP1.uw = dblHi(dest);
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'''
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@ -605,12 +637,12 @@ let {{
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exec_output += PredOpExecute.subst(vnmlaDIop);
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vnmlsSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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float mid = binaryOp(fpscr, FpOp1, FpOp2,
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fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
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FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS,
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fpscr.fz, fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",
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{ "code": vnmlsSCode,
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@ -620,14 +652,14 @@ let {{
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exec_output += PredOpExecute.subst(vnmlsSIop);
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vnmlsDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
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dbl(FpOp2P0.uw, FpOp2P1.uw),
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fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
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double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
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mid, fpAddD, fpscr.fz,
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fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(dest);
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FpDestP1.uw = dblHi(dest);
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'''
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@ -639,10 +671,10 @@ let {{
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exec_output += PredOpExecute.subst(vnmlsDIop);
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vnmulSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS,
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fpscr.fz, fpscr.dn, fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",
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{ "code": vnmulSCode,
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@ -652,12 +684,12 @@ let {{
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exec_output += PredOpExecute.subst(vnmulSIop);
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vnmulDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
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dbl(FpOp2P0.uw, FpOp2P1.uw),
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fpMulD, fpscr.fz, fpscr.dn,
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fpscr.rMode);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(dest);
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FpDestP1.uw = dblHi(dest);
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'''
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@ -676,13 +708,13 @@ let {{
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exec_output = ""
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vcvtUIntFpSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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VfpSavedState state = prepFpState(fpscr.rMode);
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__asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
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FpDest = FpOp1.uw;
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__asm__ __volatile__("" :: "m" (FpDest));
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finishVfp(fpscr, state, fpscr.fz);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
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{ "code": vcvtUIntFpSCode,
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@ -692,13 +724,13 @@ let {{
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exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
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vcvtUIntFpDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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VfpSavedState state = prepFpState(fpscr.rMode);
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__asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
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double cDest = (uint64_t)FpOp1P0.uw;
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__asm__ __volatile__("" :: "m" (cDest));
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finishVfp(fpscr, state, fpscr.fz);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(cDest);
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FpDestP1.uw = dblHi(cDest);
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'''
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@ -710,13 +742,13 @@ let {{
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exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
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vcvtSIntFpSCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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VfpSavedState state = prepFpState(fpscr.rMode);
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__asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
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FpDest = FpOp1.sw;
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__asm__ __volatile__("" :: "m" (FpDest));
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finishVfp(fpscr, state, fpscr.fz);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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'''
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vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
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{ "code": vcvtSIntFpSCode,
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@ -726,13 +758,13 @@ let {{
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exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
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vcvtSIntFpDCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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VfpSavedState state = prepFpState(fpscr.rMode);
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__asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
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double cDest = FpOp1P0.sw;
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__asm__ __volatile__("" :: "m" (cDest));
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finishVfp(fpscr, state, fpscr.fz);
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Fpscr = fpscr;
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FpCondCodes = fpscr & FpCondCodesMask;
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FpDestP0.uw = dblLow(cDest);
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FpDestP1.uw = dblHi(cDest);
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'''
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@ -744,14 +776,14 @@ let {{
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exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
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vcvtFpUIntSRCode = vfpEnabledCheckCode + '''
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FPSCR fpscr = Fpscr;
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FPSCR fpscr = Fpscr | FpCondCodes;
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VfpSavedState state = prepFpState(fpscr.rMode);
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vfpFlushToZero(fpscr, FpOp1);
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__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
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FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.uw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
|
||||
{ "code": vcvtFpUIntSRCode,
|
||||
|
@ -761,7 +793,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
|
||||
|
||||
vcvtFpUIntDRCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -769,7 +801,7 @@ let {{
|
|||
uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false);
|
||||
__asm__ __volatile__("" :: "m" (result));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = result;
|
||||
'''
|
||||
vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
|
||||
|
@ -780,14 +812,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
|
||||
|
||||
vcvtFpSIntSRCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.sw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
|
||||
{ "code": vcvtFpSIntSRCode,
|
||||
|
@ -797,7 +829,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
|
||||
|
||||
vcvtFpSIntDRCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -805,7 +837,7 @@ let {{
|
|||
int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false);
|
||||
__asm__ __volatile__("" :: "m" (result));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = result;
|
||||
'''
|
||||
vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
|
||||
|
@ -816,7 +848,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
|
||||
|
||||
vcvtFpUIntSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
fesetround(FeRoundZero);
|
||||
|
@ -824,7 +856,7 @@ let {{
|
|||
FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.uw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
|
||||
{ "code": vcvtFpUIntSCode,
|
||||
|
@ -834,7 +866,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
|
||||
|
||||
vcvtFpUIntDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -843,7 +875,7 @@ let {{
|
|||
uint64_t result = vfpFpDToFixed(cOp1, false, false, 0);
|
||||
__asm__ __volatile__("" :: "m" (result));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = result;
|
||||
'''
|
||||
vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
|
||||
|
@ -854,7 +886,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
|
||||
|
||||
vcvtFpSIntSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
fesetround(FeRoundZero);
|
||||
|
@ -862,7 +894,7 @@ let {{
|
|||
FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.sw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
|
||||
{ "code": vcvtFpSIntSCode,
|
||||
|
@ -872,7 +904,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
|
||||
|
||||
vcvtFpSIntDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -881,7 +913,7 @@ let {{
|
|||
int64_t result = vfpFpDToFixed(cOp1, true, false, 0);
|
||||
__asm__ __volatile__("" :: "m" (result));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = result;
|
||||
'''
|
||||
vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
|
||||
|
@ -892,14 +924,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
|
||||
|
||||
vcvtFpSFpDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
double cDest = fixFpSFpDDest(Fpscr, FpOp1);
|
||||
__asm__ __volatile__("" :: "m" (cDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = dblLow(cDest);
|
||||
FpDestP1.uw = dblHi(cDest);
|
||||
'''
|
||||
|
@ -911,7 +943,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
|
||||
|
||||
vcvtFpDFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -919,7 +951,7 @@ let {{
|
|||
FpDest = fixFpDFpSDest(Fpscr, cOp1);
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
|
||||
{ "code": vcvtFpDFpSCode,
|
||||
|
@ -929,7 +961,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
|
||||
|
||||
vcvtFpHTFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
|
@ -937,7 +969,7 @@ let {{
|
|||
bits(fpToBits(FpOp1), 31, 16));
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp",
|
||||
{ "code": vcvtFpHTFpSCode,
|
||||
|
@ -947,14 +979,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpHTFpSIop);
|
||||
|
||||
vcvtFpHBFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp,
|
||||
bits(fpToBits(FpOp1), 15, 0));
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp",
|
||||
{ "code": vcvtFpHBFpSCode,
|
||||
|
@ -964,7 +996,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpHBFpSIop);
|
||||
|
||||
vcvtFpSFpHTCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
|
||||
|
@ -974,7 +1006,7 @@ let {{
|
|||
fpscr.rMode, fpscr.ahp, FpOp1));
|
||||
__asm__ __volatile__("" :: "m" (FpDest.uw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp",
|
||||
{ "code": vcvtFpHTFpSCode,
|
||||
|
@ -984,7 +1016,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSFpHTIop);
|
||||
|
||||
vcvtFpSFpHBCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
|
||||
|
@ -994,7 +1026,7 @@ let {{
|
|||
fpscr.rMode, fpscr.ahp, FpOp1));
|
||||
__asm__ __volatile__("" :: "m" (FpDest.uw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp",
|
||||
{ "code": vcvtFpSFpHBCode,
|
||||
|
@ -1004,7 +1036,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSFpHBIop);
|
||||
|
||||
vcmpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpDest, FpOp1);
|
||||
if (FpDest == FpOp1) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1022,7 +1054,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",
|
||||
{ "code": vcmpSCode,
|
||||
|
@ -1034,7 +1066,7 @@ let {{
|
|||
vcmpDCode = vfpEnabledCheckCode + '''
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, cDest, cOp1);
|
||||
if (cDest == cOp1) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1052,7 +1084,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
|
||||
{ "code": vcmpDCode,
|
||||
|
@ -1062,7 +1094,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcmpDIop);
|
||||
|
||||
vcmpZeroSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpDest);
|
||||
// This only handles imm == 0 for now.
|
||||
assert(imm == 0);
|
||||
|
@ -1080,7 +1112,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
|
||||
{ "code": vcmpZeroSCode,
|
||||
|
@ -1093,7 +1125,7 @@ let {{
|
|||
// This only handles imm == 0 for now.
|
||||
assert(imm == 0);
|
||||
double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, cDest);
|
||||
if (cDest == imm) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1109,7 +1141,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
|
||||
{ "code": vcmpZeroDCode,
|
||||
|
@ -1119,7 +1151,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcmpZeroDIop);
|
||||
|
||||
vcmpeSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpDest, FpOp1);
|
||||
if (FpDest == FpOp1) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1131,7 +1163,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
|
||||
{ "code": vcmpeSCode,
|
||||
|
@ -1143,7 +1175,7 @@ let {{
|
|||
vcmpeDCode = vfpEnabledCheckCode + '''
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, cDest, cOp1);
|
||||
if (cDest == cOp1) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1155,7 +1187,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
|
||||
{ "code": vcmpeDCode,
|
||||
|
@ -1165,7 +1197,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcmpeDIop);
|
||||
|
||||
vcmpeZeroSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpDest);
|
||||
if (FpDest == imm) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1177,7 +1209,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
|
||||
{ "code": vcmpeZeroSCode,
|
||||
|
@ -1188,7 +1220,7 @@ let {{
|
|||
|
||||
vcmpeZeroDCode = vfpEnabledCheckCode + '''
|
||||
double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, cDest);
|
||||
if (cDest == imm) {
|
||||
fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
|
||||
|
@ -1200,7 +1232,7 @@ let {{
|
|||
fpscr.ioc = 1;
|
||||
fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
|
||||
}
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp",
|
||||
{ "code": vcmpeZeroDCode,
|
||||
|
@ -1217,14 +1249,14 @@ let {{
|
|||
exec_output = ""
|
||||
|
||||
vcvtFpSFixedSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.sw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
|
||||
{ "code": vcvtFpSFixedSCode,
|
||||
|
@ -1234,7 +1266,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
|
||||
|
||||
vcvtFpSFixedDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -1242,7 +1274,7 @@ let {{
|
|||
uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (mid));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = mid;
|
||||
FpDestP1.uw = mid >> 32;
|
||||
'''
|
||||
|
@ -1254,14 +1286,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
|
||||
|
||||
vcvtFpUFixedSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.uw));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
|
||||
{ "code": vcvtFpUFixedSCode,
|
||||
|
@ -1271,7 +1303,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
|
||||
|
||||
vcvtFpUFixedDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -1279,7 +1311,7 @@ let {{
|
|||
uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (mid));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = mid;
|
||||
FpDestP1.uw = mid >> 32;
|
||||
'''
|
||||
|
@ -1291,13 +1323,13 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
|
||||
|
||||
vcvtSFixedFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
|
||||
FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
|
||||
{ "code": vcvtSFixedFpSCode,
|
||||
|
@ -1307,14 +1339,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
|
||||
|
||||
vcvtSFixedFpDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (mid) : "m" (mid));
|
||||
double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (cDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = dblLow(cDest);
|
||||
FpDestP1.uw = dblHi(cDest);
|
||||
'''
|
||||
|
@ -1326,13 +1358,13 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
|
||||
|
||||
vcvtUFixedFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
|
||||
FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
|
||||
{ "code": vcvtUFixedFpSCode,
|
||||
|
@ -1342,14 +1374,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
|
||||
|
||||
vcvtUFixedFpDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (mid) : "m" (mid));
|
||||
double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
|
||||
__asm__ __volatile__("" :: "m" (cDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = dblLow(cDest);
|
||||
FpDestP1.uw = dblHi(cDest);
|
||||
'''
|
||||
|
@ -1361,14 +1393,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
|
||||
|
||||
vcvtFpSHFixedSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.sh));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
|
||||
"FpRegRegImmOp",
|
||||
|
@ -1379,7 +1411,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
|
||||
|
||||
vcvtFpSHFixedDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -1387,7 +1419,7 @@ let {{
|
|||
uint64_t result = vfpFpDToFixed(cOp1, true, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (result));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = result;
|
||||
FpDestP1.uw = result >> 32;
|
||||
'''
|
||||
|
@ -1400,14 +1432,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
|
||||
|
||||
vcvtFpUHFixedSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
vfpFlushToZero(fpscr, FpOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
|
||||
FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest.uh));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
|
||||
"FpRegRegImmOp",
|
||||
|
@ -1418,7 +1450,7 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
|
||||
|
||||
vcvtFpUHFixedDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
|
||||
vfpFlushToZero(fpscr, cOp1);
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
|
@ -1426,7 +1458,7 @@ let {{
|
|||
uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (mid));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = mid;
|
||||
FpDestP1.uw = mid >> 32;
|
||||
'''
|
||||
|
@ -1439,13 +1471,13 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
|
||||
|
||||
vcvtSHFixedFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
|
||||
FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
|
||||
"FpRegRegImmOp",
|
||||
|
@ -1456,14 +1488,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
|
||||
|
||||
vcvtSHFixedFpDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (mid) : "m" (mid));
|
||||
double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (cDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = dblLow(cDest);
|
||||
FpDestP1.uw = dblHi(cDest);
|
||||
'''
|
||||
|
@ -1476,13 +1508,13 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
|
||||
|
||||
vcvtUHFixedFpSCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
|
||||
FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (FpDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
'''
|
||||
vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
|
||||
"FpRegRegImmOp",
|
||||
|
@ -1493,14 +1525,14 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
|
||||
|
||||
vcvtUHFixedFpDCode = vfpEnabledCheckCode + '''
|
||||
FPSCR fpscr = Fpscr;
|
||||
FPSCR fpscr = Fpscr | FpCondCodes;
|
||||
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepFpState(fpscr.rMode);
|
||||
__asm__ __volatile__("" : "=m" (mid) : "m" (mid));
|
||||
double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
|
||||
__asm__ __volatile__("" :: "m" (cDest));
|
||||
finishVfp(fpscr, state, fpscr.fz);
|
||||
Fpscr = fpscr;
|
||||
FpCondCodes = fpscr & FpCondCodesMask;
|
||||
FpDestP0.uw = dblLow(cDest);
|
||||
FpDestP1.uw = dblHi(cDest);
|
||||
'''
|
||||
|
|
|
@ -182,6 +182,7 @@ def operands {{
|
|||
'OptCondCodes': ('IntReg', 'uw',
|
||||
'''(condCode == COND_AL || condCode == COND_UC) ?
|
||||
INTREG_ZERO : INTREG_CONDCODES''', None, 2),
|
||||
'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 2),
|
||||
|
||||
#Register fields for microops
|
||||
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
|
||||
|
|
|
@ -354,6 +354,10 @@ namespace ArmISA
|
|||
Bitfield<31> n;
|
||||
EndBitUnion(FPSCR)
|
||||
|
||||
// This mask selects bits of the FPSCR that actually go in the FpCondCodes
|
||||
// integer register to allow renaming.
|
||||
static const uint32_t FpCondCodesMask = 0xF800009F;
|
||||
|
||||
BitUnion32(FPEXC)
|
||||
Bitfield<31> ex;
|
||||
Bitfield<30> en;
|
||||
|
|
Loading…
Reference in a new issue