Merge zizzer:/bk/newmem

into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : a0bfc7495ba0f2916214d6712f67c5c239a210a0

arch/mips/faults.cc

@@ -98,6 +98,10 @@ FaultName IntegerOverflowFault::_name = "intover";
 FaultVect IntegerOverflowFault::_vect = 0x0501;
 FaultStat IntegerOverflowFault::_count;
 
+FaultName UnimpFault::_name = "Unimplemented Simulator feature";
+FaultVect UnimpFault::_vect = 0x0001;
+FaultStat UnimpFault::_count;
+
 #if FULL_SYSTEM
 
 void MipsFault::invoke(ExecContext * xc)
@@ -125,6 +129,12 @@ void ArithmeticFault::invoke(ExecContext * xc)
     panic("Arithmetic traps are unimplemented!");
 }
 
+void UnimpFault::invoke(ExecContext * xc)
+{
+    FaultBase::invoke(xc);
+    panic("Unimpfault: %s\n", panicStr.c_str());
+}
+
 #endif
 
 } // namespace MipsISA

arch/mips/faults.hh

@@ -264,6 +264,26 @@ class IntegerOverflowFault : public MipsFault
     FaultStat & countStat() {return _count;}
 };
 
+class UnimpFault : public MipsFault
+{
+  private:
+    std::string panicStr;
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    UnimpFault(std::string _str)
+        : panicStr(_str)
+    { }
+
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ExecContext * xc);
+#endif
+};
+
 } // MipsISA namespace
 
 #endif // __FAULTS_HH__

arch/mips/isa/base.isa

@@ -9,8 +9,6 @@
 output header {{
 
 #define R31 31
-#include "arch/mips/faults.hh"
-#include "arch/mips/isa_traits.hh"
 
     using namespace MipsISA;
 

arch/mips/isa/includes.isa

@@ -17,6 +17,8 @@ output decoder {{
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
 
 #include <math.h>
 #if defined(linux)
@@ -27,6 +29,7 @@ using namespace MipsISA;
 }};
 
 output exec {{
+#include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
 #include <math.h>
 #if defined(linux)

arch/sparc/faults.cc

@@ -215,7 +215,10 @@ TrapType      TrapInstruction::_baseTrapType = 0x100;
 FaultPriority TrapInstruction::_priority = 16;
 FaultStat     TrapInstruction::_count;
 
-
+FaultName     UnimpFault::_name = "Unimplemented Simulator feature";
+TrapType      UnimpFault::_trapType = 0x000;
+FaultPriority UnimpFault::_priority = 0;
+FaultStat     UnimpFault::_count;
 
 #if FULL_SYSTEM
 
@@ -242,6 +245,12 @@ void SparcFault::invoke(ExecContext * xc)
     xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
 }
 
+void UnimpFault::invoke(ExecContext * xc)
+{
+    panic("Unimpfault: %s\n", panicStr.c_str());
+}
+
+
 #endif
 
 } // namespace SparcISA

arch/sparc/faults.hh

@@ -581,6 +581,29 @@ class TrapInstruction : public EnumeratedFault
     FaultStat & countStat() {return _count;}
 };
 
+class UnimpFault : public SparcFault
+{
+  private:
+    static FaultName _name;
+    static TrapType _trapType;
+    static FaultPriority _priority;
+    static FaultStat _count;
+    std::string panicStr;
+  public:
+    UnimpFault(std::string _str)
+        : panicStr(_str)
+    { }
+
+    FaultName name() {return _name;}
+    TrapType trapType() {return _trapType;}
+    FaultPriority priority() {return _priority;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ExecContext * xc);
+#endif
+};
+
+
 } // SparcISA namespace
 
 #endif // __FAULTS_HH__

dev/alpha_console.cc

@@ -120,8 +120,7 @@ AlphaConsole::read(Packet &pkt)
             if (!pkt.data) {
                 data32 = new uint32_t;
                 pkt.data = (uint8_t*)data32;
-            }
+            } else
-            else
                 data32 = (uint32_t*)pkt.data;
 
             switch (daddr)
@@ -150,8 +149,7 @@ AlphaConsole::read(Packet &pkt)
             if (!pkt.data) {
                 data64 = new uint64_t;
                 pkt.data = (uint8_t*)data64;
-            }
+            } else
-            else
                 data64 = (uint64_t*)pkt.data;
             switch (daddr)
             {

dev/io_device.hh

@@ -192,11 +192,17 @@ class PioDevice : public SimObject
     { return pkt.cmd == Read ? this->read(pkt) : this->write(pkt); }
 
     /** Pure virtual function that the device must implement. Called when a read
-     * command is recieved by the port. */
+     * command is recieved by the port.
+     * @param pkt Packet describing this request
+     * @return number of ticks it took to complete
+     */
     virtual Tick read(Packet &pkt) = 0;
 
     /** Pure virtual function that the device must implement. Called when a
-     * write command is recieved by the port. */
+     * write command is recieved by the port.
+     * @param pkt Packet describing this request
+     * @return number of ticks it took to complete
+     */
     virtual Tick write(Packet &pkt) = 0;
 
   public:

dev/tsunami_cchip.cc

@@ -39,10 +39,7 @@
 #include "dev/tsunami_cchip.hh"
 #include "dev/tsunamireg.h"
 #include "dev/tsunami.hh"
-#include "mem/bus/bus.hh"
+#include "mem/port.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
@@ -52,19 +49,10 @@ using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
+TsunamiCChip::TsunamiCChip(Params *p)
-                           MemoryController *mmu, HierParams *hier,
+    : BasicPioDevice(p), tsunami(p->tsunami)
-                           Bus* pio_bus, Tick pio_latency)
-    : PioDevice(name, t), addr(a), tsunami(t)
 {
-    mmu->add_child(this, RangeSize(addr, size));
+    pioSize = 0xfffffff;
-
-    if (pio_bus) {
-        pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
-                                      &TsunamiCChip::cacheAccess);
-        pioInterface->addAddrRange(RangeSize(addr, size));
-        pioLatency = pio_latency * pio_bus->clockRate;
-    }
 
     drir = 0;
     ipint = 0;
@@ -80,123 +68,137 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
     tsunami->cchip = this;
 }
 
-Fault
+Tick
-TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
+TsunamiCChip::read(Packet &pkt)
 {
     DPRINTF(Tsunami, "read  va=%#x size=%d\n", req->vaddr, req->size);
 
-    Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
+    assert(pkt.result == Unknown);
-    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
+    assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
 
-    ExecContext *xc = req->xc;
+    pkt.time = curTick + pioDelay;
+    Addr regnum = (req->paddr - pioAddr) >> 6;
+    Addr daddr = (req->paddr - pioAddr);
 
-    switch (req->size) {
+    uint32_t *data32;
+    uint64_t *data64;
+
+    switch (pkt.size) {
 
       case sizeof(uint64_t):
+          if (!pkt.data) {
+              data64 = new uint64_t;
+              pkt.data = (uint8_t*)data64;
+          } else
+              data64 = (uint64_t*)pkt.data;
+
           if (daddr & TSDEV_CC_BDIMS)
           {
-              *(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
+              *data64 = dim[(daddr >> 4) & 0x3F];
-              return NoFault;
+              break;
           }
 
           if (daddr & TSDEV_CC_BDIRS)
           {
-              *(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
+              *data64 = dir[(daddr >> 4) & 0x3F];
-              return NoFault;
+              break;
           }
 
           switch(regnum) {
               case TSDEV_CC_CSR:
-                  *(uint64_t*)data = 0x0;
+                  *data64 = 0x0;
-                  return NoFault;
+                  break;
               case TSDEV_CC_MTR:
                   panic("TSDEV_CC_MTR not implemeted\n");
-                   return NoFault;
+                   break;
               case TSDEV_CC_MISC:
-                  *(uint64_t*)data = (ipint << 8) & 0xF |
+                  *data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
-                                     (itint << 4) & 0xF |
+                                     (pkt.req->cpuId & 0x3);
-                                     (xc->readCpuId() & 0x3);
+                  break;
-                  return NoFault;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
               case TSDEV_CC_AAR2:
               case TSDEV_CC_AAR3:
-                  *(uint64_t*)data = 0;
+                  *data64 = 0;
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIM0:
-                  *(uint64_t*)data = dim[0];
+                  *data64 = dim[0];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIM1:
-                  *(uint64_t*)data = dim[1];
+                  *data64 = dim[1];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIM2:
-                  *(uint64_t*)data = dim[2];
+                  *data64 = dim[2];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIM3:
-                  *(uint64_t*)data = dim[3];
+                  *data64 = dim[3];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIR0:
-                  *(uint64_t*)data = dir[0];
+                  *data64 = dir[0];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIR1:
-                  *(uint64_t*)data = dir[1];
+                  *data64 = dir[1];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIR2:
-                  *(uint64_t*)data = dir[2];
+                  *data64 = dir[2];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DIR3:
-                  *(uint64_t*)data = dir[3];
+                  *data64 = dir[3];
-                  return NoFault;
+                  break;
               case TSDEV_CC_DRIR:
-                  *(uint64_t*)data = drir;
+                  *data64 = drir;
-                  return NoFault;
+                  break;
               case TSDEV_CC_PRBEN:
                   panic("TSDEV_CC_PRBEN not implemented\n");
-                  return NoFault;
+                  break;
               case TSDEV_CC_IIC0:
               case TSDEV_CC_IIC1:
               case TSDEV_CC_IIC2:
               case TSDEV_CC_IIC3:
                   panic("TSDEV_CC_IICx not implemented\n");
-                  return NoFault;
+                  break;
               case TSDEV_CC_MPR0:
               case TSDEV_CC_MPR1:
               case TSDEV_CC_MPR2:
               case TSDEV_CC_MPR3:
                   panic("TSDEV_CC_MPRx not implemented\n");
-                  return NoFault;
+                  break;
               case TSDEV_CC_IPIR:
-                  *(uint64_t*)data = ipint;
+                  *data64 = ipint;
-                  return NoFault;
+                  break;
               case TSDEV_CC_ITIR:
-                  *(uint64_t*)data = itint;
+                  *data64 = itint;
-                  return NoFault;
+                  break;
               default:
                   panic("default in cchip read reached, accessing 0x%x\n");
            } // uint64_t
 
       break;
       case sizeof(uint32_t):
-          if (regnum == TSDEV_CC_DRIR) {
-              warn("accessing DRIR with 32 bit read, "
-                   "hopefully your just reading this for timing");
-              *(uint32_t*)data = drir;
-          } else
-              panic("invalid access size(?) for tsunami register!\n");
-          return NoFault;
       case sizeof(uint16_t):
       case sizeof(uint8_t):
       default:
         panic("invalid access size(?) for tsunami register!\n");
     }
-    DPRINTFN("Tsunami CChip ERROR: read  regnum=%#x size=%d\n", regnum, req->size);
+    DPRINTFN("Tsunami CChip: read  regnum=%#x size=%d data=%lld\n", regnum,
+            req->size, *data);
 
-    return NoFault;
+    pkt.result = Success;
+    return pioDelay;
 }
 
-Fault
+Tick
-TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
+TsunamiCChip::write(Packet &pkt)
 {
+    pkt.time = curTick + pioDelay;
+
+
+    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+    Addr daddr = pkt.addr - pioAddr;
+
+    uint64_t val = *(uint64_t *)pkt.data;
+    assert(pkt.size == sizeof(uint64_t));
+
     DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
             req->vaddr, *(uint64_t*)data, req->size);
 

dev/tsunami_cchip.hh

@@ -37,21 +37,13 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 
-class MemoryController;
 
 /**
  * Tsunami CChip CSR Emulation. This device includes all the interrupt
  * handling code for the chipset.
  */
-class TsunamiCChip : public PioDevice
+class TsunamiCChip : public BasicPioDevice
 {
-  private:
-    /** The base address of this device */
-    Addr addr;
-
-    /** The size of mappad from the above address */
-    static const Addr size = 0xfffffff;
-
   protected:
     /**
      * pointer to the tsunami object.
@@ -84,37 +76,25 @@ class TsunamiCChip : public PioDevice
     /** Indicator of which CPUs have an RTC interrupt */
     uint64_t itint;
 
+  public:
+    struct Params : public BasicPioDevice::Params
+    {
+        Tsunami *tsunami;
+    };
+  protected:
+    const Params *params() const {return (const Params *)_params; }
+
   public:
     /**
      * Initialize the Tsunami CChip by setting all of the
      * device register to 0.
-     * @param name name of this device.
+     * @param p params struct
-     * @param t pointer back to the Tsunami object that we belong to.
-     * @param a address we are mapped at.
-     * @param mmu pointer to the memory controller that sends us events.
-     * @param hier object to store parameters universal the device hierarchy
-     * @param bus The bus that this device is attached to
      */
-    TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
+    TsunamiCChip(Params *p);
-                 MemoryController *mmu, HierParams *hier, Bus *pio_bus,
-                 Tick pio_latency);
 
-    /**
+    virtual Tick read(Packet &pkt);
-      * Process a read to the CChip.
-      * @param req Contains the address to read from.
-      * @param data A pointer to write the read data to.
-      * @return The fault condition of the access.
-      */
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
-
+    virtual Tick write(Packet &pkt);
-    /**
-      * Process a write to the CChip.
-      * @param req Contains the address to write to.
-      * @param data The data to write.
-      * @return The fault condition of the access.
-      */
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * post an RTC interrupt to the CPU
@@ -165,12 +145,6 @@ class TsunamiCChip : public PioDevice
      */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-    /**
-     * Return how long this access will take.
-     * @param req the memory request to calcuate
-     * @return Tick when the request is done
-     */
-    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __TSUNAMI_CCHIP_HH__

sim/process.cc

@@ -316,7 +316,7 @@ LiveProcess::argsInit(int intSize, int pageSize)
                      roundUp(stack_size, pageSize));
 
     // map out initial stack contents
-    Addr argv_array_base = stack_min + sizeof(uint64_t); // room for argc
+    Addr argv_array_base = stack_min + intSize; // room for argc
     Addr envp_array_base = argv_array_base + argv_array_size;
     Addr arg_data_base = envp_array_base + envp_array_size;
     Addr env_data_base = arg_data_base + arg_data_size;