fixes for newmem
ALPHA_FS finally compiles again SConscript: Use a couple more FS sources, still don't compile that much arch/alpha/faults.hh: the unimp fault should probably exist in nonfs too. dev/alpha_console.cc: dev/alpha_console.hh: dev/simconsole.cc: dev/simple_disk.cc: dev/simple_disk.hh: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: sim/process.cc: sim/system.cc: fixes for newmem dev/io_device.hh: a system pointer is probably useful for every device to have mem/bus.hh: mem/physical.cc: new address ranges function python/m5/objects/SimpleDisk.py: simple disk now has a system pointer rather than physmem directly --HG-- extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
This commit is contained in:
parent
bb80f71f21
commit
6240f8c4bc
17 changed files with 131 additions and 141 deletions
12
SConscript
12
SConscript
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@ -183,7 +183,13 @@ full_system_sources = Split('''
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cpu/profile.cc
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cpu/profile.cc
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dev/alpha_console.cc
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dev/alpha_console.cc
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dev/disk_image.cc
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dev/io_device.cc
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dev/io_device.cc
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dev/platform.cc
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dev/simconsole.cc
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dev/simple_disk.cc
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dev/uart.cc
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dev/uart8250.cc
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kern/kernel_binning.cc
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kern/kernel_binning.cc
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kern/kernel_stats.cc
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kern/kernel_stats.cc
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@ -198,8 +204,6 @@ full_system_sources = Split('''
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''')
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''')
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# dev/baddev.cc
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# dev/baddev.cc
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# dev/simconsole.cc
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# dev/disk_image.cc
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# dev/etherbus.cc
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# dev/etherbus.cc
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# dev/etherdump.cc
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# dev/etherdump.cc
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# dev/etherint.cc
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# dev/etherint.cc
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@ -213,16 +217,12 @@ full_system_sources = Split('''
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# dev/pcidev.cc
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# dev/pcidev.cc
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# dev/pcifake.cc
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# dev/pcifake.cc
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# dev/pktfifo.cc
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# dev/pktfifo.cc
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# dev/platform.cc
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# dev/sinic.cc
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# dev/sinic.cc
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# dev/simple_disk.cc
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# dev/tsunami.cc
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# dev/tsunami.cc
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# dev/tsunami_cchip.cc
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# dev/tsunami_cchip.cc
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# dev/isa_fake.cc
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# dev/isa_fake.cc
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# dev/tsunami_io.cc
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# dev/tsunami_io.cc
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# dev/tsunami_pchip.cc
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# dev/tsunami_pchip.cc
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# dev/uart.cc
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# dev/uart8250.cc
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if env['TARGET_ISA'] == 'alpha':
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if env['TARGET_ISA'] == 'alpha':
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full_system_sources += Split('''
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full_system_sources += Split('''
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@ -349,7 +349,6 @@ class IntegerOverflowFault : public AlphaFault
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class UnimpFault : public AlphaFault
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class UnimpFault : public AlphaFault
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{
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{
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#if FULL_SYSTEM
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private:
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private:
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std::string panicStr;
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std::string panicStr;
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static FaultName _name;
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static FaultName _name;
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@ -359,7 +358,7 @@ class UnimpFault : public AlphaFault
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UnimpFault(std::string _str)
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UnimpFault(std::string _str)
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: panicStr(_str)
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: panicStr(_str)
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{ }
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{ }
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#endif
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FaultName name() {return _name;}
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FaultName name() {return _name;}
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FaultVect vect() {return _vect;}
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FaultVect vect() {return _vect;}
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FaultStat & countStat() {return _count;}
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FaultStat & countStat() {return _count;}
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@ -53,7 +53,7 @@ using namespace AlphaISA;
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AlphaConsole::AlphaConsole(Params *p)
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AlphaConsole::AlphaConsole(Params *p)
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: BasicPioDevice(p), disk(p->disk),
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: BasicPioDevice(p), disk(p->disk),
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console(params()->cons), system(params()->sys), cpu(params()->cpu)
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console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
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{
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{
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pioSize = sizeof(struct AlphaAccess);
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pioSize = sizeof(struct AlphaAccess);
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@ -99,7 +99,6 @@ AlphaConsole::addressRanges(AddrRangeList &range_list)
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Tick
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Tick
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AlphaConsole::read(Packet &pkt)
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AlphaConsole::read(Packet &pkt)
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{
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{
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pkt.time = curTick + pioDelay;
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/** XXX Do we want to push the addr munging to a bus brige or something? So
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/** XXX Do we want to push the addr munging to a bus brige or something? So
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* the device has it's physical address and then the bridge adds on whatever
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* the device has it's physical address and then the bridge adds on whatever
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@ -108,6 +107,8 @@ AlphaConsole::read(Packet &pkt)
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assert(pkt.result == Unknown);
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = pkt.addr - pioAddr;
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uint32_t *data32;
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uint32_t *data32;
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@ -355,7 +356,8 @@ CREATE_SIM_OBJECT(AlphaConsole)
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p->pio_delay = pio_latency;
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p->pio_delay = pio_latency;
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p->cons = sim_console;
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p->cons = sim_console;
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p->disk = disk;
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p->disk = disk;
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p->sys = system;
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p->alpha_sys = system;
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p->system = system;
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p->cpu = cpu;
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p->cpu = cpu;
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return new AlphaConsole(p);
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return new AlphaConsole(p);
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}
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}
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@ -100,7 +100,7 @@ class AlphaConsole : public BasicPioDevice
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{
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{
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SimConsole *cons;
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SimConsole *cons;
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SimpleDisk *disk;
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SimpleDisk *disk;
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AlphaSystem *sys;
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AlphaSystem *alpha_sys;
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BaseCPU *cpu;
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BaseCPU *cpu;
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};
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};
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protected:
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protected:
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@ -37,6 +37,7 @@
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class Platform;
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class Platform;
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class PioDevice;
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class PioDevice;
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class DmaDevice;
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class DmaDevice;
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class System;
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/**
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/**
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* The PioPort class is a programmed i/o port that all devices that are
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* The PioPort class is a programmed i/o port that all devices that are
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@ -207,6 +208,7 @@ class PioDevice : public SimObject
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{
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{
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std::string name;
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std::string name;
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Platform *platform;
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Platform *platform;
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System *system;
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};
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};
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protected:
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protected:
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@ -49,7 +49,6 @@
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#include "dev/platform.hh"
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#include "dev/platform.hh"
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#include "dev/simconsole.hh"
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#include "dev/simconsole.hh"
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#include "dev/uart.hh"
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#include "dev/uart.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace std;
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@ -42,14 +42,14 @@
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "dev/disk_image.hh"
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#include "dev/disk_image.hh"
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#include "dev/simple_disk.hh"
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#include "dev/simple_disk.hh"
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#include "mem/functional/physical.hh"
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#include "mem/port.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace std;
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SimpleDisk::SimpleDisk(const string &name, PhysicalMemory *pmem,
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SimpleDisk::SimpleDisk(const string &name, System *sys, DiskImage *img)
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DiskImage *img)
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: SimObject(name), system(sys), image(img)
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: SimObject(name), physmem(pmem), image(img)
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{}
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{}
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SimpleDisk::~SimpleDisk()
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SimpleDisk::~SimpleDisk()
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@ -59,9 +59,7 @@ SimpleDisk::~SimpleDisk()
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void
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void
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SimpleDisk::read(Addr addr, baddr_t block, int count) const
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SimpleDisk::read(Addr addr, baddr_t block, int count) const
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{
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{
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uint8_t *data = physmem->dma_addr(addr, count);
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uint8_t *data = new uint8_t[SectorSize * count];
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if (!data)
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panic("dma out of range! read addr=%#x count=%d\n", addr, count);
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if (count & (SectorSize - 1))
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if (count & (SectorSize - 1))
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panic("Not reading a multiple of a sector (count = %d)", count);
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panic("Not reading a multiple of a sector (count = %d)", count);
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@ -69,8 +67,12 @@ SimpleDisk::read(Addr addr, baddr_t block, int count) const
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for (int i = 0, j = 0; i < count; i += SectorSize, j++)
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for (int i = 0, j = 0; i < count; i += SectorSize, j++)
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image->read(data + i, block + j);
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image->read(data + i, block + j);
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system->functionalPort.writeBlob(addr, data, count);
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DPRINTF(SimpleDisk, "read block=%#x len=%d\n", (uint64_t)block, count);
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DPRINTF(SimpleDisk, "read block=%#x len=%d\n", (uint64_t)block, count);
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DDUMP(SimpleDiskData, data, count);
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DDUMP(SimpleDiskData, data, count);
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delete data;
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}
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}
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void
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void
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
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SimObjectParam<PhysicalMemory *> physmem;
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SimObjectParam<System *> system;
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SimObjectParam<DiskImage *> disk;
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SimObjectParam<DiskImage *> disk;
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END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
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END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
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BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
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BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
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INIT_PARAM(physmem, "Physical Memory"),
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INIT_PARAM(system, "System pointer"),
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INIT_PARAM(disk, "Disk Image")
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INIT_PARAM(disk, "Disk Image")
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END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
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END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
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CREATE_SIM_OBJECT(SimpleDisk)
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CREATE_SIM_OBJECT(SimpleDisk)
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{
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{
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return new SimpleDisk(getInstanceName(), physmem, disk);
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return new SimpleDisk(getInstanceName(), system, disk);
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}
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}
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REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)
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REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)
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#include "arch/isa_traits.hh"
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#include "arch/isa_traits.hh"
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class DiskImage;
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class DiskImage;
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class PhysicalMemory;
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class System;
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/*
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/*
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* Trivial interface to a disk image used by the System Console
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* Trivial interface to a disk image used by the System Console
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typedef uint64_t baddr_t;
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typedef uint64_t baddr_t;
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protected:
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protected:
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PhysicalMemory *physmem;
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System *system;
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DiskImage *image;
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DiskImage *image;
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public:
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public:
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SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
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SimpleDisk(const std::string &name, System *sys, DiskImage *img);
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~SimpleDisk();
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~SimpleDisk();
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void read(Addr addr, baddr_t block, int count) const;
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void read(Addr addr, baddr_t block, int count) const;
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32
dev/uart.cc
32
dev/uart.cc
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@ -27,39 +27,19 @@
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*/
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*/
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/** @file
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/** @file
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* Implements a 8250 UART
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* Implements a base class for UARTs
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*/
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*/
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/simconsole.hh"
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#include "dev/simconsole.hh"
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#include "dev/uart.hh"
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#include "dev/uart.hh"
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#include "dev/platform.hh"
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#include "dev/platform.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace std;
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Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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Uart::Uart(Params *p)
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Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
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: BasicPioDevice(p), platform(p->platform), cons(p->cons)
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: PioDevice(name, p), addr(a), size(s), cons(c)
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{
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&Uart::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRate;
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}
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status = 0;
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status = 0;
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@ -68,11 +48,5 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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platform->uart = this;
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platform->uart = this;
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}
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}
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Tick
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Uart::cacheAccess(MemReqPtr &req)
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{
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return curTick + pioLatency;
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}
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DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
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DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
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26
dev/uart.hh
26
dev/uart.hh
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@ -37,30 +37,27 @@
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#include "dev/io_device.hh"
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#include "dev/io_device.hh"
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class SimConsole;
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class SimConsole;
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class MemoryController;
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class Platform;
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class Platform;
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const int RX_INT = 0x1;
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const int RX_INT = 0x1;
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const int TX_INT = 0x2;
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const int TX_INT = 0x2;
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class Uart : public PioDevice
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class Uart : public BasicPioDevice
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{
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{
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protected:
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protected:
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int status;
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int status;
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Addr addr;
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Platform *platform;
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Addr size;
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SimConsole *cons;
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SimConsole *cons;
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public:
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public:
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Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
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struct Params : public BasicPioDevice::Params
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Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
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{
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Platform *p);
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SimConsole *cons;
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};
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virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
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virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
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Uart(Params *p);
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/**
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/**
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* Inform the uart that there is data available.
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* Inform the uart that there is data available.
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|
@ -74,12 +71,9 @@ class Uart : public PioDevice
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*/
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*/
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bool intStatus() { return status ? true : false; }
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bool intStatus() { return status ? true : false; }
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/**
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protected:
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* Return how long this access will take.
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const Params *params() const {return (const Params *)_params; }
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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};
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#endif // __UART_HH__
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#endif // __UART_HH__
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120
dev/uart8250.cc
120
dev/uart8250.cc
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@ -40,10 +40,6 @@
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#include "dev/simconsole.hh"
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#include "dev/simconsole.hh"
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#include "dev/uart8250.hh"
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#include "dev/uart8250.hh"
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#include "dev/platform.hh"
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#include "dev/platform.hh"
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#include "mem/bus/bus.hh"
|
|
||||||
#include "mem/bus/pio_interface.hh"
|
|
||||||
#include "mem/bus/pio_interface_impl.hh"
|
|
||||||
#include "mem/functional/memory_control.hh"
|
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
@ -100,26 +96,35 @@ Uart8250::IntrEvent::scheduleIntr()
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
|
Uart8250::Uart8250(Params *p)
|
||||||
Addr a, Addr s, HierParams *hier, Bus *pio_bus,
|
: Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
|
||||||
Tick pio_latency, Platform *p)
|
|
||||||
: Uart(name, c, mmu, a, s, hier, pio_bus, pio_latency, p),
|
|
||||||
txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
|
|
||||||
{
|
{
|
||||||
|
pioSize = 8;
|
||||||
|
|
||||||
IER = 0;
|
IER = 0;
|
||||||
DLAB = 0;
|
DLAB = 0;
|
||||||
LCR = 0;
|
LCR = 0;
|
||||||
MCR = 0;
|
MCR = 0;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault
|
Tick
|
||||||
Uart8250::read(MemReqPtr &req, uint8_t *data)
|
Uart8250::read(Packet &pkt)
|
||||||
{
|
{
|
||||||
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
|
assert(pkt.result == Unknown);
|
||||||
|
assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
|
||||||
|
assert(pkt.size == 1);
|
||||||
|
|
||||||
|
pkt.time = curTick + pioDelay;
|
||||||
|
Addr daddr = pkt.addr - pioAddr;
|
||||||
|
uint8_t *data;
|
||||||
|
|
||||||
DPRINTF(Uart, " read register %#x\n", daddr);
|
DPRINTF(Uart, " read register %#x\n", daddr);
|
||||||
|
|
||||||
assert(req->size == 1);
|
if (!pkt.data) {
|
||||||
|
data = new uint8_t;
|
||||||
|
pkt.data = data;
|
||||||
|
} else
|
||||||
|
data = pkt.data;
|
||||||
|
|
||||||
switch (daddr) {
|
switch (daddr) {
|
||||||
case 0x0:
|
case 0x0:
|
||||||
|
@ -127,7 +132,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
|
||||||
if (cons->dataAvailable())
|
if (cons->dataAvailable())
|
||||||
cons->in(*data);
|
cons->in(*data);
|
||||||
else {
|
else {
|
||||||
*(uint8_t*)data = 0;
|
*data = 0;
|
||||||
// A limited amount of these are ok.
|
// A limited amount of these are ok.
|
||||||
DPRINTF(Uart, "empty read of RX register\n");
|
DPRINTF(Uart, "empty read of RX register\n");
|
||||||
}
|
}
|
||||||
|
@ -142,7 +147,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
|
||||||
break;
|
break;
|
||||||
case 0x1:
|
case 0x1:
|
||||||
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
||||||
*(uint8_t*)data = IER;
|
*data = IER;
|
||||||
} else { // DLM divisor latch MSB
|
} else { // DLM divisor latch MSB
|
||||||
;
|
;
|
||||||
}
|
}
|
||||||
|
@ -151,17 +156,17 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
|
||||||
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
|
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
|
||||||
|
|
||||||
if (status & RX_INT) /* Rx data interrupt has a higher priority */
|
if (status & RX_INT) /* Rx data interrupt has a higher priority */
|
||||||
*(uint8_t*)data = IIR_RXID;
|
*data = IIR_RXID;
|
||||||
else if (status & TX_INT)
|
else if (status & TX_INT)
|
||||||
*(uint8_t*)data = IIR_TXID;
|
*data = IIR_TXID;
|
||||||
else
|
else
|
||||||
*(uint8_t*)data = IIR_NOPEND;
|
*data = IIR_NOPEND;
|
||||||
|
|
||||||
//Tx interrupts are cleared on IIR reads
|
//Tx interrupts are cleared on IIR reads
|
||||||
status &= ~TX_INT;
|
status &= ~TX_INT;
|
||||||
break;
|
break;
|
||||||
case 0x3: // Line Control Register (LCR)
|
case 0x3: // Line Control Register (LCR)
|
||||||
*(uint8_t*)data = LCR;
|
*data = LCR;
|
||||||
break;
|
break;
|
||||||
case 0x4: // Modem Control Register (MCR)
|
case 0x4: // Modem Control Register (MCR)
|
||||||
break;
|
break;
|
||||||
|
@ -172,34 +177,41 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
|
||||||
if (cons->dataAvailable())
|
if (cons->dataAvailable())
|
||||||
lsr = UART_LSR_DR;
|
lsr = UART_LSR_DR;
|
||||||
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
|
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
|
||||||
*(uint8_t*)data = lsr;
|
*data = lsr;
|
||||||
break;
|
break;
|
||||||
case 0x6: // Modem Status Register (MSR)
|
case 0x6: // Modem Status Register (MSR)
|
||||||
*(uint8_t*)data = 0;
|
*data = 0;
|
||||||
break;
|
break;
|
||||||
case 0x7: // Scratch Register (SCR)
|
case 0x7: // Scratch Register (SCR)
|
||||||
*(uint8_t*)data = 0; // doesn't exist with at 8250.
|
*data = 0; // doesn't exist with at 8250.
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
panic("Tried to access a UART port that doesn't exist\n");
|
panic("Tried to access a UART port that doesn't exist\n");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
return NoFault;
|
return pioDelay;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault
|
Tick
|
||||||
Uart8250::write(MemReqPtr &req, const uint8_t *data)
|
Uart8250::write(Packet &pkt)
|
||||||
{
|
{
|
||||||
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
|
|
||||||
|
|
||||||
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
assert(pkt.result == Unknown);
|
||||||
|
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
|
||||||
|
assert(pkt.size == 1);
|
||||||
|
|
||||||
|
pkt.time = curTick + pioDelay;
|
||||||
|
Addr daddr = pkt.addr - pioAddr;
|
||||||
|
|
||||||
|
uint8_t *data = pkt.data;
|
||||||
|
|
||||||
|
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *data);
|
||||||
|
|
||||||
switch (daddr) {
|
switch (daddr) {
|
||||||
case 0x0:
|
case 0x0:
|
||||||
if (!(LCR & 0x80)) { // write byte
|
if (!(LCR & 0x80)) { // write byte
|
||||||
cons->out(*(uint8_t *)data);
|
cons->out(*data);
|
||||||
platform->clearConsoleInt();
|
platform->clearConsoleInt();
|
||||||
status &= ~TX_INT;
|
status &= ~TX_INT;
|
||||||
if (UART_IER_THRI & IER)
|
if (UART_IER_THRI & IER)
|
||||||
|
@ -210,7 +222,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
|
||||||
break;
|
break;
|
||||||
case 0x1:
|
case 0x1:
|
||||||
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
||||||
IER = *(uint8_t*)data;
|
IER = *data;
|
||||||
if (UART_IER_THRI & IER)
|
if (UART_IER_THRI & IER)
|
||||||
{
|
{
|
||||||
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
|
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
|
||||||
|
@ -244,10 +256,10 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
|
||||||
case 0x2: // FIFO Control Register (FCR)
|
case 0x2: // FIFO Control Register (FCR)
|
||||||
break;
|
break;
|
||||||
case 0x3: // Line Control Register (LCR)
|
case 0x3: // Line Control Register (LCR)
|
||||||
LCR = *(uint8_t*)data;
|
LCR = *data;
|
||||||
break;
|
break;
|
||||||
case 0x4: // Modem Control Register (MCR)
|
case 0x4: // Modem Control Register (MCR)
|
||||||
if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
|
if (*data == (UART_MCR_LOOP | 0x0A))
|
||||||
MCR = 0x9A;
|
MCR = 0x9A;
|
||||||
break;
|
break;
|
||||||
case 0x7: // Scratch Register (SCR)
|
case 0x7: // Scratch Register (SCR)
|
||||||
|
@ -257,7 +269,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
|
||||||
panic("Tried to access a UART port that doesn't exist\n");
|
panic("Tried to access a UART port that doesn't exist\n");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
return NoFault;
|
return pioDelay;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -272,6 +284,14 @@ Uart8250::dataAvailable()
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
Uart8250::addressRanges(AddrRangeList &range_list)
|
||||||
|
{
|
||||||
|
assert(pioSize != 0);
|
||||||
|
range_list.clear();
|
||||||
|
range_list.push_back(RangeSize(pioAddr, pioSize));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -316,35 +336,35 @@ Uart8250::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
|
||||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
SimObjectParam<SimConsole *> console;
|
|
||||||
SimObjectParam<MemoryController *> mmu;
|
|
||||||
SimObjectParam<Platform *> platform;
|
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
Param<Addr> size;
|
|
||||||
SimObjectParam<Bus*> pio_bus;
|
|
||||||
Param<Tick> pio_latency;
|
Param<Tick> pio_latency;
|
||||||
SimObjectParam<HierParams *> hier;
|
SimObjectParam<Platform *> platform;
|
||||||
|
SimObjectParam<SimConsole *> sim_console;
|
||||||
|
SimObjectParam<System *> system;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
INIT_PARAM(console, "The console"),
|
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
|
||||||
INIT_PARAM(platform, "Pointer to platfrom"),
|
|
||||||
INIT_PARAM(addr, "Device Address"),
|
INIT_PARAM(addr, "Device Address"),
|
||||||
INIT_PARAM_DFLT(size, "Device size", 0x8),
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
|
||||||
INIT_PARAM(pio_bus, ""),
|
INIT_PARAM(platform, "platform"),
|
||||||
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
INIT_PARAM(sim_console, "The Simulator Console"),
|
||||||
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
INIT_PARAM(system, "system object")
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
END_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(Uart8250)
|
CREATE_SIM_OBJECT(Uart8250)
|
||||||
{
|
{
|
||||||
return new Uart8250(getInstanceName(), console, mmu, addr, size, hier,
|
Uart8250::Params *p = new Uart8250::Params;
|
||||||
pio_bus, pio_latency, platform);
|
p->name = getInstanceName();
|
||||||
|
p->pio_addr = addr;
|
||||||
|
p->pio_delay = pio_latency;
|
||||||
|
p->platform = platform;
|
||||||
|
p->cons = sim_console;
|
||||||
|
p->system = system;
|
||||||
|
return new Uart8250(p);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("Uart8250", Uart8250)
|
REGISTER_SIM_OBJECT("Uart8250", Uart8250)
|
||||||
|
|
||||||
|
|
|
@ -30,8 +30,8 @@
|
||||||
* Defines a 8250 UART
|
* Defines a 8250 UART
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __TSUNAMI_UART_HH__
|
#ifndef __DEV_UART8250_HH__
|
||||||
#define __TSUNAMI_UART_HH__
|
#define __DEV_UART8250_HH__
|
||||||
|
|
||||||
#include "dev/tsunamireg.h"
|
#include "dev/tsunamireg.h"
|
||||||
#include "base/range.hh"
|
#include "base/range.hh"
|
||||||
|
@ -53,7 +53,6 @@
|
||||||
#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
|
#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
|
||||||
|
|
||||||
class SimConsole;
|
class SimConsole;
|
||||||
class MemoryController;
|
|
||||||
class Platform;
|
class Platform;
|
||||||
|
|
||||||
class Uart8250 : public Uart
|
class Uart8250 : public Uart
|
||||||
|
@ -79,12 +78,11 @@ class Uart8250 : public Uart
|
||||||
IntrEvent rxIntrEvent;
|
IntrEvent rxIntrEvent;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
|
Uart8250(Params *p);
|
||||||
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
|
|
||||||
Platform *p);
|
|
||||||
|
|
||||||
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
virtual Tick read(Packet &pkt);
|
||||||
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
virtual Tick write(Packet &pkt);
|
||||||
|
virtual void addressRanges(AddrRangeList &range_list);
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -120,7 +120,7 @@ class Bus : public MemObject
|
||||||
// downstream from this bus, yes? That is, the union of all
|
// downstream from this bus, yes? That is, the union of all
|
||||||
// the 'owned' address ranges of all the other interfaces on
|
// the 'owned' address ranges of all the other interfaces on
|
||||||
// this bus...
|
// this bus...
|
||||||
virtual void addressRanges(AddrRangeList &range_list, bool &owner);
|
virtual void addressRanges(AddrRangeList &resp, AddrRangeList &snoop);
|
||||||
|
|
||||||
// Hack to make translating port work without changes
|
// Hack to make translating port work without changes
|
||||||
virtual int deviceBlockSize() { return 32; }
|
virtual int deviceBlockSize() { return 32; }
|
||||||
|
|
|
@ -184,18 +184,18 @@ PhysicalMemory::MemoryPort::recvStatusChange(Port::Status status)
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
|
PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp,
|
||||||
bool &owner)
|
AddrRangeList &snoop)
|
||||||
{
|
{
|
||||||
memory->getAddressRanges(range_list, owner);
|
memory->getAddressRanges(resp, snoop);
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
PhysicalMemory::getAddressRanges(AddrRangeList &range_list, bool &owner)
|
PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
|
||||||
{
|
{
|
||||||
owner = true;
|
snoop.clear();
|
||||||
range_list.clear();
|
resp.clear();
|
||||||
range_list.push_back(RangeSize(base_addr, pmem_size));
|
resp.push_back(RangeSize(base_addr, pmem_size));
|
||||||
}
|
}
|
||||||
|
|
||||||
int
|
int
|
||||||
|
|
|
@ -2,4 +2,4 @@ from m5 import *
|
||||||
class SimpleDisk(SimObject):
|
class SimpleDisk(SimObject):
|
||||||
type = 'SimpleDisk'
|
type = 'SimpleDisk'
|
||||||
disk = Param.DiskImage("Disk Image")
|
disk = Param.DiskImage("Disk Image")
|
||||||
physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
|
system = Param.System(Parent.any, "Sysetm Pointer")
|
||||||
|
|
|
@ -39,7 +39,7 @@
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
#include "cpu/exec_context.hh"
|
#include "cpu/exec_context.hh"
|
||||||
#include "mem/page_table.hh"
|
#include "mem/page_table.hh"
|
||||||
#include "mem/mem_object.hh"
|
#include "mem/physical.hh"
|
||||||
#include "mem/translating_port.hh"
|
#include "mem/translating_port.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "sim/process.hh"
|
#include "sim/process.hh"
|
||||||
|
|
|
@ -4,6 +4,7 @@
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "cpu/exec_context.hh"
|
#include "cpu/exec_context.hh"
|
||||||
#include "mem/mem_object.hh"
|
#include "mem/mem_object.hh"
|
||||||
|
#include "mem/physical.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "sim/byteswap.hh"
|
#include "sim/byteswap.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
@ -11,7 +12,6 @@
|
||||||
#include "arch/vtophys.hh"
|
#include "arch/vtophys.hh"
|
||||||
#include "base/remote_gdb.hh"
|
#include "base/remote_gdb.hh"
|
||||||
#include "kern/kernel_stats.hh"
|
#include "kern/kernel_stats.hh"
|
||||||
#include "mem/physical.hh"
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
@ -242,7 +242,7 @@ DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
|
||||||
|
|
||||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
|
||||||
|
|
||||||
SimObjectParam<MemObject *> physmem;
|
SimObjectParam<PhysicalMemory *> physmem;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(System)
|
END_DECLARE_SIM_OBJECT_PARAMS(System)
|
||||||
|
|
||||||
|
|
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Reference in a new issue