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added unimp faults

Browse source 
update for newmem

arch/mips/faults.cc:
arch/mips/faults.hh:
arch/sparc/faults.cc:
arch/sparc/faults.hh:
    added unimp faults for mips
arch/mips/isa/base.isa:
arch/mips/isa/includes.isa:
    thou shalt not put includes inside a namespace
dev/alpha_console.cc:
    fix formatting
dev/io_device.hh:
    add comments
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
    update for newmem
sim/process.cc:
    fix seemingly wronge code.

--HG--
extra : convert_revision : 9dcfe188d00d525b935d8ef4fa323280bbfa9a0e
This commit is contained in:
Ali Saidi 2006-04-06 18:04:49 -04:00
parent 6240f8c4bc
commit 61b2bd9d28
11 changed files with 163 additions and 120 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
arch/mips/faults.cc
View file

@ -98,6 +98,10 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
FaultName UnimpFault::_name = "Unimplemented Simulator feature";
FaultVect UnimpFault::_vect = 0x0001;
FaultStat UnimpFault::_count;
#if FULL_SYSTEM
void MipsFault::invoke(ExecContext * xc)
@ -125,6 +129,12 @@ void ArithmeticFault::invoke(ExecContext * xc)
panic("Arithmetic traps are unimplemented!");
}
void UnimpFault::invoke(ExecContext * xc)
{
FaultBase::invoke(xc);
panic("Unimpfault: %s\n", panicStr.c_str());
}
#endif
} // namespace MipsISA

20
arch/mips/faults.hh
View file

@ -264,6 +264,26 @@ class IntegerOverflowFault : public MipsFault
FaultStat & countStat() {return _count;}
};
class UnimpFault : public MipsFault
{
private:
std::string panicStr;
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
UnimpFault(std::string _str)
: panicStr(_str)
{ }
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if FULL_SYSTEM
void invoke(ExecContext * xc);
#endif
};
} // MipsISA namespace
#endif // __FAULTS_HH__

2
arch/mips/isa/base.isa
View file

@ -9,8 +9,6 @@
output header {{
#define R31 31
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
using namespace MipsISA;

3
arch/mips/isa/includes.isa
View file

@ -17,6 +17,8 @@ output decoder {{
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include <math.h>
#if defined(linux)
@ -27,6 +29,7 @@ using namespace MipsISA;
}};
output exec {{
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include <math.h>
#if defined(linux)

11
arch/sparc/faults.cc
View file

@ -215,7 +215,10 @@ TrapType TrapInstruction::_baseTrapType = 0x100;
FaultPriority TrapInstruction::_priority = 16;
FaultStat TrapInstruction::_count;
FaultName UnimpFault::_name = "Unimplemented Simulator feature";
TrapType UnimpFault::_trapType = 0x000;
FaultPriority UnimpFault::_priority = 0;
FaultStat UnimpFault::_count;
#if FULL_SYSTEM
@ -242,6 +245,12 @@ void SparcFault::invoke(ExecContext * xc)
xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
}
void UnimpFault::invoke(ExecContext * xc)
{
panic("Unimpfault: %s\n", panicStr.c_str());
}
#endif
} // namespace SparcISA

23
arch/sparc/faults.hh
View file

@ -582,6 +582,29 @@ class TrapInstruction : public EnumeratedFault
FaultStat & countStat() {return _count;}
};
class UnimpFault : public SparcFault
{
private:
static FaultName _name;
static TrapType _trapType;
static FaultPriority _priority;
static FaultStat _count;
std::string panicStr;
public:
UnimpFault(std::string _str)
: panicStr(_str)
{ }
FaultName name() {return _name;}
TrapType trapType() {return _trapType;}
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
#if FULL_SYSTEM
void invoke(ExecContext * xc);
#endif
};
} // SparcISA namespace
#endif // __FAULTS_HH__

6
dev/alpha_console.cc
View file

@ -120,8 +120,7 @@ AlphaConsole::read(Packet &pkt)
if (!pkt.data) {
data32 = new uint32_t;
pkt.data = (uint8_t*)data32;
}
else
} else
data32 = (uint32_t*)pkt.data;
switch (daddr)
@ -150,8 +149,7 @@ AlphaConsole::read(Packet &pkt)
if (!pkt.data) {
data64 = new uint64_t;
pkt.data = (uint8_t*)data64;
}
else
} else
data64 = (uint64_t*)pkt.data;
switch (daddr)
{

10
dev/io_device.hh
View file

@ -192,11 +192,17 @@ class PioDevice : public SimObject
{ return pkt.cmd == Read ? this->read(pkt) : this->write(pkt); }
/** Pure virtual function that the device must implement. Called when a read
* command is recieved by the port. */
* command is recieved by the port.
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
virtual Tick read(Packet &pkt) = 0;
/** Pure virtual function that the device must implement. Called when a
* write command is recieved by the port. */
* write command is recieved by the port.
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
virtual Tick write(Packet &pkt) = 0;
public:

144
dev/tsunami_cchip.cc
View file

@ -39,10 +39,7 @@
#include "dev/tsunami_cchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "mem/port.hh"
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
@ -52,19 +49,10 @@ using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
Bus* pio_bus, Tick pio_latency)
: PioDevice(name, t), addr(a), tsunami(t)
TsunamiCChip::TsunamiCChip(Params *p)
: BasicPioDevice(p), tsunami(p->tsunami)
{
mmu->add_child(this, RangeSize(addr, size));
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&TsunamiCChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * pio_bus->clockRate;
}
pioSize = 0xfffffff;
drir = 0;
ipint = 0;
@ -80,123 +68,137 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
tsunami->cchip = this;
}
Fault
TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
Tick
TsunamiCChip::read(Packet &pkt)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
assert(pkt.result == Unknown);
assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
ExecContext *xc = req->xc;
pkt.time = curTick + pioDelay;
Addr regnum = (req->paddr - pioAddr) >> 6;
Addr daddr = (req->paddr - pioAddr);
switch (req->size) {
uint32_t *data32;
uint64_t *data64;
switch (pkt.size) {
case sizeof(uint64_t):
if (!pkt.data) {
data64 = new uint64_t;
pkt.data = (uint8_t*)data64;
} else
data64 = (uint64_t*)pkt.data;
if (daddr & TSDEV_CC_BDIMS)
{
*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
return NoFault;
*data64 = dim[(daddr >> 4) & 0x3F];
break;
}
if (daddr & TSDEV_CC_BDIRS)
{
*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
return NoFault;
*data64 = dir[(daddr >> 4) & 0x3F];
break;
}
switch(regnum) {
case TSDEV_CC_CSR:
*(uint64_t*)data = 0x0;
return NoFault;
*data64 = 0x0;
break;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR not implemeted\n");
return NoFault;
break;
case TSDEV_CC_MISC:
*(uint64_t*)data = (ipint << 8) & 0xF |
(itint << 4) & 0xF |
(xc->readCpuId() & 0x3);
return NoFault;
*data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
(pkt.req->cpuId & 0x3);
break;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
*(uint64_t*)data = 0;
return NoFault;
*data64 = 0;
break;
case TSDEV_CC_DIM0:
*(uint64_t*)data = dim[0];
return NoFault;
*data64 = dim[0];
break;
case TSDEV_CC_DIM1:
*(uint64_t*)data = dim[1];
return NoFault;
*data64 = dim[1];
break;
case TSDEV_CC_DIM2:
*(uint64_t*)data = dim[2];
return NoFault;
*data64 = dim[2];
break;
case TSDEV_CC_DIM3:
*(uint64_t*)data = dim[3];
return NoFault;
*data64 = dim[3];
break;
case TSDEV_CC_DIR0:
*(uint64_t*)data = dir[0];
return NoFault;
*data64 = dir[0];
break;
case TSDEV_CC_DIR1:
*(uint64_t*)data = dir[1];
return NoFault;
*data64 = dir[1];
break;
case TSDEV_CC_DIR2:
*(uint64_t*)data = dir[2];
return NoFault;
*data64 = dir[2];
break;
case TSDEV_CC_DIR3:
*(uint64_t*)data = dir[3];
return NoFault;
*data64 = dir[3];
break;
case TSDEV_CC_DRIR:
*(uint64_t*)data = drir;
return NoFault;
*data64 = drir;
break;
case TSDEV_CC_PRBEN:
panic("TSDEV_CC_PRBEN not implemented\n");
return NoFault;
break;
case TSDEV_CC_IIC0:
case TSDEV_CC_IIC1:
case TSDEV_CC_IIC2:
case TSDEV_CC_IIC3:
panic("TSDEV_CC_IICx not implemented\n");
return NoFault;
break;
case TSDEV_CC_MPR0:
case TSDEV_CC_MPR1:
case TSDEV_CC_MPR2:
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx not implemented\n");
return NoFault;
break;
case TSDEV_CC_IPIR:
*(uint64_t*)data = ipint;
return NoFault;
*data64 = ipint;
break;
case TSDEV_CC_ITIR:
*(uint64_t*)data = itint;
return NoFault;
*data64 = itint;
break;
default:
panic("default in cchip read reached, accessing 0x%x\n");
} // uint64_t
break;
case sizeof(uint32_t):
if (regnum == TSDEV_CC_DRIR) {
warn("accessing DRIR with 32 bit read, "
"hopefully your just reading this for timing");
*(uint32_t*)data = drir;
} else
panic("invalid access size(?) for tsunami register!\n");
return NoFault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!\n");
}
DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
DPRINTFN("Tsunami CChip: read regnum=%#x size=%d data=%lld\n", regnum,
req->size, *data);
return NoFault;
pkt.result = Success;
return pioDelay;
}
Fault
TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
Tick
TsunamiCChip::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
Addr daddr = pkt.addr - pioAddr;
uint64_t val = *(uint64_t *)pkt.data;
assert(pkt.size == sizeof(uint64_t));
DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
req->vaddr, *(uint64_t*)data, req->size);

52
dev/tsunami_cchip.hh
View file

@ -37,21 +37,13 @@
#include "base/range.hh"
#include "dev/io_device.hh"
class MemoryController;
/**
* Tsunami CChip CSR Emulation. This device includes all the interrupt
* handling code for the chipset.
*/
class TsunamiCChip : public PioDevice
class TsunamiCChip : public BasicPioDevice
{
private:
/** The base address of this device */
Addr addr;
/** The size of mappad from the above address */
static const Addr size = 0xfffffff;
protected:
/**
* pointer to the tsunami object.
@ -84,37 +76,25 @@ class TsunamiCChip : public PioDevice
/** Indicator of which CPUs have an RTC interrupt */
uint64_t itint;
public:
struct Params : public BasicPioDevice::Params
{
Tsunami *tsunami;
};
protected:
const Params *params() const {return (const Params *)_params; }
public:
/**
* Initialize the Tsunami CChip by setting all of the
* device register to 0.
* @param name name of this device.
* @param t pointer back to the Tsunami object that we belong to.
* @param a address we are mapped at.
* @param mmu pointer to the memory controller that sends us events.
* @param hier object to store parameters universal the device hierarchy
* @param bus The bus that this device is attached to
* @param p params struct
*/
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier, Bus *pio_bus,
Tick pio_latency);
TsunamiCChip(Params *p);
/**
* Process a read to the CChip.
* @param req Contains the address to read from.
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Tick read(Packet &pkt);
/**
* Process a write to the CChip.
* @param req Contains the address to write to.
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Tick write(Packet &pkt);
/**
* post an RTC interrupt to the CPU
@ -165,12 +145,6 @@ class TsunamiCChip : public PioDevice
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_CCHIP_HH__

2
sim/process.cc
View file

@ -316,7 +316,7 @@ LiveProcess::argsInit(int intSize, int pageSize)
roundUp(stack_size, pageSize));
// map out initial stack contents
Addr argv_array_base = stack_min + sizeof(uint64_t); // room for argc
Addr argv_array_base = stack_min + intSize; // room for argc
Addr envp_array_base = argv_array_base + argv_array_size;
Addr arg_data_base = envp_array_base + envp_array_size;
Addr env_data_base = arg_data_base + arg_data_size;