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mem: update DDR3 die revision

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Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
This commit is contained in:
Omar Naji 2016-10-13 19:22:10 +01:00
parent d19dc35b06
commit 61b2b493d4
1 changed files with 8 additions and 8 deletions
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16
src/mem/DRAMCtrl.py
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@ -1,4 +1,4 @@
# Copyright (c) 2012-2014 ARM Limited # Copyright (c) 2012-2016 ARM Limited
# All rights reserved. # All rights reserved.
# #
# The license below extends only to copyright in the software and shall # The license below extends only to copyright in the software and shall
@ -376,13 +376,13 @@ class DDR3_1600_x64(DRAMCtrl):
# self refresh exit time # self refresh exit time
tXS = '270ns' tXS = '270ns'
# Current values from datasheet # Current values from datasheet Die Rev E,J
IDD0 = '75mA' IDD0 = '55mA'
IDD2N = '50mA' IDD2N = '32mA'
IDD3N = '57mA' IDD3N = '38mA'
IDD4W = '165mA' IDD4W = '125mA'
IDD4R = '187mA' IDD4R = '157mA'
IDD5 = '220mA' IDD5 = '235mA'
VDD = '1.5V' VDD = '1.5V'
# A single HMC-2500 x32 model based on: # A single HMC-2500 x32 model based on: