mem: update DDR3 die revision
Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
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1 changed files with 8 additions and 8 deletions
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@ -1,4 +1,4 @@
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# Copyright (c) 2012-2014 ARM Limited
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# Copyright (c) 2012-2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -376,13 +376,13 @@ class DDR3_1600_x64(DRAMCtrl):
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# self refresh exit time
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tXS = '270ns'
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# Current values from datasheet
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IDD0 = '75mA'
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IDD2N = '50mA'
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IDD3N = '57mA'
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IDD4W = '165mA'
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IDD4R = '187mA'
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IDD5 = '220mA'
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# Current values from datasheet Die Rev E,J
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IDD0 = '55mA'
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IDD2N = '32mA'
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IDD3N = '38mA'
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IDD4W = '125mA'
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IDD4R = '157mA'
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IDD5 = '235mA'
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VDD = '1.5V'
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# A single HMC-2500 x32 model based on:
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