inorder: mem. mgmt. update
update address List and address Map to take into account multiple threads
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parent
4dbc2f1718
commit
611a8642c2
2 changed files with 13 additions and 9 deletions
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@ -131,6 +131,8 @@ CacheUnit::init()
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int
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CacheUnit::getSlot(DynInstPtr inst)
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{
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ThreadID tid = inst->readTid();
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if (tlbBlocked[inst->threadNumber]) {
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return -1;
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}
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@ -142,7 +144,7 @@ CacheUnit::getSlot(DynInstPtr inst)
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Addr req_addr = inst->getMemAddr();
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if (resName == "icache_port" ||
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find(addrList.begin(), addrList.end(), req_addr) == addrList.end()) {
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find(addrList[tid].begin(), addrList[tid].end(), req_addr) == addrList[tid].end()) {
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int new_slot = Resource::getSlot(inst);
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@ -150,8 +152,8 @@ CacheUnit::getSlot(DynInstPtr inst)
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return -1;
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inst->memTime = curTick;
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addrList.push_back(req_addr);
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addrMap[req_addr] = inst->seqNum;
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addrList[tid].push_back(req_addr);
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addrMap[tid][req_addr] = inst->seqNum;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
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inst->readTid(), inst->seqNum, req_addr);
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@ -160,7 +162,7 @@ CacheUnit::getSlot(DynInstPtr inst)
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DPRINTF(InOrderCachePort,
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"[tid:%i] Denying request because there is an outstanding"
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" request to/for addr. %08p. by [sn:%i] @ tick %i\n",
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inst->readTid(), req_addr, addrMap[req_addr], inst->memTime);
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inst->readTid(), req_addr, addrMap[tid][req_addr], inst->memTime);
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return -1;
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}
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}
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@ -168,15 +170,17 @@ CacheUnit::getSlot(DynInstPtr inst)
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void
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CacheUnit::freeSlot(int slot_num)
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{
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vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(),
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ThreadID tid = reqMap[slot_num]->inst->readTid();
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vector<Addr>::iterator vect_it = find(addrList[tid].begin(), addrList[tid].end(),
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reqMap[slot_num]->inst->getMemAddr());
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assert(vect_it != addrList.end());
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assert(vect_it != addrList[tid].end());
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Address %08p removed from dependency list\n",
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reqMap[slot_num]->inst->readTid(), (*vect_it));
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addrList.erase(vect_it);
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addrList[tid].erase(vect_it);
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Resource::freeSlot(slot_num);
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}
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@ -198,9 +198,9 @@ class CacheUnit : public Resource
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bool cacheBlocked;
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std::vector<Addr> addrList;
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std::vector<Addr> addrList[ThePipeline::MaxThreads];
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std::map<Addr, InstSeqNum> addrMap;
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std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
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public:
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int cacheBlkSize;
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