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inorder: mem. mgmt. update

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update address List and address Map to take
into account multiple threads
This commit is contained in:
Korey Sewell 2010-01-31 18:27:12 -05:00
parent 4dbc2f1718
commit 611a8642c2
2 changed files with 13 additions and 9 deletions
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18
src/cpu/inorder/resources/cache_unit.cc
View file

@ -131,6 +131,8 @@ CacheUnit::init()
int int
CacheUnit::getSlot(DynInstPtr inst) CacheUnit::getSlot(DynInstPtr inst)
{ {
ThreadID tid = inst->readTid();
if (tlbBlocked[inst->threadNumber]) { if (tlbBlocked[inst->threadNumber]) {
return -1; return -1;
} }
@ -142,7 +144,7 @@ CacheUnit::getSlot(DynInstPtr inst)
Addr req_addr = inst->getMemAddr(); Addr req_addr = inst->getMemAddr();
if (resName == "icache_port" || if (resName == "icache_port" ||
find(addrList.begin(), addrList.end(), req_addr) == addrList.end()) { find(addrList[tid].begin(), addrList[tid].end(), req_addr) == addrList[tid].end()) {
int new_slot = Resource::getSlot(inst); int new_slot = Resource::getSlot(inst);
@ -150,8 +152,8 @@ CacheUnit::getSlot(DynInstPtr inst)
return -1; return -1;
inst->memTime = curTick; inst->memTime = curTick;
addrList.push_back(req_addr); addrList[tid].push_back(req_addr);
addrMap[req_addr] = inst->seqNum; addrMap[tid][req_addr] = inst->seqNum;
DPRINTF(InOrderCachePort, DPRINTF(InOrderCachePort,
"[tid:%i]: [sn:%i]: Address %08p added to dependency list\n", "[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
inst->readTid(), inst->seqNum, req_addr); inst->readTid(), inst->seqNum, req_addr);
@ -160,7 +162,7 @@ CacheUnit::getSlot(DynInstPtr inst)
DPRINTF(InOrderCachePort, DPRINTF(InOrderCachePort,
"[tid:%i] Denying request because there is an outstanding" "[tid:%i] Denying request because there is an outstanding"
" request to/for addr. %08p. by [sn:%i] @ tick %i\n", " request to/for addr. %08p. by [sn:%i] @ tick %i\n",
inst->readTid(), req_addr, addrMap[req_addr], inst->memTime); inst->readTid(), req_addr, addrMap[tid][req_addr], inst->memTime);
return -1; return -1;
} }
} }
@ -168,15 +170,17 @@ CacheUnit::getSlot(DynInstPtr inst)
void void
CacheUnit::freeSlot(int slot_num) CacheUnit::freeSlot(int slot_num)
{ {
vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(), ThreadID tid = reqMap[slot_num]->inst->readTid();
vector<Addr>::iterator vect_it = find(addrList[tid].begin(), addrList[tid].end(),
reqMap[slot_num]->inst->getMemAddr()); reqMap[slot_num]->inst->getMemAddr());
assert(vect_it != addrList.end()); assert(vect_it != addrList[tid].end());
DPRINTF(InOrderCachePort, DPRINTF(InOrderCachePort,
"[tid:%i]: Address %08p removed from dependency list\n", "[tid:%i]: Address %08p removed from dependency list\n",
reqMap[slot_num]->inst->readTid(), (*vect_it)); reqMap[slot_num]->inst->readTid(), (*vect_it));
addrList.erase(vect_it); addrList[tid].erase(vect_it);
Resource::freeSlot(slot_num); Resource::freeSlot(slot_num);
} }

4
src/cpu/inorder/resources/cache_unit.hh
View file

@ -198,9 +198,9 @@ class CacheUnit : public Resource
bool cacheBlocked; bool cacheBlocked;
std::vector<Addr> addrList; std::vector<Addr> addrList[ThePipeline::MaxThreads];
std::map<Addr, InstSeqNum> addrMap; std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
public: public:
int cacheBlkSize; int cacheBlkSize;