ARM: Implement the vstr instruction.
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f64c8bafd2
commit
6106bd18cd
1 changed files with 35 additions and 11 deletions
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@ -78,7 +78,8 @@ let {{
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exec_output += newExec
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exec_output += newExec
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def buildImmStore(mnem, post, add, writeback, \
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def buildImmStore(mnem, post, add, writeback, \
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size=4, sign=False, user=False, strex=False):
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size=4, sign=False, user=False, \
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strex=False, vstr=False):
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name = mnem
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name = mnem
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Name = storeImmClassName(post, add, writeback, \
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Name = storeImmClassName(post, add, writeback, \
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size, sign, user)
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size, sign, user)
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@ -94,8 +95,14 @@ let {{
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eaCode += offset
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eaCode += offset
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eaCode += ";"
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eaCode += ";"
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accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
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if vstr:
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{ "suffix" : buildMemSuffix(sign, size) }
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accCode = '''
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Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);
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''' % { "suffix" : buildMemSuffix(sign, size) }
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else:
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accCode = '''
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Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);
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''' % { "suffix" : buildMemSuffix(sign, size) }
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if writeback:
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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accCode += "Base = Base %s;\n" % offset
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@ -107,7 +114,10 @@ let {{
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postAccCode = "Result = !writeResult;"
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postAccCode = "Result = !writeResult;"
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execTemplateBase = 'StoreEx'
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execTemplateBase = 'StoreEx'
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else:
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else:
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memFlags.append("ArmISA::TLB::AllowUnaligned")
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if vstr:
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Name = "%s_%s" % (mnem.upper(), Name)
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else:
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memFlags.append("ArmISA::TLB::AllowUnaligned")
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base = buildMemBase("MemoryImm", post, writeback)
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base = buildMemBase("MemoryImm", post, writeback)
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postAccCode = ""
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postAccCode = ""
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execTemplateBase = 'Store'
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execTemplateBase = 'Store'
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@ -179,7 +189,8 @@ let {{
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"ArmISA::TLB::AllowUnaligned", \
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"ArmISA::TLB::AllowUnaligned", \
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"%d" % (size - 1)], [], base)
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"%d" % (size - 1)], [], base)
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def buildDoubleImmStore(mnem, post, add, writeback, strex=False):
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def buildDoubleImmStore(mnem, post, add, writeback, \
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strex=False, vstr=False):
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name = mnem
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name = mnem
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Name = storeDoubleImmClassName(post, add, writeback)
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Name = storeDoubleImmClassName(post, add, writeback)
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@ -194,11 +205,18 @@ let {{
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eaCode += offset
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eaCode += offset
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eaCode += ";"
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eaCode += ";"
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accCode = '''
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if vstr:
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CPSR cpsr = Cpsr;
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accCode = '''
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Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
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uint64_t swappedMem = (uint64_t)FpDest.uw |
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((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
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((uint64_t)FpDest2.uw << 32);
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'''
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Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
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'''
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else:
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accCode = '''
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CPSR cpsr = Cpsr;
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Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
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((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
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'''
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if writeback:
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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accCode += "Base = Base %s;\n" % offset
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@ -206,12 +224,13 @@ let {{
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"ArmISA::TLB::AlignWord"]
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"ArmISA::TLB::AlignWord"]
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if strex:
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if strex:
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memFlags.append("Request::LLSC")
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memFlags.append("Request::LLSC")
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Name = "%s_%s" % (mnem.upper(), Name)
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base = buildMemBase("MemoryExDImm", post, writeback)
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base = buildMemBase("MemoryExDImm", post, writeback)
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postAccCode = "Result = !writeResult;"
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postAccCode = "Result = !writeResult;"
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else:
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else:
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base = buildMemBase("MemoryDImm", post, writeback)
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base = buildMemBase("MemoryDImm", post, writeback)
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postAccCode = ""
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postAccCode = ""
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if vstr or strex:
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Name = "%s_%s" % (mnem.upper(), Name)
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emitStore(name, Name, True, eaCode, accCode, postAccCode, \
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emitStore(name, Name, True, eaCode, accCode, postAccCode, \
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memFlags, [], base, double=True, strex=strex)
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memFlags, [], base, double=True, strex=strex)
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@ -300,4 +319,9 @@ let {{
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buildImmStore("strexh", False, True, False, size=2, strex=True)
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buildImmStore("strexh", False, True, False, size=2, strex=True)
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buildImmStore("strexb", False, True, False, size=1, strex=True)
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buildImmStore("strexb", False, True, False, size=1, strex=True)
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buildDoubleImmStore("strexd", False, True, False, strex=True)
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buildDoubleImmStore("strexd", False, True, False, strex=True)
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buildImmStore("vstr", False, True, False, size=4, vstr=True)
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buildImmStore("vstr", False, False, False, size=4, vstr=True)
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buildDoubleImmStore("vstr", False, True, False, vstr=True)
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buildDoubleImmStore("vstr", False, False, False, vstr=True)
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}};
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}};
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