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ARM: Implement the vstr instruction.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:12 -05:00
parent f64c8bafd2
commit 6106bd18cd
1 changed files with 35 additions and 11 deletions
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34
src/arch/arm/isa/insts/str.isa
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@ -78,7 +78,8 @@ let {{
exec_output += newExec exec_output += newExec
def buildImmStore(mnem, post, add, writeback, \ def buildImmStore(mnem, post, add, writeback, \
size=4, sign=False, user=False, strex=False): size=4, sign=False, user=False, \
strex=False, vstr=False):
name = mnem name = mnem
Name = storeImmClassName(post, add, writeback, \ Name = storeImmClassName(post, add, writeback, \
size, sign, user) size, sign, user)
@ -94,8 +95,14 @@ let {{
eaCode += offset eaCode += offset
eaCode += ";" eaCode += ";"
accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ if vstr:
{ "suffix" : buildMemSuffix(sign, size) } accCode = '''
Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);
''' % { "suffix" : buildMemSuffix(sign, size) }
else:
accCode = '''
Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);
''' % { "suffix" : buildMemSuffix(sign, size) }
if writeback: if writeback:
accCode += "Base = Base %s;\n" % offset accCode += "Base = Base %s;\n" % offset
@ -106,6 +113,9 @@ let {{
base = buildMemBase("MemoryExImm", post, writeback) base = buildMemBase("MemoryExImm", post, writeback)
postAccCode = "Result = !writeResult;" postAccCode = "Result = !writeResult;"
execTemplateBase = 'StoreEx' execTemplateBase = 'StoreEx'
else:
if vstr:
Name = "%s_%s" % (mnem.upper(), Name)
else: else:
memFlags.append("ArmISA::TLB::AllowUnaligned") memFlags.append("ArmISA::TLB::AllowUnaligned")
base = buildMemBase("MemoryImm", post, writeback) base = buildMemBase("MemoryImm", post, writeback)
@ -179,7 +189,8 @@ let {{
"ArmISA::TLB::AllowUnaligned", \ "ArmISA::TLB::AllowUnaligned", \
"%d" % (size - 1)], [], base) "%d" % (size - 1)], [], base)
def buildDoubleImmStore(mnem, post, add, writeback, strex=False): def buildDoubleImmStore(mnem, post, add, writeback, \
strex=False, vstr=False):
name = mnem name = mnem
Name = storeDoubleImmClassName(post, add, writeback) Name = storeDoubleImmClassName(post, add, writeback)
@ -194,6 +205,13 @@ let {{
eaCode += offset eaCode += offset
eaCode += ";" eaCode += ";"
if vstr:
accCode = '''
uint64_t swappedMem = (uint64_t)FpDest.uw |
((uint64_t)FpDest2.uw << 32);
Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
'''
else:
accCode = ''' accCode = '''
CPSR cpsr = Cpsr; CPSR cpsr = Cpsr;
Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
@ -206,12 +224,13 @@ let {{
"ArmISA::TLB::AlignWord"] "ArmISA::TLB::AlignWord"]
if strex: if strex:
memFlags.append("Request::LLSC") memFlags.append("Request::LLSC")
Name = "%s_%s" % (mnem.upper(), Name)
base = buildMemBase("MemoryExDImm", post, writeback) base = buildMemBase("MemoryExDImm", post, writeback)
postAccCode = "Result = !writeResult;" postAccCode = "Result = !writeResult;"
else: else:
base = buildMemBase("MemoryDImm", post, writeback) base = buildMemBase("MemoryDImm", post, writeback)
postAccCode = "" postAccCode = ""
if vstr or strex:
Name = "%s_%s" % (mnem.upper(), Name)
emitStore(name, Name, True, eaCode, accCode, postAccCode, \ emitStore(name, Name, True, eaCode, accCode, postAccCode, \
memFlags, [], base, double=True, strex=strex) memFlags, [], base, double=True, strex=strex)
@ -300,4 +319,9 @@ let {{
buildImmStore("strexh", False, True, False, size=2, strex=True) buildImmStore("strexh", False, True, False, size=2, strex=True)
buildImmStore("strexb", False, True, False, size=1, strex=True) buildImmStore("strexb", False, True, False, size=1, strex=True)
buildDoubleImmStore("strexd", False, True, False, strex=True) buildDoubleImmStore("strexd", False, True, False, strex=True)
buildImmStore("vstr", False, True, False, size=4, vstr=True)
buildImmStore("vstr", False, False, False, size=4, vstr=True)
buildDoubleImmStore("vstr", False, True, False, vstr=True)
buildDoubleImmStore("vstr", False, False, False, vstr=True)
}}; }};