Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface

--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
This commit is contained in:
Ron Dreslinski 2005-04-29 21:01:43 -04:00
parent e07fee31cb
commit 602a489573
6 changed files with 25 additions and 9 deletions

View file

@ -97,7 +97,8 @@ IdeController::IdeController(Params *p)
dmaInterface = new DMAInterface<Bus>(name() + ".dma", dmaInterface = new DMAInterface<Bus>(name() + ".dma",
params()->host_bus, params()->host_bus,
params()->host_bus, 1); params()->host_bus, 1,
true);
pioLatency = params()->pio_latency * params()->host_bus->clockRatio; pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
} }

View file

@ -120,11 +120,13 @@ NSGigE::NSGigE(Params *p)
if (p->payload_bus) if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(name() + ".dma", dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->header_bus, p->header_bus,
p->payload_bus, 1); p->payload_bus, 1,
p->dma_no_allocate);
else else
dmaInterface = new DMAInterface<Bus>(name() + ".dma", dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->header_bus, p->header_bus,
p->header_bus, 1); p->header_bus, 1,
p->dma_no_allocate);
} else if (p->payload_bus) { } else if (p->payload_bus) {
pioInterface = newPioInterface(name(), p->hier, pioInterface = newPioInterface(name(), p->hier,
p->payload_bus, this, p->payload_bus, this,
@ -134,7 +136,8 @@ NSGigE::NSGigE(Params *p)
dmaInterface = new DMAInterface<Bus>(name() + ".dma", dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->payload_bus, p->payload_bus,
p->payload_bus, 1); p->payload_bus, 1,
p->dma_no_allocate);
} }
@ -2713,6 +2716,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<uint32_t> tx_fifo_size; Param<uint32_t> tx_fifo_size;
Param<uint32_t> rx_fifo_size; Param<uint32_t> rx_fifo_size;
Param<uint32_t> m5reg; Param<uint32_t> m5reg;
Param<bool> dma_no_allocate;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
@ -2746,7 +2750,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072), INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072),
INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072), INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072),
INIT_PARAM(m5reg, "m5 register") INIT_PARAM(m5reg, "m5 register"),
INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true)
END_INIT_SIM_OBJECT_PARAMS(NSGigE) END_INIT_SIM_OBJECT_PARAMS(NSGigE)
@ -2784,6 +2789,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->tx_fifo_size = tx_fifo_size; params->tx_fifo_size = tx_fifo_size;
params->rx_fifo_size = rx_fifo_size; params->rx_fifo_size = rx_fifo_size;
params->m5reg = m5reg; params->m5reg = m5reg;
params->dma_no_allocate = dma_no_allocate;
return new NSGigE(params); return new NSGigE(params);
} }

View file

@ -344,6 +344,7 @@ class NSGigE : public PciDev
uint32_t tx_fifo_size; uint32_t tx_fifo_size;
uint32_t rx_fifo_size; uint32_t rx_fifo_size;
uint32_t m5reg; uint32_t m5reg;
bool dma_no_allocate;
}; };
NSGigE(Params *params); NSGigE(Params *params);

View file

@ -103,11 +103,11 @@ Device::Device(Params *p)
if (p->payload_bus) if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
p->header_bus, p->payload_bus, p->header_bus, p->payload_bus,
1); 1, p->dma_no_allocate);
else else
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
p->header_bus, p->header_bus, p->header_bus, p->header_bus,
1); 1, p->dma_no_allocate);
} else if (p->payload_bus) { } else if (p->payload_bus) {
pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this, pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
&Device::cacheAccess); &Device::cacheAccess);
@ -115,7 +115,8 @@ Device::Device(Params *p)
pioLatency = p->pio_latency * p->payload_bus->clockRatio; pioLatency = p->pio_latency * p->payload_bus->clockRatio;
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus, dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
p->payload_bus, 1); p->payload_bus, 1,
p->dma_no_allocate);
} }
} }
@ -1388,6 +1389,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<Tick> dma_read_factor; Param<Tick> dma_read_factor;
Param<Tick> dma_write_delay; Param<Tick> dma_write_delay;
Param<Tick> dma_write_factor; Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
END_DECLARE_SIM_OBJECT_PARAMS(Device) END_DECLARE_SIM_OBJECT_PARAMS(Device)
@ -1421,7 +1423,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0), INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),
INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0), INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0),
INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0), INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0),
INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0) INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
INIT_PARAM_DFLT(dma_no_allocate, "Should we allocat on read in cache", true)
END_INIT_SIM_OBJECT_PARAMS(Device) END_INIT_SIM_OBJECT_PARAMS(Device)
@ -1458,6 +1461,7 @@ CREATE_SIM_OBJECT(Device)
params->dma_read_factor = dma_read_factor; params->dma_read_factor = dma_read_factor;
params->dma_write_delay = dma_write_delay; params->dma_write_delay = dma_write_delay;
params->dma_write_factor = dma_write_factor; params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
return new Device(params); return new Device(params);
} }

View file

@ -316,6 +316,7 @@ class Device : public Base
Tick dma_read_factor; Tick dma_read_factor;
Tick dma_write_delay; Tick dma_write_delay;
Tick dma_write_factor; Tick dma_write_factor;
bool dma_no_allocate;
}; };
protected: protected:

View file

@ -41,6 +41,7 @@ simobj EtherDev(DmaDevice):
dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes") dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
rx_filter = Param.Bool(True, "Enable Receive Filter") rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Latency('1us', "Receive Delay") rx_delay = Param.Latency('1us', "Receive Delay")
@ -64,6 +65,8 @@ simobj NSGigE(PciDevice):
dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes") dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
rx_filter = Param.Bool(True, "Enable Receive Filter") rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Latency('1us', "Receive Delay") rx_delay = Param.Latency('1us', "Receive Delay")