sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Interesting memtest finally.

Browse source 
Get over 500,000 reads on each of 8 testers before memory leak becomes large.

tests/configs/memtest.py:
    Update test to be more interesting

--HG--
extra : convert_revision : 4258b798fbeeed2a376f1bfac100a109eb05620e
This commit is contained in:
Ron Dreslinski 2006-10-11 01:18:20 -04:00
parent 4e35c5656f
commit 60252f8e63
1 changed files with 6 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
tests/configs/memtest.py
View file

@ -53,14 +53,14 @@ class L2(BaseCache):
#MAX CORES IS 8 with the fals sharing method #MAX CORES IS 8 with the fals sharing method
nb_cores = 8 nb_cores = 8
cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0) for i in xrange(nb_cores) ] cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ]
# system simulated # system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(), system = System(cpu = cpus, funcmem = PhysicalMemory(),
physmem = PhysicalMemory(), membus = Bus()) physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
# l2cache & bus # l2cache & bus
system.toL2Bus = Bus() system.toL2Bus = Bus(clock="500GHz", width=16)
system.l2c = L2(size='64kB', assoc=8) system.l2c = L2(size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port system.l2c.cpu_side = system.toL2Bus.port
@ -90,4 +90,6 @@ system.physmem.port = system.membus.port
root = Root( system = system ) root = Root( system = system )
root.system.mem_mode = 'timing' root.system.mem_mode = 'timing'
root.trace.flags="Cache" #root.trace.flags="Cache CachePort Bus"
#root.trace.cycle=3810800