Make things compile in SE again.

--HG--
extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800
This commit is contained in:
Gabe Black 2006-11-03 14:42:12 -05:00
parent 8778d85b2d
commit 601822c6b5

View file

@ -322,8 +322,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc) const MiscReg &val, ThreadContext * tc)
{ {
const uint64_t Bit64 = (1ULL << 63); const uint64_t Bit64 = (1ULL << 63);
uint64_t time;
#if FULL_SYSTEM #if FULL_SYSTEM
uint64_t time;
SparcSystem *sys; SparcSystem *sys;
#endif #endif
switch (miscReg) { switch (miscReg) {
@ -364,6 +364,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_SOFTINT_SET: case MISCREG_SOFTINT_SET:
//Do whatever this is supposed to do... //Do whatever this is supposed to do...
break; break;
#if FULL_SYSTEM
case MISCREG_TICK_CMPR: case MISCREG_TICK_CMPR:
if (tickCompare == NULL) if (tickCompare == NULL)
tickCompare = new TickCompareEvent(this, tc); tickCompare = new TickCompareEvent(this, tc);
@ -374,6 +375,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
if (!tick_cmprFields.int_dis && time > 0) if (!tick_cmprFields.int_dis && time > 0)
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
break; break;
#endif
case MISCREG_PIL: case MISCREG_PIL:
//We need to inject interrupts, and or notify the interrupt //We need to inject interrupts, and or notify the interrupt
//object that it needs to use a different interrupt level. //object that it needs to use a different interrupt level.
@ -482,6 +484,7 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
implicitDataAsi = (ASI)temp; implicitDataAsi = (ASI)temp;
} }
#if FULL_SYSTEM
void void
MiscRegFile::processTickCompare(ThreadContext *tc) MiscRegFile::processTickCompare(ThreadContext *tc)
{ {
@ -499,3 +502,4 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
{ {
panic("tick compare not implemented\n"); panic("tick compare not implemented\n");
} }
#endif