ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
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@ -69,6 +69,8 @@ def template SwapExecute {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -103,6 +105,8 @@ def template SwapInitiateAcc {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -164,6 +168,8 @@ def template LoadExecute {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -200,6 +206,8 @@ def template StoreExecute {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -242,6 +250,8 @@ def template StoreExExecute {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -279,6 +289,8 @@ def template StoreExInitiateAcc {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -316,6 +328,8 @@ def template StoreInitiateAcc {{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -342,8 +356,11 @@ def template LoadInitiateAcc {{
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
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}
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} else if (fault == NoFault && machInst.itstateMask != 0) {
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xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
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} else {
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xc->setPredicate(false);
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if (fault == NoFault && machInst.itstateMask != 0) {
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xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
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}
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}
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return fault;
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@ -142,6 +142,8 @@ def template PredOpExecute {{
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{
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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if (fault == NoFault && machInst.itstateMask != 0) {
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@ -246,6 +246,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Micro PC of this instruction. */
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Addr microPC;
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/** Did this instruction execute, or is it predicated false */
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bool predicate;
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protected:
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/** Next non-speculative PC. It is not filled in at fetch, but rather
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* once the target of the branch is truly known (either decode or
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@ -794,6 +797,16 @@ class BaseDynInst : public FastAlloc, public RefCounted
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nextMicroPC = val;
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}
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bool readPredicate()
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{
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return predicate;
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}
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void setPredicate(bool val)
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{
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predicate = val;
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}
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/** Sets the ASID. */
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void setASID(short addr_space_id) { asid = addr_space_id; }
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@ -154,6 +154,7 @@ BaseDynInst<Impl>::initVars()
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eaCalcDone = false;
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memOpDone = false;
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predicate = true;
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lqIdx = -1;
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sqIdx = -1;
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -439,9 +451,9 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
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load_fault = inst->initiateAcc();
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// If the instruction faulted, then we need to send it along to commit
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// without the instruction completing.
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if (load_fault != NoFault) {
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// If the instruction faulted or predicated false, then we need to send it
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// along to commit without the instruction completing.
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if (load_fault != NoFault || inst->readPredicate() == false) {
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// Send this instruction to commit, also make sure iew stage
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// realizes there is activity.
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// Mark it as executed unless it is an uncached load that
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@ -287,12 +287,15 @@ class BaseSimpleCPU : public BaseCPU
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uint64_t readNextPC() { return thread->readNextPC(); }
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uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
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uint64_t readNextNPC() { return thread->readNextNPC(); }
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bool readPredicate() { return thread->readPredicate(); }
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void setPC(uint64_t val) { thread->setPC(val); }
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void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
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void setNextPC(uint64_t val) { thread->setNextPC(val); }
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void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
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void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
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void setPredicate(bool val)
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{ return thread->setPredicate(val); }
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MiscReg readMiscRegNoEffect(int misc_reg)
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{
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@ -128,6 +128,9 @@ class SimpleThread : public ThreadState
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*/
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Addr nextNPC;
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/** Did this instruction execute or is it predicated false */
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bool predicate;
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public:
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// pointer to CPU associated with this SimpleThread
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BaseCPU *cpu;
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@ -371,6 +374,16 @@ class SimpleThread : public ThreadState
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#endif
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}
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bool readPredicate()
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{
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return predicate;
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}
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void setPredicate(bool val)
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{
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predicate = val;
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
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{
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@ -404,6 +404,11 @@ class ProxyThreadContext : public ThreadContext
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void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
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bool readPredicate() { return actualTC->readPredicate(); }
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void setPredicate(bool val)
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{ actualTC->setPredicate(val); }
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MiscReg readMiscRegNoEffect(int misc_reg)
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{ return actualTC->readMiscRegNoEffect(misc_reg); }
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