sim: move iterating over SimObjects into Python.
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@ -530,7 +530,8 @@ class SimObject(object):
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# If the attribute exists on the C++ object, transparently
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# forward the reference there. This is typically used for
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# SWIG-wrapped methods such as init(), regStats(),
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# regFormulas(), resetStats(), and startup().
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# regFormulas(), resetStats(), startup(), drain(), and
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# resume().
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if self._ccObject and hasattr(self._ccObject, attr):
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return getattr(self._ccObject, attr)
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@ -660,7 +661,7 @@ class SimObject(object):
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def unproxy(self, base):
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return self
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def unproxy_all(self):
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def unproxyParams(self):
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for param in self._params.iterkeys():
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value = self._values.get(param)
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if value != None and isproxy(value):
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@ -681,12 +682,6 @@ class SimObject(object):
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if port != None:
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port.unproxy(self)
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# Unproxy children in sorted order for determinism also.
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child_names = self._children.keys()
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child_names.sort()
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for child in child_names:
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self._children[child].unproxy_all()
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def print_ini(self, ini_file):
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print >>ini_file, '[' + self.path() + ']' # .ini section header
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@ -717,9 +712,6 @@ class SimObject(object):
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print >>ini_file # blank line between objects
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for child in child_names:
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self._children[child].print_ini(ini_file)
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def getCCParams(self):
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if self._ccParams:
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return self._ccParams
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@ -774,39 +766,25 @@ class SimObject(object):
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% self.path()
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return self._ccObject
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# Call C++ to create C++ object corresponding to this object and
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# (recursively) all its children
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def descendants(self):
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yield self
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for child in self._children.itervalues():
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for obj in child.descendants():
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yield obj
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# Call C++ to create C++ object corresponding to this object
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def createCCObject(self):
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self.getCCParams()
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self.getCCObject() # force creation
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for child in self._children.itervalues():
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child.createCCObject()
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def getValue(self):
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return self.getCCObject()
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# Create C++ port connections corresponding to the connections in
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# _port_refs (& recursively for all children)
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# _port_refs
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def connectPorts(self):
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for portRef in self._port_refs.itervalues():
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portRef.ccConnect()
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for child in self._children.itervalues():
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child.connectPorts()
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def startDrain(self, drain_event, recursive):
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count = 0
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if isinstance(self, SimObject):
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count += self._ccObject.drain(drain_event)
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if recursive:
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for child in self._children.itervalues():
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count += child.startDrain(drain_event, True)
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return count
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def resume(self):
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if isinstance(self, SimObject):
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self._ccObject.resume()
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for child in self._children.itervalues():
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child.resume()
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def getMemoryMode(self):
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if not isinstance(self, m5.objects.System):
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@ -820,8 +798,6 @@ class SimObject(object):
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# setMemoryMode directly from self._ccObject results in calling
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# SimObject::setMemoryMode, not the System::setMemoryMode
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self._ccObject.setMemoryMode(mode)
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for child in self._children.itervalues():
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child.changeTiming(mode)
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def takeOverFrom(self, old_cpu):
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self._ccObject.takeOverFrom(old_cpu._ccObject)
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@ -27,14 +27,6 @@
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# Authors: Nathan Binkert
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import internal
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from internal.core import initAll, regAllStats
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def setOutputDir(dir):
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internal.core.setOutputDir(dir)
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def initAll():
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internal.core.initAll()
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def regAllStats():
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internal.core.regAllStats()
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@ -55,25 +55,29 @@ def instantiate():
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# we need to fix the global frequency
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ticks.fixGlobalFrequency()
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root.unproxy_all()
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# Unproxy in sorted order for determinism
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for obj in root.descendants(): obj.unproxyParams()
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if options.dump_config:
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ini_file = file(os.path.join(options.outdir, options.dump_config), 'w')
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root.print_ini(ini_file)
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# Print ini sections in sorted order for easier diffing
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for obj in sorted(root.descendants(), key=lambda o: o.path()):
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obj.print_ini(ini_file)
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ini_file.close()
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# Initialize the global statistics
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stats.initSimStats()
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# Create the C++ sim objects and connect ports
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root.createCCObject()
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root.connectPorts()
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for obj in root.descendants(): obj.createCCObject()
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for obj in root.descendants(): obj.connectPorts()
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# Do a second pass to finish initializing the sim objects
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core.initAll()
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for obj in root.descendants(): obj.init()
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# Do a third pass to initialize statistics
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core.regAllStats()
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for obj in root.descendants(): obj.regStats()
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for obj in root.descendants(): obj.regFormulas()
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# We're done registering statistics. Enable the stats package now.
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stats.enable()
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@ -97,7 +101,8 @@ def simulate(*args, **kwargs):
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global need_resume, need_startup
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if need_startup:
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internal.core.startupAll()
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root = objects.Root.getInstance()
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for obj in root.descendants(): obj.startup()
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need_startup = False
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for root in need_resume:
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@ -129,10 +134,10 @@ def doDrain(root):
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def drain(root):
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all_drained = False
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drain_event = internal.event.createCountedDrain()
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unready_objects = root.startDrain(drain_event, True)
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unready_objs = sum(obj.drain(drain_event) for obj in root.descendants())
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# If we've got some objects that can't drain immediately, then simulate
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if unready_objects > 0:
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drain_event.setCount(unready_objects)
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if unready_objs > 0:
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drain_event.setCount(unready_objs)
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simulate()
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else:
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all_drained = True
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@ -140,7 +145,7 @@ def drain(root):
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return all_drained
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def resume(root):
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root.resume()
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for obj in root.descendants(): obj.resume()
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def checkpoint(dir):
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root = objects.Root.getInstance()
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@ -165,7 +170,8 @@ def changeToAtomic(system):
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if system.getMemoryMode() != objects.params.atomic:
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doDrain(system)
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print "Changing memory mode to atomic"
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system.changeTiming(objects.params.atomic)
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for obj in system.descendants():
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obj.changeTiming(objects.params.atomic)
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def changeToTiming(system):
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if not isinstance(system, (objects.Root, objects.System)):
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@ -175,7 +181,8 @@ def changeToTiming(system):
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if system.getMemoryMode() != objects.params.timing:
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doDrain(system)
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print "Changing memory mode to timing"
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system.changeTiming(objects.params.timing)
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for obj in system.descendants():
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obj.changeTiming(objects.params.timing)
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def switchCpus(cpuList):
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print "switching cpus"
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@ -29,6 +29,7 @@
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import internal
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from internal.stats import StatEvent as event
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from objects import Root
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def initText(filename, desc=True):
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internal.stats.initText(filename, desc)
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@ -56,4 +57,8 @@ def dump():
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internal.stats.dump()
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def reset():
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# call reset stats on all SimObjects
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root = Root.getInstance()
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for obj in root.descendants(): obj.resetStats()
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# call any other registered stats reset callbacks
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internal.stats.reset()
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@ -78,10 +78,6 @@ Tick curTick;
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void serializeAll(const std::string &cpt_dir);
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void unserializeAll(const std::string &cpt_dir);
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void initAll();
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void regAllStats();
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void startupAll();
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bool want_warn, warn_verbose;
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bool want_info, info_verbose;
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bool want_hack, hack_verbose;
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@ -45,17 +45,6 @@ SimObject *resolveSimObject(const std::string &name);
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int connectPorts(SimObject *o1, const std::string &name1, int i1,
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SimObject *o2, const std::string &name2, int i2);
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inline void
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initAll()
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{
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SimObject::initAll();
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}
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inline void
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regAllStats()
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{
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SimObject::regAllStats();
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}
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inline void
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serializeAll(const std::string &cpt_dir)
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@ -68,9 +57,3 @@ unserializeAll(const std::string &cpt_dir)
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{
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Serializable::unserializeAll(cpt_dir);
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}
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inline void
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startupAll()
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{
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SimObject::startupAll();
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}
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@ -50,6 +50,12 @@ class SimObject {
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Drained
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};
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void init();
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void regStats();
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void regFormulas();
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void resetStats();
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void startup();
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unsigned int drain(Event *drain_event);
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void resume();
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void switchOut();
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@ -96,76 +96,6 @@ SimObject::resetStats()
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{
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}
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//
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// static function:
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// call regStats() on all SimObjects and then regFormulas() on all
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// SimObjects.
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//
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struct SimObjectResetCB : public Callback
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{
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virtual void process() { SimObject::resetAllStats(); }
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};
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namespace {
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static SimObjectResetCB StatResetCB;
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}
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void
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SimObject::regAllStats()
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{
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SimObjectList::iterator i;
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SimObjectList::iterator end = simObjectList.end();
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/**
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* @todo change cprintfs to DPRINTFs
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*/
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for (i = simObjectList.begin(); i != end; ++i) {
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#ifdef STAT_DEBUG
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cprintf("registering stats for %s\n", (*i)->name());
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#endif
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(*i)->regStats();
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}
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for (i = simObjectList.begin(); i != end; ++i) {
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#ifdef STAT_DEBUG
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cprintf("registering formulas for %s\n", (*i)->name());
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#endif
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(*i)->regFormulas();
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}
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Stats::registerResetCallback(&StatResetCB);
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}
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//
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// static function: call init() on all SimObjects.
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//
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void
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SimObject::initAll()
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{
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SimObjectList::iterator i = simObjectList.begin();
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SimObjectList::iterator end = simObjectList.end();
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for (; i != end; ++i) {
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SimObject *obj = *i;
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obj->init();
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}
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}
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//
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// static function: call resetStats() on all SimObjects.
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//
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void
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SimObject::resetAllStats()
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{
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SimObjectList::iterator i = simObjectList.begin();
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SimObjectList::iterator end = simObjectList.end();
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for (; i != end; ++i) {
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SimObject *obj = *i;
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obj->resetStats();
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}
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}
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//
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// static function: serialize all SimObjects.
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//
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@ -201,18 +131,6 @@ SimObject::unserializeAll(Checkpoint *cp)
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}
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void
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SimObject::startupAll()
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{
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SimObjectList::iterator i = simObjectList.begin();
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SimObjectList::iterator end = simObjectList.end();
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while (i != end) {
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(*i)->startup();
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++i;
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}
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}
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#ifdef DEBUG
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//
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@ -94,7 +94,6 @@ class SimObject : public EventManager, public Serializable
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// initialization pass of all objects.
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// Gets invoked after construction, before unserialize.
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virtual void init();
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static void initAll();
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// register statistics for this object
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virtual void regStats();
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// final initialization before simulation
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// all state is unserialized so
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virtual void startup();
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static void startupAll();
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// static: call reg_stats on all SimObjects
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static void regAllStats();
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// static: call resetStats on all SimObjects
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static void resetAllStats();
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// static: call nameOut() & serialize() on all SimObjects
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static void serializeAll(std::ostream &);
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