From 5e2263fc523633af81a81ed7cea2cf72bd57efbb Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sat, 21 Oct 2006 23:35:00 -0700
Subject: [PATCH] Small bug fixes for timing LL/SC.  Better now but not
 necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
---
 src/mem/cache/cache_impl.hh | 7 ++++++-
 src/mem/packet.hh           | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 64f658907..3c47762f6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -232,7 +232,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
         }
     }
 
-    if (!(pkt->flags & SATISFIED)) {
+    if (pkt->flags & SATISFIED) {
+        // happens when a store conditional fails because it missed
+        // the cache completely
+        if (pkt->needsResponse())
+            respond(pkt, curTick+lat);
+    } else {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
     }
 
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 1a0011d87..cb97dd036 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -310,6 +310,7 @@ class Packet
      *   multiple transactions. */
     void reinitFromRequest() {
         assert(req->validPaddr);
+        flags = 0;
         addr = req->paddr;
         size = req->size;
         time = req->time;