diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 64f658907..3c47762f6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -232,7 +232,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
         }
     }
 
-    if (!(pkt->flags & SATISFIED)) {
+    if (pkt->flags & SATISFIED) {
+        // happens when a store conditional fails because it missed
+        // the cache completely
+        if (pkt->needsResponse())
+            respond(pkt, curTick+lat);
+    } else {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
     }
 
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 1a0011d87..cb97dd036 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -310,6 +310,7 @@ class Packet
      *   multiple transactions. */
     void reinitFromRequest() {
         assert(req->validPaddr);
+        flags = 0;
         addr = req->paddr;
         size = req->size;
         time = req->time;