kvm: x86: Adjust PC to remove the CS segment base address
gem5 seems to store the PC as RIP+CS_BASE. This is not what KVM expects, so we need to subtract CS_BASE prior to transferring the PC into KVM. This changeset adds the necessary PC manipulation and refactors thread context updates slightly to avoid reading registers multiple times from KVM. --HG-- extra : rebase_source : 3f0569dca06a1fcd8694925f75c8918d954ada44
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2 changed files with 32 additions and 28 deletions
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@ -690,7 +690,7 @@ X86KvmCPU::updateKvmStateRegs()
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FOREACH_IREG();
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#undef APPLY_IREG
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regs.rip = tc->instAddr();
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regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE);
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/* You might think that setting regs.rflags to the contents
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* MISCREG_RFLAGS here would suffice. In that case you're
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@ -936,16 +936,29 @@ X86KvmCPU::updateKvmStateMSRs()
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void
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X86KvmCPU::updateThreadContext()
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{
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struct kvm_regs regs;
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struct kvm_sregs sregs;
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getRegisters(regs);
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getSpecialRegisters(sregs);
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DPRINTF(KvmContext, "X86KvmCPU::updateThreadContext():\n");
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if (DTRACE(KvmContext))
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dump();
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updateThreadContextRegs();
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updateThreadContextSRegs();
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if (useXSave)
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updateThreadContextXSave();
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else
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updateThreadContextFPU();
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updateThreadContextRegs(regs, sregs);
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updateThreadContextSRegs(sregs);
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if (useXSave) {
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struct kvm_xsave xsave;
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getXSave(xsave);
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updateThreadContextXSave(xsave);
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} else {
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struct kvm_fpu fpu;
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getFPUState(fpu);
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updateThreadContextFPU(fpu);
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}
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updateThreadContextMSRs();
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// The M5 misc reg caches some values from other
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@ -955,18 +968,16 @@ X86KvmCPU::updateThreadContext()
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}
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void
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X86KvmCPU::updateThreadContextRegs()
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X86KvmCPU::updateThreadContextRegs(const struct kvm_regs ®s,
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const struct kvm_sregs &sregs)
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{
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struct kvm_regs regs;
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getRegisters(regs);
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#define APPLY_IREG(kreg, mreg) tc->setIntReg(mreg, regs.kreg)
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FOREACH_IREG();
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#undef APPLY_IREG
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tc->pcState(PCState(regs.rip));
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tc->pcState(PCState(regs.rip + sregs.cs.base));
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// Flags are spread out across multiple semi-magic registers so we
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// need some special care when updating them.
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@ -1011,11 +1022,8 @@ setContextSegment(ThreadContext *tc, const struct kvm_dtable &kvm_dtable,
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}
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void
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X86KvmCPU::updateThreadContextSRegs()
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X86KvmCPU::updateThreadContextSRegs(const struct kvm_sregs &sregs)
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{
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struct kvm_sregs sregs;
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getSpecialRegisters(sregs);
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assert(getKvmRunState()->apic_base == sregs.apic_base);
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assert(getKvmRunState()->cr8 == sregs.cr8);
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@ -1070,11 +1078,8 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu)
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}
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void
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X86KvmCPU::updateThreadContextFPU()
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X86KvmCPU::updateThreadContextFPU(const struct kvm_fpu &fpu)
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{
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struct kvm_fpu fpu;
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getFPUState(fpu);
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updateThreadContextFPUCommon(tc, fpu);
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tc->setMiscRegNoEffect(MISCREG_FISEG, 0);
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@ -1084,11 +1089,9 @@ X86KvmCPU::updateThreadContextFPU()
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}
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void
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X86KvmCPU::updateThreadContextXSave()
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X86KvmCPU::updateThreadContextXSave(const struct kvm_xsave &kxsave)
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{
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struct kvm_xsave kxsave;
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FXSave &xsave(*(FXSave *)kxsave.region);
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getXSave(kxsave);
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const FXSave &xsave(*(const FXSave *)kxsave.region);
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updateThreadContextFPUCommon(tc, xsave);
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@ -209,13 +209,14 @@ class X86KvmCPU : public BaseKvmCPU
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* @{
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*/
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/** Update integer registers */
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void updateThreadContextRegs();
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void updateThreadContextRegs(const struct kvm_regs ®s,
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const struct kvm_sregs &sregs);
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/** Update control registers (CRx, segments, etc.) */
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void updateThreadContextSRegs();
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void updateThreadContextSRegs(const struct kvm_sregs &sregs);
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/** Update FPU and SIMD registers using the legacy API */
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void updateThreadContextFPU();
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void updateThreadContextFPU(const struct kvm_fpu &fpu);
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/** Update FPU and SIMD registers using the XSave API */
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void updateThreadContextXSave();
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void updateThreadContextXSave(const struct kvm_xsave &kxsave);
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/** Update MSR registers */
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void updateThreadContextMSRs();
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/** @} */
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