diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index 0aa57a261..f1bfceac1 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -235,6 +235,9 @@ def format ArmUnconditional() {{
                     return new BlxImm(machInst, imm);
                 }
               case 0x2:
+                if (CPNUM == 0xa || CPNUM == 0xb) {
+                    return decodeExtensionRegLoadStore(machInst);
+                }
                 if (bits(op1, 0) == 1) {
                     if (rn == INTREG_PC) {
                         if (bits(op1, 4, 3) != 0x0) {
@@ -260,6 +263,9 @@ def format ArmUnconditional() {{
                 break;
               case 0x3:
                 {
+                    if (CPNUM == 0xa || CPNUM == 0xb) {
+                        return decodeShortFpTransfer(machInst);
+                    }
                     const bool op = bits(machInst, 4);
                     if (op) {
                         if (bits(op1, 0)) {