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Stats: Update stats for minor O3 changes below.

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This commit is contained in:
Ali Saidi 2011-05-23 10:59:13 -05:00
parent d0b0a55515
commit 5d5b0f49cc
33 changed files with 7785 additions and 7760 deletions
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8
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
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@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 13:57:03 M5 started May 16 2011 16:32:58
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -44,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 189747670000 because target called exit() Exiting @ tick 189745250000 because target called exit()

1006
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

10
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
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@ -1,3 +1,5 @@
Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -5,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Apr 21 2011 13:27:10 M5 compiled May 17 2011 09:24:34
M5 started Apr 21 2011 13:30:00 M5 started May 18 2011 08:03:10
M5 executing on maize M5 executing on nadc-0214
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -42,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 582418059000 because target called exit() Exiting @ tick 582418265000 because target called exit()

852
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
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@ -1,319 +1,111 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 154343 # Simulator instruction rate (inst/s)
host_mem_usage 212152 # Number of bytes of host memory used
host_seconds 9107.03 # Real time elapsed on the host
host_tick_rate 63952564 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405604152 # Number of instructions simulated
sim_seconds 0.582418 # Number of seconds simulated sim_seconds 0.582418 # Number of seconds simulated
sim_ticks 582418059000 # Number of ticks simulated sim_ticks 582418265000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 199078 # Simulator instruction rate (inst/s)
host_tick_rate 82488656 # Simulator tick rate (ticks/s)
host_mem_usage 245404 # Number of bytes of host memory used
host_seconds 7060.59 # Real time elapsed on the host
sim_insts 1405604152 # Number of instructions simulated
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1164836531 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 103713430 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 103713430 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 5339068 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 99018529 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 97659626 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 97659749 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 99018650 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5339067 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 103713551 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 103713551 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 5339067 # The number of times a branch was mispredicted system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.commit.branches 86248929 # Number of branches committed system.cpu.fetch.icacheStallCycles 170870341 # Number of cycles fetch is stalled on an Icache miss
system.cpu.commit.bw_lim_events 26710610 # number cycles where commit BW limit reached system.cpu.fetch.Insts 1732290571 # Number of instructions fetch has processed
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.fetch.Branches 103713430 # Number of branches that fetch encountered
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions system.cpu.fetch.predictedBranches 97659626 # Number of branches that fetch has predicted taken
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards system.cpu.fetch.Cycles 370649677 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.commit.commitSquashedInsts 199490556 # The number of squashed insts skipped by commit system.cpu.fetch.SquashCycles 5787764 # Number of cycles fetch has spent squashing
system.cpu.commit.committed_per_cycle::samples 1136580592 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.310530 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1136580592 # Number of insts commited each cycle
system.cpu.commit.count 1489523295 # Number of instructions committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.loads 402512844 # Number of loads committed
system.cpu.commit.membars 51356 # Number of memory barriers committed
system.cpu.commit.refs 569360986 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.828709 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 291461478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14664.632652 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7474.067095 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 290645276 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11969302500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002800 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 816202 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 602863 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1594510000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000732 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 213339 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 15381.021476 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13048.542893 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 165025455 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 28014392657 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010916 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1821361 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1553325 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 3497479243 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001606 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 268036 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 946.591376 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 458308294 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 15159.332747 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency
system.cpu.dcache.demand_hits 455670731 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 39983695157 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005755 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2637563 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2156188 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5091989243 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001050 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 481375 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 4095.405595 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 458308294 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15159.332747 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 455670731 # number of overall hits
system.cpu.dcache.overall_miss_latency 39983695157 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005755 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2637563 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2156188 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5091989243 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001050 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 481375 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 477286 # number of replacements
system.cpu.dcache.sampled_refs 481382 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.405595 # Cycle average of tags in use
system.cpu.dcache.total_refs 455672050 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 132278000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428224 # number of writebacks
system.cpu.decode.BlockedCycles 373408138 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 1727466392 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 394807577 # Number of cycles decode is idle
system.cpu.decode.RunCycles 348667632 # Number of cycles decode is running
system.cpu.decode.SquashCycles 27885594 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 19696634 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 103713551 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 170870865 # Number of cache lines fetched
system.cpu.fetch.Cycles 370648133 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1257771 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1732289789 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 5787763 # Number of cycles fetch has spent squashing system.cpu.fetch.CacheLines 170870341 # Number of cache lines fetched
system.cpu.fetch.branchRate 0.089037 # Number of branch fetches per cycle system.cpu.fetch.IcacheSquashes 1258030 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.icacheStallCycles 170870865 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.rateDist::samples 1164465958 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.predictedBranches 97659749 # Number of branches that fetch has predicted taken system.cpu.fetch.rateDist::mean 1.491542 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rate 1.487153 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1164465575 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.491538 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.715145 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.715145 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 793817442 68.17% 68.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 793816281 68.17% 68.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 81924135 7.04% 75.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 81924128 7.04% 75.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 44978693 3.86% 79.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 44979241 3.86% 79.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 22977276 1.97% 81.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 22976761 1.97% 81.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 33360505 2.86% 83.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 33360505 2.86% 83.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 33148842 2.85% 86.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 33149354 2.85% 86.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 14858388 1.28% 88.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 14860425 1.28% 88.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7508131 0.64% 88.67% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 7508136 0.64% 88.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 131892163 11.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 131891127 11.33% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1164465575 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1164465958 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16956220 # number of floating regfile reads system.cpu.fetch.branchRate 0.089037 # Number of branch fetches per cycle
system.cpu.fp_regfile_writes 10464632 # number of floating regfile writes system.cpu.fetch.rate 1.487153 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_accesses 170870865 # number of ReadReq accesses(hits+misses) system.cpu.decode.IdleCycles 394807963 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_miss_latency 35272.495756 # average ReadReq miss latency system.cpu.decode.BlockedCycles 373406946 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.283732 # average ReadReq mshr miss latency system.cpu.decode.RunCycles 348668673 # Number of cycles decode is running
system.cpu.icache.ReadReq_hits 170869098 # number of ReadReq hits system.cpu.decode.UnblockCycles 19696602 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_latency 62326500 # number of ReadReq miss cycles system.cpu.decode.SquashCycles 27885774 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.decode.DecodedInsts 1727469213 # Number of instructions handled by decode
system.cpu.icache.ReadReq_misses 1767 # number of ReadReq misses system.cpu.rename.SquashCycles 27885774 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_hits 470 # number of ReadReq MSHR hits system.cpu.rename.IdleCycles 433132489 # Number of cycles rename is idle
system.cpu.icache.ReadReq_mshr_miss_latency 45468000 # number of ReadReq MSHR miss cycles system.cpu.rename.BlockCycles 115497751 # Number of cycles rename is blocking
system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.rename.serializeStallCycles 53046647 # count of cycles rename stalled for serializing inst
system.cpu.icache.ReadReq_mshr_misses 1297 # number of ReadReq MSHR misses system.cpu.rename.RunCycles 325738473 # Number of cycles rename is running
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.UnblockCycles 209164824 # Number of cycles rename is unblocking
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.RenamedInsts 1709743087 # Number of instructions processed by rename
system.cpu.icache.avg_refs 131843.439815 # Average number of references to valid blocks. system.cpu.rename.IQFullEvents 128337088 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 40459305 # Number of times rename has blocked due to LSQ full
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.FullRegisterEvents 28107626 # Number of times there has been no free registers
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.RenamedOperands 1426817560 # Number of destination operands rename has renamed
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenameLookups 2887436309 # Number of register rename lookups that rename has made
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.int_rename_lookups 2853766100 # Number of integer rename lookups
system.cpu.icache.demand_accesses 170870865 # number of demand (read+write) accesses system.cpu.rename.fp_rename_lookups 33670209 # Number of floating rename lookups
system.cpu.icache.demand_avg_miss_latency 35272.495756 # average overall miss latency system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.icache.demand_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency system.cpu.rename.UndoneMaps 182047108 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_hits 170869098 # number of demand (read+write) hits system.cpu.rename.serializingInsts 3085415 # count of serializing insts renamed
system.cpu.icache.demand_miss_latency 62326500 # number of demand (read+write) miss cycles system.cpu.rename.tempSerializingInsts 3085429 # count of temporary serializing insts renamed
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.rename.skidInsts 378978234 # count of insts added to the skid buffer
system.cpu.icache.demand_misses 1767 # number of demand (read+write) misses system.cpu.memDep0.insertedLoads 461157304 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_hits 470 # number of demand (read+write) MSHR hits system.cpu.memDep0.insertedStores 187023629 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_latency 45468000 # number of demand (read+write) MSHR miss cycles system.cpu.memDep0.conflictingLoads 386274628 # Number of conflicting loads.
system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses system.cpu.memDep0.conflictingStores 159918062 # Number of conflicting stores.
system.cpu.icache.demand_mshr_misses 1297 # number of demand (read+write) MSHR misses system.cpu.iq.iqInstsAdded 1585635160 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.iq.iqNonSpecInstsAdded 3099558 # Number of non-speculative instructions added to the IQ
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.iq.iqInstsIssued 1482248202 # Number of instructions issued
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqSquashedInstsIssued 280896 # Number of squashed instructions issued
system.cpu.icache.occ_blocks::0 1047.623620 # Average occupied blocks per context system.cpu.iq.iqSquashedInstsExamined 182707220 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.occ_percent::0 0.511535 # Average percentage of cache occupancy system.cpu.iq.iqSquashedOperandsExamined 240691130 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_accesses 170870865 # number of overall (read+write) accesses system.cpu.iq.iqSquashedNonSpecRemoved 855887 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_avg_miss_latency 35272.495756 # average overall miss latency system.cpu.iq.issued_per_cycle::samples 1164465958 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency system.cpu.iq.issued_per_cycle::mean 1.272900 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.issued_per_cycle::stdev 1.148645 # Number of insts issued each cycle
system.cpu.icache.overall_hits 170869098 # number of overall hits system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 62326500 # number of overall miss cycles system.cpu.iq.issued_per_cycle::0 309299023 26.56% 26.56% # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::1 465738912 40.00% 66.56% # Number of insts issued each cycle
system.cpu.icache.overall_misses 1767 # number of overall misses system.cpu.iq.issued_per_cycle::2 229120955 19.68% 86.23% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 470 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::3 104114644 8.94% 95.17% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 45468000 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::4 41468820 3.56% 98.74% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::5 8912789 0.77% 99.50% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 1297 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::6 5349021 0.46% 99.96% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::7 304255 0.03% 99.99% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::8 157539 0.01% 100.00% # Number of insts issued each cycle
system.cpu.icache.replacements 159 # number of replacements system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 1296 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.icache.tagsinuse 1047.623620 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::total 1164465958 # Number of insts issued each cycle
system.cpu.icache.total_refs 170869098 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 370544 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 5675287 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 89603944 # Number of branches executed
system.cpu.iew.exec_nop 100373819 # number of nop insts executed
system.cpu.iew.exec_rate 1.267070 # Inst execution rate
system.cpu.iew.exec_refs 591399205 # number of memory reference insts executed
system.cpu.iew.exec_stores 170154785 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 2507924 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 461157302 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 4553877 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 187022162 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1689106884 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 421244420 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6318503 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1475928628 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 66196 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 58644458 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 20174020 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 1209973999 # num instructions consuming a value
system.cpu.iew.wb_count 1473173854 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.961076 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1162877329 # num instructions producing a value
system.cpu.iew.wb_rate 1.264705 # insts written-back per cycle
system.cpu.iew.wb_sent 1474297623 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 1997794756 # number of integer regfile reads
system.cpu.int_regfile_writes 1296594839 # number of integer regfile writes
system.cpu.ipc 1.206697 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.206697 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1482247131 # Type of FU issued
system.cpu.iq.fp_alu_accesses 9142959 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 17762219 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 8523024 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 9165283 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 3391020 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 187446 5.53% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available
@ -339,139 +131,347 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.85% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 2748470 81.06% 92.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 240369 7.09% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 1476495192 # Number of integer alu accesses system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.int_inst_queue_reads 4114870575 # Number of integer instruction queue reads system.cpu.iq.FU_type_0::IntAlu 883945192 59.64% 59.64% # Type of FU issued
system.cpu.iq.int_inst_queue_wakeup_accesses 1464650830 # Number of integer instruction queue wakeup accesses system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.int_inst_queue_writes 1762732094 # Number of integer instruction queue writes system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.iqInstsAdded 1585633508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.FU_type_0::FloatAdd 2632003 0.18% 59.81% # Type of FU issued
system.cpu.iq.iqInstsIssued 1482247131 # Number of instructions issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.iqNonSpecInstsAdded 3099557 # Number of non-speculative instructions added to the IQ system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.iqSquashedInstsExamined 182705519 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.iqSquashedInstsIssued 281937 # Number of squashed instructions issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.iqSquashedNonSpecRemoved 855886 # Number of squashed non-spec instructions that were removed system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.iqSquashedOperandsExamined 240684944 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::samples 1164465575 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::mean 1.272899 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.issued_per_cycle::total 1164465575 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.rate 1.272494 # Inst issue rate system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses) system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444 # average ReadExReq miss latency system.cpu.iq.FU_type_0::MemRead 424002994 28.61% 88.42% # Type of FU issued
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026 # average ReadExReq mshr miss latency system.cpu.iq.FU_type_0::MemWrite 171668013 11.58% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_hits 207600 # number of ReadExReq hits system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_miss_latency 2079988000 # number of ReadExReq miss cycles system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_miss_rate 0.225521 # miss rate for ReadExReq accesses system.cpu.iq.FU_type_0::total 1482248202 # Type of FU issued
system.cpu.l2cache.ReadExReq_misses 60451 # number of ReadExReq misses system.cpu.iq.rate 1.272495 # Inst issue rate
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893368000 # number of ReadExReq MSHR miss cycles system.cpu.iq.fu_busy_cnt 3390497 # FU busy when requested
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225521 # mshr miss rate for ReadExReq accesses system.cpu.iq.fu_busy_rate 0.002287 # FU busy rate (busy events/executed inst)
system.cpu.l2cache.ReadExReq_mshr_misses 60451 # number of ReadExReq MSHR misses system.cpu.iq.int_inst_queue_reads 4114870963 # Number of integer instruction queue reads
system.cpu.l2cache.ReadReq_accesses 214628 # number of ReadReq accesses(hits+misses) system.cpu.iq.int_inst_queue_writes 1762732436 # Number of integer instruction queue writes
system.cpu.l2cache.ReadReq_avg_miss_latency 34037.437678 # average ReadReq miss latency system.cpu.iq.int_inst_queue_wakeup_accesses 1464650831 # Number of integer instruction queue wakeup accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.970916 # average ReadReq mshr miss latency system.cpu.iq.fp_inst_queue_reads 17762792 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9168295 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8523374 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1476495195 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9143504 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 58644460 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 20175487 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 27885774 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2507670 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 128778 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1689108521 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 4553883 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 461157304 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 187023629 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 66282 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 8454 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 670428 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 5675288 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1475929151 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 421244589 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6319051 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 100373803 # number of nop insts executed
system.cpu.iew.exec_refs 591399372 # number of memory reference insts executed
system.cpu.iew.exec_branches 89603944 # Number of branches executed
system.cpu.iew.exec_stores 170154783 # Number of stores executed
system.cpu.iew.exec_rate 1.267070 # Inst execution rate
system.cpu.iew.wb_sent 1474297977 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1473174205 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1162879989 # num instructions producing a value
system.cpu.iew.wb_consumers 1209979019 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.264705 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.961075 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 199492196 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 5339068 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1136580795 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.310530 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.747402 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 402923295 35.45% 35.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 477569254 42.02% 77.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 55696756 4.90% 82.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 97088676 8.54% 90.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 32659153 2.87% 93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 8439015 0.74% 94.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 25679683 2.26% 96.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9814988 0.86% 97.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 26709975 2.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1136580795 # Number of insts commited each cycle
system.cpu.commit.count 1489523295 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 569360986 # Number of memory references committed
system.cpu.commit.loads 402512844 # Number of loads committed
system.cpu.commit.membars 51356 # Number of memory barriers committed
system.cpu.commit.branches 86248929 # Number of branches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 26709975 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2798821441 # The number of ROB reads
system.cpu.rob.rob_writes 3405949800 # The number of ROB writes
system.cpu.timesIdled 11505 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 370573 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.828709 # CPI: Total CPI of All Threads
system.cpu.ipc 1.206696 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.206696 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1997795279 # number of integer regfile reads
system.cpu.int_regfile_writes 1296594841 # number of integer regfile writes
system.cpu.fp_regfile_reads 16957636 # number of floating regfile reads
system.cpu.fp_regfile_writes 10465342 # number of floating regfile writes
system.cpu.misc_regfile_reads 597198734 # number of misc regfile reads
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes
system.cpu.icache.replacements 159 # number of replacements
system.cpu.icache.tagsinuse 1046.779418 # Cycle average of tags in use
system.cpu.icache.total_refs 170868575 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1295 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 131944.845560 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1046.779418 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.511123 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 170868575 # number of ReadReq hits
system.cpu.icache.demand_hits 170868575 # number of demand (read+write) hits
system.cpu.icache.overall_hits 170868575 # number of overall hits
system.cpu.icache.ReadReq_misses 1766 # number of ReadReq misses
system.cpu.icache.demand_misses 1766 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1766 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 62279500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 62279500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 62279500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 170870341 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 170870341 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 170870341 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35265.855040 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35265.855040 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35265.855040 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 470 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 470 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 470 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1296 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1296 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1296 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 45432500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45432500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45432500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35055.941358 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35055.941358 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35055.941358 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 477286 # number of replacements
system.cpu.dcache.tagsinuse 4095.405832 # Cycle average of tags in use
system.cpu.dcache.total_refs 455671846 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 481382 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 946.590953 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 132241000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.405832 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 290645446 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 165025081 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits 455670527 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 455670527 # number of overall hits
system.cpu.dcache.ReadReq_misses 816201 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1821735 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.demand_misses 2637936 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2637936 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 11969600500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28019650157 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency 39989250657 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39989250657 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 291461647 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 458308463 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 458308463 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002800 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.010919 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate 0.005756 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.005756 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 14665.015725 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 15380.749756 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency 15159.295243 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 15159.295243 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 428224 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 602862 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1553699 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 2156561 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 2156561 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 213339 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 268036 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses 481375 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 481375 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1594439500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3497902243 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5092341743 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5092341743 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000732 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001606 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.001050 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001050 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7473.736635 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13050.121040 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10578.741611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10578.741611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 75915 # number of replacements
system.cpu.l2cache.tagsinuse 17662.572587 # Cycle average of tags in use
system.cpu.l2cache.total_refs 467082 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 91426 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.108853 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1959.264776 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15703.307811 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.059792 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.479227 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 180932 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 180932 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1146925500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.156997 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33696 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044743500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156997 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33696 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 428224 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 428224 # number of Writeback hits system.cpu.l2cache.Writeback_hits 428224 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_hits 207600 # number of ReadExReq hits
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.demand_hits 388532 # number of demand (read+write) hits
system.cpu.l2cache.avg_refs 5.108819 # Average number of references to valid blocks. system.cpu.l2cache.overall_hits 388532 # number of overall hits
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.ReadReq_misses 33695 # number of ReadReq misses
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.ReadExReq_misses 60451 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 94146 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 94146 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1146858500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2079993500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3226852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3226852000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 214627 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 428224 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 482678 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 482678 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.156993 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.225521 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.195049 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.195049 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.459415 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.925427 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34274.977163 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34274.977163 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 482679 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34275.266339 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 388532 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3226913500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.195051 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 94147 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2938111500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.195051 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 94147 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 1959.521413 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15703.307498 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.059800 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.479227 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 482679 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34275.266339 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 388532 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3226913500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.195051 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 94147 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2938111500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.195051 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 94147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 75916 # number of replacements
system.cpu.l2cache.sampled_refs 91427 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17662.828910 # Cycle average of tags in use
system.cpu.l2cache.total_refs 467084 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 59282 # number of writebacks system.cpu.l2cache.writebacks 59282 # number of writebacks
system.cpu.memDep0.conflictingLoads 386274637 # Number of conflicting loads. system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.memDep0.conflictingStores 159916794 # Number of conflicting stores. system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.memDep0.insertedLoads 461157302 # Number of loads inserted to the mem dependence unit. system.cpu.l2cache.ReadReq_mshr_misses 33695 # number of ReadReq MSHR misses
system.cpu.memDep0.insertedStores 187022162 # Number of stores inserted to the mem dependence unit. system.cpu.l2cache.ReadExReq_mshr_misses 60451 # number of ReadExReq MSHR misses
system.cpu.misc_regfile_reads 597198570 # number of misc regfile reads system.cpu.l2cache.demand_mshr_misses 94146 # number of demand (read+write) MSHR misses
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes system.cpu.l2cache.overall_mshr_misses 94146 # number of overall MSHR misses
system.cpu.numCycles 1164836119 # number of cpu cycles simulated system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.l2cache.ReadReq_mshr_miss_latency 1044714500 # number of ReadReq MSHR miss cycles
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893375500 # number of ReadExReq MSHR miss cycles
system.cpu.rename.BlockCycles 115497905 # Number of cycles rename is blocking system.cpu.l2cache.demand_mshr_miss_latency 2938090000 # number of demand (read+write) MSHR miss cycles
system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.l2cache.overall_mshr_miss_latency 2938090000 # number of overall MSHR miss cycles
system.cpu.rename.FullRegisterEvents 28107626 # Number of times there has been no free registers system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.rename.IQFullEvents 128337052 # Number of times rename has blocked due to IQ full system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156993 # mshr miss rate for ReadReq accesses
system.cpu.rename.IdleCycles 433132347 # Number of cycles rename is idle system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225521 # mshr miss rate for ReadExReq accesses
system.cpu.rename.LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full system.cpu.l2cache.demand_mshr_miss_rate 0.195049 # mshr miss rate for demand accesses
system.cpu.rename.RenameLookups 2887426636 # Number of register rename lookups that rename has made system.cpu.l2cache.overall_mshr_miss_rate 0.195049 # mshr miss rate for overall accesses
system.cpu.rename.RenamedInsts 1709740875 # Number of instructions processed by rename system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.030420 # average ReadReq mshr miss latency
system.cpu.rename.RenamedOperands 1426816340 # Number of destination operands rename has renamed system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.830094 # average ReadExReq mshr miss latency
system.cpu.rename.RunCycles 325737783 # Number of cycles rename is running system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.804899 # average overall mshr miss latency
system.cpu.rename.SquashCycles 27885594 # Number of cycles rename is squashing system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.804899 # average overall mshr miss latency
system.cpu.rename.UnblockCycles 209164686 # Number of cycles rename is unblocking system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.rename.UndoneMaps 182045888 # Number of HB maps that are undone due to squashing system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.rename.fp_rename_lookups 33660518 # Number of floating rename lookups system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.rename.int_rename_lookups 2853766118 # Number of integer rename lookups system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.rename.serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 3085415 # count of serializing insts renamed
system.cpu.rename.skidInsts 378977297 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 3085429 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 2798818963 # The number of ROB reads
system.cpu.rob.rob_writes 3405946340 # The number of ROB writes
system.cpu.timesIdled 11499 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

10
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simout
Redirecting stderr to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -5,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Apr 21 2011 13:30:37 M5 compiled May 17 2011 12:22:59
M5 started Apr 21 2011 13:30:43 M5 started May 18 2011 08:01:14
M5 executing on maize M5 executing on nadc-0105
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -1066,4 +1068,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 751079230500 because target called exit() Exiting @ tick 750278436000 because target called exit()

828
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,264 +1,142 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 131052 # Simulator instruction rate (inst/s) sim_seconds 0.750278 # Number of seconds simulated
host_mem_usage 215332 # Number of bytes of host memory used sim_ticks 750278436000 # Number of ticks simulated
host_seconds 12372.92 # Real time elapsed on the host
host_tick_rate 60703496 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 180615 # Simulator instruction rate (inst/s)
host_tick_rate 83571906 # Simulator tick rate (ticks/s)
host_mem_usage 250232 # Number of bytes of host memory used
host_seconds 8977.64 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated sim_insts 1621493982 # Number of instructions simulated
sim_seconds 0.751079 # Number of seconds simulated system.cpu.workload.num_syscalls 48 # Number of system calls
sim_ticks 751079230500 # Number of ticks simulated system.cpu.numCycles 1500556873 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 179206646 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 179206646 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 8463551 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 169776881 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 168588435 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 168460210 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 169652659 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 8971423 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.commit.branches 107161579 # Number of branches committed system.cpu.fetch.icacheStallCycles 168643185 # Number of cycles fetch is stalled on an Icache miss
system.cpu.commit.bw_lim_events 11445860 # number cycles where commit BW limit reached system.cpu.fetch.Insts 1398775423 # Number of instructions fetch has processed
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.fetch.Branches 179206646 # Number of branches that fetch encountered
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.fetch.predictedBranches 168588435 # Number of branches that fetch has predicted taken
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards system.cpu.fetch.Cycles 401459368 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit system.cpu.fetch.SquashCycles 14868125 # Number of cycles fetch has spent squashing
system.cpu.commit.committed_per_cycle::samples 1402522347 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.156127 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1402522347 # Number of insts commited each cycle
system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.loads 419042125 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 607228182 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.926404 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 325401931 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10107.251018 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7152.951878 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 325183672 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2205998500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000671 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 218259 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 3345 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1537269500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 214914 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 19574.534314 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10012.304968 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 186952974 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 24137025496 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006552 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1233083 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 982981 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2504097497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 250102 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15974.978853 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1101.331236 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 472140500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 513587988 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18150.803874 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency
system.cpu.dcache.demand_hits 512136646 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 26343023996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002826 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1451342 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 986326 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4041366997 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 465016 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999792 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 512136646 # number of overall hits
system.cpu.dcache.overall_miss_latency 26343023996 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002826 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1451342 # number of overall misses
system.cpu.dcache.overall_mshr_hits 986326 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4041366997 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 465016 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 460920 # number of replacements
system.cpu.dcache.sampled_refs 465016 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.146726 # Cycle average of tags in use
system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 411408 # number of writebacks
system.cpu.decode.BlockedCycles 587921420 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 2472731706 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 429893143 # Number of cycles decode is idle
system.cpu.decode.RunCycles 331529130 # Number of cycles decode is running
system.cpu.decode.SquashCycles 99378480 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 53178654 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched
system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 625222 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1408639601 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 15384200 # Number of cycles fetch has spent squashing system.cpu.fetch.CacheLines 168643185 # Number of cache lines fetched
system.cpu.fetch.branchRate 0.119823 # Number of branch fetches per cycle system.cpu.fetch.IcacheSquashes 821564 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.icacheStallCycles 170058043 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.rateDist::samples 1500265844 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.predictedBranches 168460210 # Number of branches that fetch has predicted taken system.cpu.fetch.rateDist::mean 1.692515 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rate 0.937744 # Number of inst fetches per cycle system.cpu.fetch.rateDist::stdev 3.050179 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 1501900827 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.699260 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.059388 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1104715792 73.55% 73.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 1101846908 73.44% 73.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 26107791 1.74% 75.29% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 25629201 1.71% 75.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14369087 0.96% 76.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 17503252 1.17% 76.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13756932 0.92% 77.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 17259352 1.15% 77.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 30207594 2.01% 79.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 30203070 2.01% 79.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 20132707 1.34% 80.52% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 16882652 1.13% 80.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 34410865 2.29% 82.81% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 34105222 2.27% 82.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 37556252 2.50% 85.31% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 37737433 2.52% 85.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 220643807 14.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 219098754 14.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1501900827 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1500265844 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 12 # number of floating regfile reads system.cpu.fetch.branchRate 0.119427 # Number of branch fetches per cycle
system.cpu.icache.ReadReq_accesses 170058043 # number of ReadReq accesses(hits+misses) system.cpu.fetch.rate 0.932171 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_avg_miss_latency 35240.756303 # average ReadReq miss latency system.cpu.decode.IdleCycles 426619882 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.058688 # average ReadReq mshr miss latency system.cpu.decode.BlockedCycles 588582259 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_hits 170056853 # number of ReadReq hits system.cpu.decode.RunCycles 331774062 # Number of cycles decode is running
system.cpu.icache.ReadReq_miss_latency 41936500 # number of ReadReq miss cycles system.cpu.decode.UnblockCycles 54890410 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses system.cpu.decode.SquashCycles 98399231 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_misses 1190 # number of ReadReq misses system.cpu.decode.DecodedInsts 2463603655 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_hits 321 # number of ReadReq MSHR hits system.cpu.rename.SquashCycles 98399231 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_miss_latency 30694000 # number of ReadReq MSHR miss cycles system.cpu.rename.IdleCycles 490140995 # Number of cycles rename is idle
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.rename.BlockCycles 167797271 # Number of cycles rename is blocking
system.cpu.icache.ReadReq_mshr_misses 869 # number of ReadReq MSHR misses system.cpu.rename.serializeStallCycles 3037 # count of cycles rename stalled for serializing inst
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.RunCycles 309381141 # Number of cycles rename is running
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.UnblockCycles 434544169 # Number of cycles rename is unblocking
system.cpu.icache.avg_refs 195692.581128 # Average number of references to valid blocks. system.cpu.rename.RenamedInsts 2390094348 # Number of instructions processed by rename
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 298397694 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 109374277 # Number of times rename has blocked due to LSQ full
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedOperands 2388910462 # Number of destination operands rename has renamed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.RenameLookups 5790943512 # Number of register rename lookups that rename has made
system.cpu.icache.demand_accesses 170058043 # number of demand (read+write) accesses system.cpu.rename.int_rename_lookups 5790943448 # Number of integer rename lookups
system.cpu.icache.demand_avg_miss_latency 35240.756303 # average overall miss latency system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups
system.cpu.icache.demand_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.icache.demand_hits 170056853 # number of demand (read+write) hits system.cpu.rename.UndoneMaps 770915812 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_miss_latency 41936500 # number of demand (read+write) miss cycles system.cpu.rename.serializingInsts 87 # count of serializing insts renamed
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
system.cpu.icache.demand_misses 1190 # number of demand (read+write) misses system.cpu.rename.skidInsts 713558954 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits system.cpu.memDep0.insertedLoads 613723437 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_latency 30694000 # number of demand (read+write) MSHR miss cycles system.cpu.memDep0.insertedStores 250366407 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.memDep0.conflictingLoads 539421468 # Number of conflicting loads.
system.cpu.icache.demand_mshr_misses 869 # number of demand (read+write) MSHR misses system.cpu.memDep0.conflictingStores 206415389 # Number of conflicting stores.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.iq.iqInstsAdded 2337617045 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqInstsIssued 1854722734 # Number of instructions issued
system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context system.cpu.iq.iqSquashedInstsIssued 196953 # Number of squashed instructions issued
system.cpu.icache.occ_percent::0 0.387535 # Average percentage of cache occupancy system.cpu.iq.iqSquashedInstsExamined 715983422 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses system.cpu.iq.iqSquashedOperandsExamined 1505792788 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency system.cpu.iq.issued_per_cycle::samples 1500265844 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.issued_per_cycle::mean 1.236263 # Number of insts issued each cycle
system.cpu.icache.overall_hits 170056853 # number of overall hits system.cpu.iq.issued_per_cycle::stdev 1.216770 # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 41936500 # number of overall miss cycles system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::0 461494018 30.76% 30.76% # Number of insts issued each cycle
system.cpu.icache.overall_misses 1190 # number of overall misses system.cpu.iq.issued_per_cycle::1 582014055 38.79% 69.55% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 321 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::2 214930558 14.33% 83.88% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 30694000 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::3 153972669 10.26% 94.14% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::4 64799231 4.32% 98.46% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 869 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::5 17691341 1.18% 99.64% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::6 4397619 0.29% 99.94% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::7 840611 0.06% 99.99% # Number of insts issued each cycle
system.cpu.icache.replacements 11 # number of replacements system.cpu.iq.issued_per_cycle::8 125742 0.01% 100.00% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 869 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.tagsinuse 793.670730 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.icache.total_refs 170056853 # Total number of references to valid blocks. system.cpu.iq.issued_per_cycle::total 1500265844 # Number of insts issued each cycle
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iq.fu_full::IntAlu 159647 3.75% 3.75% # attempts to use FU when none available
system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iq.fu_full::IntMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute system.cpu.iq.fu_full::IntDiv 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.exec_branches 111429178 # Number of branches executed system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.exec_rate 1.227514 # Inst execution rate system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.exec_refs 636597814 # number of memory reference insts executed system.cpu.iq.fu_full::FloatMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.exec_stores 191695864 # Number of stores executed system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewDispSquashedInsts 312936 # Number of squashed instructions skipped by dispatch system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewDispStoreInsts 250798855 # Number of dispatched store instructions system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewDispatchedInsts 2343198083 # Number of instructions dispatched to IQ system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewExecLoadInsts 444901950 # Number of load instructions executed system.cpu.iq.fu_full::SimdMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewExecSquashedInsts 13067063 # Number of squashed instructions skipped in execute system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewExecutedInsts 1843921293 # Number of executed instructions system.cpu.iq.fu_full::SimdShift 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewIQFullEvents 56293 # Number of times the IQ has become full, causing a stall system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.forwLoads 119484333 # Number of loads that had data forwarded from stores system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.memOrderViolation 6399400 # Number of memory ordering violations system.cpu.iq.fu_full::MemRead 3486871 81.91% 85.66% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled system.cpu.iq.fu_full::MemWrite 610438 14.34% 100.00% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.squashedLoads 196809249 # Number of loads squashed system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.squashedStores 62612798 # Number of stores squashed system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations system.cpu.iq.FU_type_0::No_OpClass 27575645 1.49% 1.49% # Type of FU issued
system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly system.cpu.iq.FU_type_0::IntAlu 1184540758 63.87% 65.35% # Type of FU issued
system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 2082700302 # num instructions consuming a value
system.cpu.iew.wb_count 1838995466 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.683970 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1424504384 # num instructions producing a value
system.cpu.iew.wb_rate 1.224235 # insts written-back per cycle
system.cpu.iew.wb_sent 1842743630 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads
system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes
system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued
@ -287,179 +165,301 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 450487645 24.29% 89.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 192118686 10.36% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1856988356 # Type of FU issued system.cpu.iq.FU_type_0::total 1854722734 # Type of FU issued
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses system.cpu.iq.rate 1.236023 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4256956 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002295 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5214165186 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3059990828 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1837811582 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 4273878 # FU busy when requested system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst) system.cpu.iq.int_alu_accesses 1831404026 # Number of integer alu accesses
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
system.cpu.iq.fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.forwLoads 117971084 # Number of loads that had data forwarded from stores
system.cpu.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.squashedLoads 194681312 # Number of loads squashed
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.ignoredResponses 16091 # Number of memory responses ignored because the instruction is squashed
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.memOrderViolation 6391116 # Number of memory ordering violations
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.squashedStores 62180350 # Number of stores squashed
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.lsq.thread0.cacheBlocked 30252 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewSquashCycles 98399231 # Number of cycles IEW is squashing
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewBlockCycles 1363305 # Number of cycles IEW is blocking
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewUnblockCycles 110880 # Number of cycles IEW is unblocking
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewDispatchedInsts 2337617123 # Number of instructions dispatched to IQ
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewDispSquashedInsts 338195 # Number of squashed instructions skipped by dispatch
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewDispLoadInsts 613723437 # Number of dispatched load instructions
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewDispStoreInsts 250366407 # Number of dispatched store instructions
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewIQFullEvents 56702 # Number of times the IQ has become full, causing a stall
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.memOrderViolationEvents 6391116 # Number of memory order violations
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.predictedTakenIncorrect 4450206 # Number of branches that were predicted taken incorrectly
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.predictedNotTakenIncorrect 4153743 # Number of branches that were predicted not taken incorrectly
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.branchMispredicts 8603949 # Number of branch mispredicts detected at execute
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewExecutedInsts 1842187665 # Number of executed instructions
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewExecLoadInsts 444314021 # Number of load instructions executed
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.iewExecSquashedInsts 12535069 # Number of squashed instructions skipped in execute
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iq.fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iq.fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available system.cpu.iew.exec_refs 636013673 # number of memory reference insts executed
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iew.exec_branches 111427506 # Number of branches executed
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iew.exec_stores 191699652 # Number of stores executed
system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses system.cpu.iew.exec_rate 1.227669 # Inst execution rate
system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads system.cpu.iew.wb_sent 1840965230 # cumulative count of insts sent to commit
system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses system.cpu.iew.wb_count 1837811594 # cumulative count of insts written-back
system.cpu.iq.int_inst_queue_writes 3071160852 # Number of integer instruction queue writes system.cpu.iew.wb_producers 1424401809 # num instructions producing a value
system.cpu.iq.iqInstsAdded 2343198002 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iew.wb_consumers 2083960582 # num instructions consuming a value
system.cpu.iq.iqInstsIssued 1856988356 # Number of instructions issued system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ system.cpu.iew.wb_rate 1.224753 # insts written-back per cycle
system.cpu.iq.iqSquashedInstsExamined 721564206 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iew.wb_fanout 0.683507 # average fanout of values written-back
system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph system.cpu.commit.commitSquashedInsts 716132515 # The number of squashed insts skipped by commit
system.cpu.iq.issued_per_cycle::samples 1501900827 # Number of insts issued each cycle system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.iq.issued_per_cycle::mean 1.236425 # Number of insts issued each cycle system.cpu.commit.branchMispredicts 8463578 # The number of times a branch was mispredicted
system.cpu.iq.issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::samples 1401866613 # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::mean 1.156668 # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::stdev 1.378442 # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::0 520031376 37.10% 37.10% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::1 533018726 38.02% 75.12% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::2 125308330 8.94% 84.06% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::3 139235246 9.93% 93.99% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::4 43288203 3.09% 97.08% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::5 23453801 1.67% 98.75% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::6 4331063 0.31% 99.06% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::7 1854281 0.13% 99.19% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::8 11345587 0.81% 100.00% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::total 1501900827 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.iq.rate 1.236213 # Inst issue rate system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses) system.cpu.commit.committed_per_cycle::total 1401866613 # Number of insts commited each cycle
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.l2cache.ReadExReq_hits 191287 # number of ReadExReq hits system.cpu.commit.refs 607228182 # Number of memory references committed
system.cpu.l2cache.ReadExReq_miss_latency 2024064500 # number of ReadExReq miss cycles system.cpu.commit.loads 419042125 # Number of loads committed
system.cpu.l2cache.ReadExReq_miss_rate 0.235198 # miss rate for ReadExReq accesses system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.l2cache.ReadExReq_misses 58826 # number of ReadExReq misses system.cpu.commit.branches 107161579 # Number of branches committed
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832767000 # number of ReadExReq MSHR miss cycles system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235198 # mshr miss rate for ReadExReq accesses system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.l2cache.ReadExReq_mshr_misses 58826 # number of ReadExReq MSHR misses system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.l2cache.ReadReq_accesses 215772 # number of ReadReq accesses(hits+misses) system.cpu.commit.bw_lim_events 11345587 # number cycles where commit BW limit reached
system.cpu.l2cache.ReadReq_avg_miss_latency 34136.783762 # average ReadReq miss latency system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.222249 # average ReadReq mshr miss latency system.cpu.rob.rob_reads 3728147523 # The number of ROB reads
system.cpu.l2cache.ReadReq_hits 182665 # number of ReadReq hits system.cpu.rob.rob_writes 4773653528 # The number of ROB writes
system.cpu.l2cache.ReadReq_miss_latency 1130166500 # number of ReadReq miss cycles system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.l2cache.ReadReq_miss_rate 0.153435 # miss rate for ReadReq accesses system.cpu.idleCycles 291029 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.l2cache.ReadReq_misses 33107 # number of ReadReq misses system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.l2cache.ReadReq_mshr_miss_latency 1026523000 # number of ReadReq MSHR miss cycles system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153435 # mshr miss rate for ReadReq accesses system.cpu.cpi 0.925416 # CPI: Cycles Per Instruction
system.cpu.l2cache.ReadReq_mshr_misses 33107 # number of ReadReq MSHR misses system.cpu.cpi_total 0.925416 # CPI: Total CPI of All Threads
system.cpu.l2cache.Writeback_accesses 411408 # number of Writeback accesses(hits+misses) system.cpu.ipc 1.080595 # IPC: Instructions Per Cycle
system.cpu.l2cache.Writeback_hits 411408 # number of Writeback hits system.cpu.ipc_total 1.080595 # IPC: Total IPC of All Threads
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked system.cpu.int_regfile_reads 3235784294 # number of integer regfile reads
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.int_regfile_writes 1830729236 # number of integer regfile writes
system.cpu.l2cache.avg_refs 5.099879 # Average number of references to valid blocks. system.cpu.fp_regfile_reads 12 # number of floating regfile reads
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.misc_regfile_reads 930213220 # number of misc regfile reads
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 793.330591 # Cycle average of tags in use
system.cpu.icache.total_refs 168641986 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 875 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 192733.698286 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 793.330591 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.387368 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 168641986 # number of ReadReq hits
system.cpu.icache.demand_hits 168641986 # number of demand (read+write) hits
system.cpu.icache.overall_hits 168641986 # number of overall hits
system.cpu.icache.ReadReq_misses 1199 # number of ReadReq misses
system.cpu.icache.demand_misses 1199 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1199 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 42201000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 42201000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 42201000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 168643185 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 168643185 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 168643185 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35196.830692 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35196.830692 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35196.830692 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 324 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 324 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 875 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 875 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 875 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 30921000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 30921000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 30921000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35338.285714 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 460957 # number of replacements
system.cpu.dcache.tagsinuse 4095.145869 # Cycle average of tags in use
system.cpu.dcache.total_refs 513034277 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 465053 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1103.173782 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317696000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.145869 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 326108931 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 186925346 # number of WriteReq hits
system.cpu.dcache.demand_hits 513034277 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 513034277 # number of overall hits
system.cpu.dcache.ReadReq_misses 218266 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1260711 # number of WriteReq misses
system.cpu.dcache.demand_misses 1478977 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1478977 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2205272500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 24390827496 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 26596099996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 26596099996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 326327197 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 514513254 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 514513254 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000669 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.006699 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.002875 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002875 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 10103.600652 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 19346.882431 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 17982.767816 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 17982.767816 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 474736000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29560 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16060.081191 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 411400 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 3331 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1010593 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1013924 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1013924 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 214935 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 250118 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 465053 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 465053 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1536673000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2518183497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4054856497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4054856497 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7149.477749 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10067.981901 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73679 # number of replacements
system.cpu.l2cache.tagsinuse 18021.980204 # Cycle average of tags in use
system.cpu.l2cache.total_refs 455469 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.101465 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1918.737195 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16103.243009 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058555 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.491432 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 182682 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 411400 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 191297 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 373979 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 373979 # number of overall hits
system.cpu.l2cache.ReadReq_misses 33118 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58831 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91949 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91949 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1130130500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2026415500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3156546000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3156546000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 215800 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 411400 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 250128 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 465928 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 465928 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.153466 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235204 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.197346 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.197346 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34124.358355 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34444.689024 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34329.312989 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34329.312989 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 465885 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34310.106273 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 373952 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3154231000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.197330 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 91933 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2859290000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.197330 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 91933 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.writebacks 58539 # number of writebacks
system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058491 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.491164 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 373952 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3154231000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.197330 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 91933 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2859290000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_misses 33118 # number of ReadReq MSHR misses
system.cpu.l2cache.overall_mshr_miss_rate 0.197330 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_mshr_misses 58831 # number of ReadExReq MSHR misses
system.cpu.l2cache.overall_mshr_misses 91933 # number of overall MSHR misses system.cpu.l2cache.demand_mshr_misses 91949 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_misses 91949 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 73660 # number of replacements system.cpu.l2cache.ReadReq_mshr_miss_latency 1026873000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.sampled_refs 89268 # Sample count of references to valid blocks. system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832918500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2859791500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2859791500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153466 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235204 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.197346 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.197346 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.491938 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.657731 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18011.074755 # Cycle average of tags in use system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.total_refs 455256 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 58532 # number of writebacks
system.cpu.memDep0.conflictingLoads 528261825 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 206728085 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 615851374 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 250798855 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 931071836 # number of misc regfile reads
system.cpu.numCycles 1502158462 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 169288978 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 298516669 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 493321936 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 5808956116 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 2397077126 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 2395694665 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 310095488 # Number of cycles rename is running
system.cpu.rename.SquashCycles 99378480 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 429812969 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 777700015 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 5808956052 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 2976 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 89 # count of serializing insts renamed
system.cpu.rename.skidInsts 706930007 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 89 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3734283918 # The number of ROB reads
system.cpu.rob.rob_writes 4785794667 # The number of ROB writes
system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

2
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
View file

@ -22,8 +22,6 @@ warn: instruction 'mcr icimvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb For more information see: http://www.m5sim.org/warn/21b09adb
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
For more information see: http://www.m5sim.org/warn/7998f2ea
warn: instruction 'mcr bpiall' unimplemented warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb For more information see: http://www.m5sim.org/warn/21b09adb
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors

8
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -7,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 15:43:04 M5 compiled May 16 2011 21:41:16
M5 started May 4 2011 15:43:52 M5 started May 16 2011 21:43:01
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/alisai01/dist/binaries/vmlinux.arm info: kernel located at: /arm/scratch/alisai01/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 82034111500 because m5_exit instruction encountered Exiting @ tick 81956970500 because m5_exit instruction encountered

1394
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 15:10:15 M5 started May 16 2011 18:02:55
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -29,4 +29,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 38285728000 because target called exit() Exiting @ tick 38330782000 because target called exit()

952
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,299 +1,189 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 204577 # Simulator instruction rate (inst/s) sim_seconds 0.038331 # Number of seconds simulated
host_mem_usage 394692 # Number of bytes of host memory used sim_ticks 38330782000 # Number of ticks simulated
host_seconds 446.04 # Real time elapsed on the host
host_tick_rate 85834347 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50765 # Simulator instruction rate (inst/s)
host_tick_rate 21324746 # Simulator tick rate (ticks/s)
host_mem_usage 388132 # Number of bytes of host memory used
host_seconds 1797.48 # Real time elapsed on the host
sim_insts 91249905 # Number of instructions simulated sim_insts 91249905 # Number of instructions simulated
sim_seconds 0.038286 # Number of seconds simulated
sim_ticks 38285728000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 23530821 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 24877982 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 12905 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1726717 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 22205827 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 27600817 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 100979 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 1707487 # The number of times a branch was mispredicted
system.cpu.commit.branches 18722470 # Number of branches committed
system.cpu.commit.bw_lim_events 3914130 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 27309497 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 72214525 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.263769 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.025482 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 36127600 50.03% 50.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18090116 25.05% 75.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 6155866 8.52% 83.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4484410 6.21% 89.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2045917 2.83% 92.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 550531 0.76% 93.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 763612 1.06% 94.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 82343 0.11% 94.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3914130 5.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 72214525 # Number of insts commited each cycle
system.cpu.commit.count 91262514 # Number of instructions committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.int_insts 72533318 # Number of committed integer instructions.
system.cpu.commit.loads 22575876 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.refs 27322629 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 91249905 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated
system.cpu.cpi 0.839140 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.839140 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 6778 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 6771 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.001033 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 25525235 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5595.134205 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2527.282218 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 24493235 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5774178500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.040431 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1032000 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 119171 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2306976500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035762 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 912829 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 27661.201792 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30532.344047 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 4581531 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4244611415 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.032408 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 153450 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 118821 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1057304542 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007313 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 34629 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2864.324268 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 30.700427 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 8126 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 23275499 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 30260216 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 8451.465616 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3550.849792 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29074766 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10018789915 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.039175 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1185450 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 237992 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3364281042 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.031310 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 947458 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 3486.280912 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.851143 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 30260216 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 8451.465616 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3550.849792 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 29074766 # number of overall hits
system.cpu.dcache.overall_miss_latency 10018789915 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.039175 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1185450 # number of overall misses
system.cpu.dcache.overall_mshr_hits 237992 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3364281042 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.031310 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 947458 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 943361 # number of replacements
system.cpu.dcache.sampled_refs 947457 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3486.280912 # Cycle average of tags in use
system.cpu.dcache.total_refs 29087334 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 16275855000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 942852 # number of writebacks
system.cpu.decode.BlockedCycles 10213263 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 32161 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 4330029 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 129908076 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 30506430 # Number of cycles decode is idle
system.cpu.decode.RunCycles 31240805 # Number of cycles decode is running
system.cpu.decode.SquashCycles 4327396 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 33218 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 254026 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 27600817 # Number of branches that fetch encountered system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.fetch.CacheLines 14528959 # Number of cache lines fetched system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.fetch.Cycles 32560436 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.fetch.IcacheSquashes 362446 # Number of outstanding Icache misses that were squashed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.fetch.Insts 132910862 # Number of instructions fetch has processed system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.fetch.SquashCycles 1860393 # Number of cycles fetch has spent squashing system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.fetch.branchRate 0.360458 # Number of branch fetches per cycle system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.fetch.icacheStallCycles 14528959 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.fetch.predictedBranches 23631800 # Number of branches that fetch has predicted taken system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.fetch.rate 1.735776 # Number of inst fetches per cycle system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.fetch.rateDist::samples 76541920 # Number of instructions fetched each cycle (Total) system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.fetch.rateDist::mean 1.751769 # Number of instructions fetched each cycle (Total) system.cpu.dtb.hits 0 # DTB hits
system.cpu.fetch.rateDist::stdev 2.650338 # Number of instructions fetched each cycle (Total) system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 76661565 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 27657644 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 22240511 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1744604 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 24744282 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 23393916 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 124718 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 12906 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14552899 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 133105183 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27657644 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23518634 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 32520380 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1878354 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 14552899 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 370142 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 76631921 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.753228 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.654795 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 44039302 57.54% 57.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 44169594 57.64% 57.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6026139 7.87% 65.41% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 6017071 7.85% 65.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6234278 8.14% 73.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6194245 8.08% 73.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4503549 5.88% 79.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 4415007 5.76% 79.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3291793 4.30% 83.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 3274566 4.27% 83.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1400372 1.83% 85.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1452193 1.90% 85.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1662749 2.17% 87.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 1693941 2.21% 87.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3136974 4.10% 91.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 3142647 4.10% 91.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6246764 8.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 6272657 8.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 76541920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 76631921 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 60 # number of floating regfile reads system.cpu.fetch.branchRate 0.360776 # Number of branch fetches per cycle
system.cpu.fp_regfile_writes 46 # number of floating regfile writes system.cpu.fetch.rate 1.736270 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_accesses 14528959 # number of ReadReq accesses(hits+misses) system.cpu.decode.IdleCycles 30588008 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_miss_latency 36006.674757 # average ReadReq miss latency system.cpu.decode.BlockedCycles 10266300 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34472.834068 # average ReadReq mshr miss latency system.cpu.decode.RunCycles 31174404 # Number of cycles decode is running
system.cpu.icache.ReadReq_hits 14528135 # number of ReadReq hits system.cpu.decode.UnblockCycles 260454 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_latency 29669500 # number of ReadReq miss cycles system.cpu.decode.SquashCycles 4342755 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses system.cpu.decode.BranchResolved 4341355 # Number of times decode resolved a branch
system.cpu.icache.ReadReq_misses 824 # number of ReadReq misses system.cpu.decode.BranchMispred 41083 # Number of times decode detected a branch misprediction
system.cpu.icache.ReadReq_mshr_hits 143 # number of ReadReq MSHR hits system.cpu.decode.DecodedInsts 130094148 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_latency 23476000 # number of ReadReq MSHR miss cycles system.cpu.decode.SquashedInsts 33304 # Number of squashed instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses system.cpu.rename.SquashCycles 4342755 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_misses 681 # number of ReadReq MSHR misses system.cpu.rename.IdleCycles 31960440 # Number of cycles rename is idle
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.BlockCycles 537193 # Number of cycles rename is blocking
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.serializeStallCycles 8162537 # count of cycles rename stalled for serializing inst
system.cpu.icache.avg_refs 21364.904412 # Average number of references to valid blocks. system.cpu.rename.RunCycles 30023248 # Number of cycles rename is running
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.UnblockCycles 1605748 # Number of cycles rename is unblocking
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedInsts 125609145 # Number of instructions processed by rename
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 50871 # Number of times rename has blocked due to IQ full
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.LSQFullEvents 833181 # Number of times rename has blocked due to LSQ full
system.cpu.icache.demand_accesses 14528959 # number of demand (read+write) accesses system.cpu.rename.FullRegisterEvents 20 # Number of times there has been no free registers
system.cpu.icache.demand_avg_miss_latency 36006.674757 # average overall miss latency system.cpu.rename.RenamedOperands 146281053 # Number of destination operands rename has renamed
system.cpu.icache.demand_avg_mshr_miss_latency 34472.834068 # average overall mshr miss latency system.cpu.rename.RenameLookups 547382815 # Number of register rename lookups that rename has made
system.cpu.icache.demand_hits 14528135 # number of demand (read+write) hits system.cpu.rename.int_rename_lookups 547382254 # Number of integer rename lookups
system.cpu.icache.demand_miss_latency 29669500 # number of demand (read+write) miss cycles system.cpu.rename.fp_rename_lookups 561 # Number of floating rename lookups
system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed
system.cpu.icache.demand_misses 824 # number of demand (read+write) misses system.cpu.rename.UndoneMaps 38851577 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_mshr_hits 143 # number of demand (read+write) MSHR hits system.cpu.rename.serializingInsts 673626 # count of serializing insts renamed
system.cpu.icache.demand_mshr_miss_latency 23476000 # number of demand (read+write) MSHR miss cycles system.cpu.rename.tempSerializingInsts 677053 # count of temporary serializing insts renamed
system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses system.cpu.rename.skidInsts 5163872 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_misses 681 # number of demand (read+write) MSHR misses system.cpu.memDep0.insertedLoads 29426504 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.memDep0.insertedStores 6065519 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.memDep0.conflictingLoads 977286 # Number of conflicting loads.
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.memDep0.conflictingStores 410445 # Number of conflicting stores.
system.cpu.icache.occ_blocks::0 570.381562 # Average occupied blocks per context system.cpu.iq.iqInstsAdded 117966564 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.occ_percent::0 0.278507 # Average percentage of cache occupancy system.cpu.iq.iqNonSpecInstsAdded 652219 # Number of non-speculative instructions added to the IQ
system.cpu.icache.overall_accesses 14528959 # number of overall (read+write) accesses system.cpu.iq.iqInstsIssued 107299468 # Number of instructions issued
system.cpu.icache.overall_avg_miss_latency 36006.674757 # average overall miss latency system.cpu.iq.iqSquashedInstsIssued 25775 # Number of squashed instructions issued
system.cpu.icache.overall_avg_mshr_miss_latency 34472.834068 # average overall mshr miss latency system.cpu.iq.iqSquashedInstsExamined 24675448 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.iqSquashedOperandsExamined 62409285 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_hits 14528135 # number of overall hits system.cpu.iq.iqSquashedNonSpecRemoved 97813 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_miss_latency 29669500 # number of overall miss cycles system.cpu.iq.issued_per_cycle::samples 76631921 # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::mean 1.400193 # Number of insts issued each cycle
system.cpu.icache.overall_misses 824 # number of overall misses system.cpu.iq.issued_per_cycle::stdev 1.609861 # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 143 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 23476000 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::0 31086016 40.57% 40.57% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::1 16895448 22.05% 62.61% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 681 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::2 11625629 15.17% 77.78% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::3 7628942 9.96% 87.74% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::4 5191089 6.77% 94.51% # Number of insts issued each cycle
system.cpu.icache.replacements 2 # number of replacements system.cpu.iq.issued_per_cycle::5 2275199 2.97% 97.48% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 680 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::6 1510567 1.97% 99.45% # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::7 290065 0.38% 99.83% # Number of insts issued each cycle
system.cpu.icache.tagsinuse 570.381562 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::8 128966 0.17% 100.00% # Number of insts issued each cycle
system.cpu.icache.total_refs 14528135 # Total number of references to valid blocks. system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.idleCycles 29537 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iq.issued_per_cycle::total 76631921 # Number of insts issued each cycle
system.cpu.iew.branchMispredicts 1811010 # Number of branch mispredicts detected at execute system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iew.exec_branches 21021161 # Number of branches executed system.cpu.iq.fu_full::IntAlu 155894 31.11% 31.11% # attempts to use FU when none available
system.cpu.iew.exec_nop 38671 # number of nop insts executed system.cpu.iq.fu_full::IntMult 27 0.01% 31.11% # attempts to use FU when none available
system.cpu.iew.exec_rate 1.370820 # Inst execution rate system.cpu.iq.fu_full::IntDiv 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.exec_refs 31258880 # number of memory reference insts executed system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.exec_stores 5296884 # Number of stores executed system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewBlockCycles 92844 # Number of cycles IEW is blocking system.cpu.iq.fu_full::FloatMult 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewDispLoadInsts 29388831 # Number of dispatched load instructions system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewDispNonSpecInsts 647702 # Number of dispatched non-speculative instructions system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewDispSquashedInsts 633555 # Number of squashed instructions skipped by dispatch system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewDispStoreInsts 6085547 # Number of dispatched store instructions system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewDispatchedInsts 118572043 # Number of instructions dispatched to IQ system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewExecLoadInsts 25961996 # Number of load instructions executed system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewExecSquashedInsts 2334217 # Number of squashed instructions skipped in execute system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewExecutedInsts 104965675 # Number of executed instructions system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewIQFullEvents 21340 # Number of times the IQ has become full, causing a stall system.cpu.iq.fu_full::SimdMult 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewLSQFullEvents 243 # Number of times the LSQ has become full, causing a stall system.cpu.iq.fu_full::SimdShift 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewSquashCycles 4327396 # Number of cycles IEW is squashing system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.iewUnblockCycles 27063 # Number of cycles IEW is unblocking system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.cacheBlocked 30520 # Number of times an access to memory failed due to the cache being blocked system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.forwLoads 260518 # Number of loads that had data forwarded from stores system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.ignoredResponses 7496 # Number of memory responses ignored because the instruction is squashed system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.memOrderViolation 117715 # Number of memory ordering violations system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.squashedLoads 6812954 # Number of loads squashed system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iew.lsq.thread0.squashedStores 1338794 # Number of stores squashed system.cpu.iq.fu_full::MemRead 83070 16.58% 47.69% # attempts to use FU when none available
system.cpu.iew.memOrderViolationEvents 117715 # Number of memory order violations system.cpu.iq.fu_full::MemWrite 262134 52.31% 100.00% # attempts to use FU when none available
system.cpu.iew.predictedNotTakenIncorrect 241876 # Number of branches that were predicted not taken incorrectly system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iew.predictedTakenIncorrect 1569134 # Number of branches that were predicted taken incorrectly system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iew.wb_consumers 95054189 # num instructions consuming a value
system.cpu.iew.wb_count 102978657 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.626333 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 59535555 # num instructions producing a value
system.cpu.iew.wb_rate 1.344870 # insts written-back per cycle
system.cpu.iew.wb_sent 103397813 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 499543161 # number of integer regfile reads
system.cpu.int_regfile_writes 121465311 # number of integer regfile writes
system.cpu.ipc 1.191696 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.191696 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 75293930 70.17% 70.17% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 75289326 70.17% 70.17% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10513 0.01% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10516 0.01% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.18% # Type of FU issued
@ -321,210 +211,320 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 70.18% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26527925 24.72% 94.90% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 26536591 24.73% 94.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5467485 5.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 5462996 5.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 107299892 # Type of FU issued system.cpu.iq.FU_type_0::total 107299468 # Type of FU issued
system.cpu.iq.fp_alu_accesses 69 # Number of floating point alu accesses system.cpu.iq.rate 1.399651 # Inst issue rate
system.cpu.iq.fu_busy_cnt 501125 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004670 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 291757623 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 143406422 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102963471 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 134 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 134 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 92 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 92 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 522807 # FU busy when requested system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fu_busy_rate 0.004872 # FU busy rate (busy events/executed inst) system.cpu.iq.int_alu_accesses 107800524 # Number of integer alu accesses
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fp_alu_accesses 69 # Number of floating point alu accesses
system.cpu.iq.fu_full::IntAlu 178340 34.11% 34.11% # attempts to use FU when none available system.cpu.iew.lsq.thread0.forwLoads 260883 # Number of loads that had data forwarded from stores
system.cpu.iq.fu_full::IntMult 27 0.01% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.squashedLoads 6850627 # Number of loads squashed
system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.ignoredResponses 7190 # Number of memory responses ignored because the instruction is squashed
system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.memOrderViolation 117769 # Number of memory ordering violations
system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.squashedStores 1318766 # Number of stores squashed
system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.lsq.thread0.cacheBlocked 30512 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewSquashCycles 4342755 # Number of cycles IEW is squashing
system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewBlockCycles 92075 # Number of cycles IEW is blocking
system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewUnblockCycles 26289 # Number of cycles IEW is unblocking
system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewDispatchedInsts 118657452 # Number of instructions dispatched to IQ
system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewDispSquashedInsts 642589 # Number of squashed instructions skipped by dispatch
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewDispLoadInsts 29426504 # Number of dispatched load instructions
system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewDispStoreInsts 6065519 # Number of dispatched store instructions
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewDispNonSpecInsts 647367 # Number of dispatched non-speculative instructions
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewIQFullEvents 20754 # Number of times the IQ has become full, causing a stall
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewLSQFullEvents 246 # Number of times the LSQ has become full, causing a stall
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.memOrderViolationEvents 117769 # Number of memory order violations
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.predictedTakenIncorrect 1576147 # Number of branches that were predicted taken incorrectly
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.predictedNotTakenIncorrect 244055 # Number of branches that were predicted not taken incorrectly
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.branchMispredicts 1820202 # Number of branch mispredicts detected at execute
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewExecutedInsts 104961161 # Number of executed instructions
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewExecLoadInsts 25966774 # Number of load instructions executed
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.iewExecSquashedInsts 2338307 # Number of squashed instructions skipped in execute
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iq.fu_full::MemRead 83834 16.04% 50.15% # attempts to use FU when none available system.cpu.iew.exec_nop 38669 # number of nop insts executed
system.cpu.iq.fu_full::MemWrite 260606 49.85% 100.00% # attempts to use FU when none available system.cpu.iew.exec_refs 31256963 # number of memory reference insts executed
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iew.exec_branches 21029204 # Number of branches executed
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iew.exec_stores 5290189 # Number of stores executed
system.cpu.iq.int_alu_accesses 107822630 # Number of integer alu accesses system.cpu.iew.exec_rate 1.369150 # Inst execution rate
system.cpu.iq.int_inst_queue_reads 291690830 # Number of integer instruction queue reads system.cpu.iew.wb_sent 103386173 # cumulative count of insts sent to commit
system.cpu.iq.int_inst_queue_wakeup_accesses 102978596 # Number of integer instruction queue wakeup accesses system.cpu.iew.wb_count 102963532 # cumulative count of insts written-back
system.cpu.iq.int_inst_queue_writes 143196091 # Number of integer instruction queue writes system.cpu.iew.wb_producers 59509513 # num instructions producing a value
system.cpu.iq.iqInstsAdded 117880817 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iew.wb_consumers 95068105 # num instructions consuming a value
system.cpu.iq.iqInstsIssued 107299892 # Number of instructions issued system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iq.iqNonSpecInstsAdded 652555 # Number of non-speculative instructions added to the IQ system.cpu.iew.wb_rate 1.343092 # insts written-back per cycle
system.cpu.iq.iqSquashedInstsExamined 24550577 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iew.wb_fanout 0.625967 # average fanout of values written-back
system.cpu.iq.iqSquashedInstsIssued 26453 # Number of squashed instructions issued system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iq.iqSquashedNonSpecRemoved 98149 # Number of squashed non-spec instructions that were removed system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions
system.cpu.iq.iqSquashedOperandsExamined 62032164 # Number of squashed operands that are examined and possibly removed from graph system.cpu.commit.commitSquashedInsts 27394736 # The number of squashed insts skipped by commit
system.cpu.iq.issued_per_cycle::samples 76541920 # Number of insts issued each cycle system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards
system.cpu.iq.issued_per_cycle::mean 1.401845 # Number of insts issued each cycle system.cpu.commit.branchMispredicts 1716455 # The number of times a branch was mispredicted
system.cpu.iq.issued_per_cycle::stdev 1.609057 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::samples 72289167 # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::mean 1.262465 # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::0 30986860 40.48% 40.48% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::stdev 2.025163 # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::1 16938663 22.13% 62.61% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::2 11541566 15.08% 77.69% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::0 36212335 50.09% 50.09% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::3 7661333 10.01% 87.70% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::1 18072720 25.00% 75.09% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::4 5199199 6.79% 94.49% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::2 6165923 8.53% 83.62% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::5 2314331 3.02% 97.52% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::3 4479757 6.20% 89.82% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::6 1500377 1.96% 99.48% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::4 2050310 2.84% 92.66% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::7 273343 0.36% 99.84% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::5 555022 0.77% 93.42% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::8 126248 0.16% 100.00% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::6 748999 1.04% 94.46% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::7 84475 0.12% 94.58% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::8 3919626 5.42% 100.00% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.iq.issued_per_cycle::total 76541920 # Number of insts issued each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.iq.rate 1.401304 # Inst issue rate system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.itb.accesses 0 # DTB accesses system.cpu.commit.committed_per_cycle::total 72289167 # Number of insts commited each cycle
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.commit.count 91262514 # Number of instructions committed
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.commit.refs 27322629 # Number of memory references committed
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.commit.loads 22575876 # Number of loads committed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.commit.branches 18722470 # Number of branches committed
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.itb.hits 0 # DTB hits system.cpu.commit.int_insts 72533318 # Number of committed integer instructions.
system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.commit.bw_lim_events 3919626 # number cycles where commit BW limit reached
system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.itb.misses 0 # DTB misses system.cpu.rob.rob_reads 187021057 # The number of ROB reads
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.rob.rob_writes 241665246 # The number of ROB writes
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.timesIdled 1537 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.idleCycles 29644 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.committedInsts 91249905 # Number of Instructions Simulated
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated
system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.cpi 0.840128 # CPI: Cycles Per Instruction
system.cpu.itb.write_hits 0 # DTB write hits system.cpu.cpi_total 0.840128 # CPI: Total CPI of All Threads
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.ipc 1.190295 # IPC: Instructions Per Cycle
system.cpu.l2cache.ReadExReq_accesses 34664 # number of ReadExReq accesses(hits+misses) system.cpu.ipc_total 1.190295 # IPC: Total IPC of All Threads
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.196506 # average ReadExReq miss latency system.cpu.int_regfile_reads 499502252 # number of integer regfile reads
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.712222 # average ReadExReq mshr miss latency system.cpu.int_regfile_writes 121448309 # number of integer regfile writes
system.cpu.fp_regfile_reads 60 # number of floating regfile reads
system.cpu.fp_regfile_writes 46 # number of floating regfile writes
system.cpu.misc_regfile_reads 187007485 # number of misc regfile reads
system.cpu.misc_regfile_writes 11602 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 569.362196 # Cycle average of tags in use
system.cpu.icache.total_refs 14552080 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 21463.244838 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 569.362196 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.278009 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 14552080 # number of ReadReq hits
system.cpu.icache.demand_hits 14552080 # number of demand (read+write) hits
system.cpu.icache.overall_hits 14552080 # number of overall hits
system.cpu.icache.ReadReq_misses 819 # number of ReadReq misses
system.cpu.icache.demand_misses 819 # number of demand (read+write) misses
system.cpu.icache.overall_misses 819 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 29501500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 29501500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 29501500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 14552899 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 14552899 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 14552899 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000056 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000056 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000056 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36021.367521 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36021.367521 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36021.367521 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 140 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 140 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 140 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 679 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 679 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 679 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 23405500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 23405500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 23405500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34470.544919 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34470.544919 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34470.544919 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943332 # number of replacements
system.cpu.dcache.tagsinuse 3485.983944 # Cycle average of tags in use
system.cpu.dcache.total_refs 29091101 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947428 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.705342 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 16303802000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3485.983944 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.851070 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24496946 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 4581580 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 6778 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 29078526 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 29078526 # number of overall hits
system.cpu.dcache.ReadReq_misses 1032002 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 153401 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1185403 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1185403 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5774861500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4244831902 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 10019693402 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 10019693402 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 25528948 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 6785 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 30263929 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 30263929 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.040425 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.032397 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001032 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.039169 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.039169 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 5595.785183 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27671.474775 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 8452.562885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 8452.562885 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23297488 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8138 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.802654 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 942849 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 119201 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 118773 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 237974 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 237974 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 912801 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 34628 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 947429 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 947429 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2307886000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1057417534 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3365303534 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3365303534 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035756 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007313 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.031306 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.031306 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2528.356126 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30536.488795 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3552.037708 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3552.037708 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 702 # number of replacements
system.cpu.l2cache.tagsinuse 8532.679465 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1625371 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15516 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 104.754511 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 402.391901 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8130.287564 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.012280 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.248117 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 912439 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 942849 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 20125 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits 20125 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 499228500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_hits 932564 # number of demand (read+write) hits
system.cpu.l2cache.ReadExReq_miss_rate 0.419426 # miss rate for ReadExReq accesses system.cpu.l2cache.overall_hits 932564 # number of overall hits
system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses system.cpu.l2cache.ReadReq_misses 1003 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451519000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419426 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 913473 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34317.365269 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.911290 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 912471 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 34386000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001097 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1002 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001086 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 992 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.demand_misses 15542 # number of demand (read+write) misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.overall_misses 15542 # number of overall misses
system.cpu.l2cache.Writeback_accesses 942852 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadReq_miss_latency 34422500 # number of ReadReq miss cycles
system.cpu.l2cache.Writeback_hits 942852 # number of Writeback hits system.cpu.l2cache.ReadExReq_miss_latency 499217500 # number of ReadExReq miss cycles
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.demand_miss_latency 533640000 # number of demand (read+write) miss cycles
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.overall_miss_latency 533640000 # number of overall miss cycles
system.cpu.l2cache.avg_refs 104.767129 # Average number of references to valid blocks. system.cpu.l2cache.ReadReq_accesses 913442 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.Writeback_accesses 942849 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 34664 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 948106 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 948106 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.001098 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.419426 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.016393 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.016393 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34319.541376 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.439920 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34335.349376 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34335.349376 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 948137 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34335.917895 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.429528 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 932596 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 533614500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016391 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15541 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 482384000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016381 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15531 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 401.000485 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8133.618465 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.012238 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.248218 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 948137 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34335.917895 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.429528 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 932596 # number of overall hits
system.cpu.l2cache.overall_miss_latency 533614500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016391 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15541 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 482384000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.016381 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15531 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 703 # number of replacements
system.cpu.l2cache.sampled_refs 15515 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8534.618949 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1625462 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 32 # number of writebacks system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.memDep0.conflictingLoads 929079 # Number of conflicting loads. system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.memDep0.conflictingStores 406185 # Number of conflicting stores. system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.memDep0.insertedLoads 29388831 # Number of loads inserted to the mem dependence unit. system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.memDep0.insertedStores 6085547 # Number of stores inserted to the mem dependence unit. system.cpu.l2cache.ReadReq_mshr_misses 993 # number of ReadReq MSHR misses
system.cpu.misc_regfile_reads 186806187 # number of misc regfile reads system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.misc_regfile_writes 11602 # number of misc regfile writes system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses
system.cpu.numCycles 76571457 # number of cpu cycles simulated system.cpu.l2cache.demand_mshr_misses 15532 # number of demand (read+write) MSHR misses
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.l2cache.overall_mshr_misses 15532 # number of overall MSHR misses
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.rename.BlockCycles 527053 # Number of cycles rename is blocking system.cpu.l2cache.ReadReq_mshr_miss_latency 30896000 # number of ReadReq MSHR miss cycles
system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers system.cpu.l2cache.ReadExReq_mshr_miss_latency 451520000 # number of ReadExReq MSHR miss cycles
system.cpu.rename.IQFullEvents 52081 # Number of times rename has blocked due to IQ full system.cpu.l2cache.demand_mshr_miss_latency 482416000 # number of demand (read+write) MSHR miss cycles
system.cpu.rename.IdleCycles 31875440 # Number of cycles rename is idle system.cpu.l2cache.overall_mshr_miss_latency 482416000 # number of overall MSHR miss cycles
system.cpu.rename.LSQFullEvents 790758 # Number of times rename has blocked due to LSQ full system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001087 # mshr miss rate for ReadReq accesses
system.cpu.rename.RenameLookups 546541782 # Number of register rename lookups that rename has made system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.rename.RenamedInsts 125415140 # Number of instructions processed by rename system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419426 # mshr miss rate for ReadExReq accesses
system.cpu.rename.RenamedOperands 146085442 # Number of destination operands rename has renamed system.cpu.l2cache.demand_mshr_miss_rate 0.016382 # mshr miss rate for demand accesses
system.cpu.rename.RunCycles 30085876 # Number of cycles rename is running system.cpu.l2cache.overall_mshr_miss_rate 0.016382 # mshr miss rate for overall accesses
system.cpu.rename.SquashCycles 4327396 # Number of cycles rename is squashing system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.796576 # average ReadReq mshr miss latency
system.cpu.rename.UnblockCycles 1561693 # Number of cycles rename is unblocking system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.rename.UndoneMaps 38655966 # Number of HB maps that are undone due to squashing system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.781003 # average ReadExReq mshr miss latency
system.cpu.rename.fp_rename_lookups 561 # Number of floating rename lookups system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.490085 # average overall mshr miss latency
system.cpu.rename.int_rename_lookups 546541221 # Number of integer rename lookups system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.490085 # average overall mshr miss latency
system.cpu.rename.serializeStallCycles 8164462 # count of cycles rename stalled for serializing inst system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.rename.serializingInsts 673678 # count of serializing insts renamed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.rename.skidInsts 5091742 # count of insts added to the skid buffer system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.rename.tempSerializingInsts 677127 # count of temporary serializing insts renamed system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.rob.rob_reads 186866672 # The number of ROB reads
system.cpu.rob.rob_writes 241479537 # The number of ROB writes
system.cpu.timesIdled 1545 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

10
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -5,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Apr 21 2011 13:30:37 M5 compiled May 17 2011 12:22:59
M5 started Apr 21 2011 13:35:14 M5 started May 17 2011 13:00:50
M5 executing on maize M5 executing on nadc-0309
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -27,4 +29,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 81396224000 because target called exit() Exiting @ tick 81353358500 because target called exit()

844
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,306 +1,108 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 154675 # Simulator instruction rate (inst/s) sim_seconds 0.081353 # Number of seconds simulated
host_mem_usage 349680 # Number of bytes of host memory used sim_ticks 81353358500 # Number of ticks simulated
host_seconds 1798.56 # Real time elapsed on the host
host_tick_rate 45256270 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 230671 # Simulator instruction rate (inst/s)
host_tick_rate 67456393 # Simulator tick rate (ticks/s)
host_mem_usage 384688 # Number of bytes of host memory used
host_seconds 1206.01 # Real time elapsed on the host
sim_insts 278192519 # Number of instructions simulated sim_insts 278192519 # Number of instructions simulated
sim_seconds 0.081396 # Number of seconds simulated system.cpu.workload.num_syscalls 444 # Number of system calls
sim_ticks 81396224000 # Number of ticks simulated system.cpu.numCycles 162706718 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 43478033 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 43478033 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2457578 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 38773202 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 38222212 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 38238795 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 38788801 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 2465320 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 43504790 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 43504790 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 2465329 # The number of times a branch was mispredicted system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.commit.branches 29309710 # Number of branches committed system.cpu.fetch.icacheStallCycles 30836194 # Number of cycles fetch is stalled on an Icache miss
system.cpu.commit.bw_lim_events 13548841 # number cycles where commit BW limit reached system.cpu.fetch.Insts 225319865 # Number of instructions fetch has processed
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.fetch.Branches 43478033 # Number of branches that fetch encountered
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.fetch.predictedBranches 38222212 # Number of branches that fetch has predicted taken
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.fetch.Cycles 71185004 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.commit.commitSquashedInsts 88842299 # The number of squashed insts skipped by commit system.cpu.fetch.SquashCycles 2631314 # Number of cycles fetch has spent squashing
system.cpu.commit.committed_per_cycle::samples 149131695 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.865415 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 149131695 # Number of insts commited each cycle
system.cpu.commit.count 278192519 # Number of instructions committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.loads 90779388 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 122219139 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
system.cpu.cpi 0.585179 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.585179 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 63345837 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 6389.837562 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.424936 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 61126773 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 14179458500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.035031 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 2219064 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 247059 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 5532312000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.031131 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1972005 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 17790.751735 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17644.271587 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 31202641 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4218365144 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.007542 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 237110 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 131111 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1870275144 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003371 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105999 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3445.783133 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 44.431869 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 286000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 94785588 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 7490.439865 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency
system.cpu.dcache.demand_hits 92329414 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 18397823644 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.025913 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2456174 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 378170 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 7402587144 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.021923 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2078004 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 4075.274681 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994940 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 94785588 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7490.439865 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 92329414 # number of overall hits
system.cpu.dcache.overall_miss_latency 18397823644 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.025913 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2456174 # number of overall misses
system.cpu.dcache.overall_mshr_hits 378170 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 7402587144 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.021923 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2078004 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2073904 # number of replacements
system.cpu.dcache.sampled_refs 2078000 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4075.274681 # Cycle average of tags in use
system.cpu.dcache.total_refs 92329423 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 30396735000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1448011 # number of writebacks
system.cpu.decode.BlockedCycles 13645155 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 390459172 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 68124952 # Number of cycles decode is idle
system.cpu.decode.RunCycles 66154578 # Number of cycles decode is running
system.cpu.decode.SquashCycles 12492114 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 1207010 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 43504790 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 30855910 # Number of cache lines fetched
system.cpu.fetch.Cycles 71218247 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 310077 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 225429246 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 2638813 # Number of cycles fetch has spent squashing system.cpu.fetch.CacheLines 30836194 # Number of cache lines fetched
system.cpu.fetch.branchRate 0.267241 # Number of branch fetches per cycle system.cpu.fetch.IcacheSquashes 310702 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.icacheStallCycles 30855910 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.rateDist::samples 161537602 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.predictedBranches 38238795 # Number of branches that fetch has predicted taken system.cpu.fetch.rateDist::mean 2.462501 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rate 1.384765 # Number of inst fetches per cycle system.cpu.fetch.rateDist::stdev 3.241161 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 161623809 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.462324 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.240695 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 92912734 57.49% 57.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 92871454 57.49% 57.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4821587 2.98% 60.47% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4826864 2.99% 60.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3003433 1.86% 62.33% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 3003358 1.86% 62.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6267047 3.88% 66.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 6248204 3.87% 66.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7344013 4.54% 70.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 7317457 4.53% 70.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5575474 3.45% 74.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 5554189 3.44% 74.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 8028911 4.97% 79.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 8050336 4.98% 79.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 6451248 3.99% 83.16% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 6460332 4.00% 83.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 27219362 16.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 27205408 16.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 161623809 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 161537602 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 75 # number of floating regfile reads system.cpu.fetch.branchRate 0.267217 # Number of branch fetches per cycle
system.cpu.fp_regfile_writes 41 # number of floating regfile writes system.cpu.fetch.rate 1.384822 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_accesses 30855910 # number of ReadReq accesses(hits+misses) system.cpu.decode.IdleCycles 68100522 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_miss_latency 36182.458888 # average ReadReq miss latency system.cpu.decode.BlockedCycles 13645785 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35209.772952 # average ReadReq mshr miss latency system.cpu.decode.RunCycles 66107585 # Number of cycles decode is running
system.cpu.icache.ReadReq_hits 30854633 # number of ReadReq hits system.cpu.decode.UnblockCycles 1213656 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_latency 46205000 # number of ReadReq miss cycles system.cpu.decode.SquashCycles 12470054 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses system.cpu.decode.DecodedInsts 390299110 # Number of instructions handled by decode
system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses system.cpu.rename.SquashCycles 12470054 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_hits 264 # number of ReadReq MSHR hits system.cpu.rename.IdleCycles 72027635 # Number of cycles rename is idle
system.cpu.icache.ReadReq_mshr_miss_latency 35667500 # number of ReadReq MSHR miss cycles system.cpu.rename.BlockCycles 3012057 # Number of cycles rename is blocking
system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses system.cpu.rename.serializeStallCycles 6445 # count of cycles rename stalled for serializing inst
system.cpu.icache.ReadReq_mshr_misses 1013 # number of ReadReq MSHR misses system.cpu.rename.RunCycles 63003531 # Number of cycles rename is running
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.UnblockCycles 11017880 # Number of cycles rename is unblocking
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.RenamedInsts 382954672 # Number of instructions processed by rename
system.cpu.icache.avg_refs 30488.767787 # Average number of references to valid blocks. system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 129804 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 9724945 # Number of times rename has blocked due to LSQ full
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.RenamedOperands 343637650 # Number of destination operands rename has renamed
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenameLookups 940851472 # Number of register rename lookups that rename has made
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.int_rename_lookups 940850893 # Number of integer rename lookups
system.cpu.icache.demand_accesses 30855910 # number of demand (read+write) accesses system.cpu.rename.fp_rename_lookups 579 # Number of floating rename lookups
system.cpu.icache.demand_avg_miss_latency 36182.458888 # average overall miss latency system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.icache.demand_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency system.cpu.rename.UndoneMaps 95293458 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_hits 30854633 # number of demand (read+write) hits system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
system.cpu.icache.demand_miss_latency 46205000 # number of demand (read+write) miss cycles system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses system.cpu.rename.skidInsts 25876088 # count of insts added to the skid buffer
system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses system.cpu.memDep0.insertedLoads 121481389 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits system.cpu.memDep0.insertedStores 39633547 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_latency 35667500 # number of demand (read+write) MSHR miss cycles system.cpu.memDep0.conflictingLoads 49140895 # Number of conflicting loads.
system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses system.cpu.memDep0.conflictingStores 10609784 # Number of conflicting stores.
system.cpu.icache.demand_mshr_misses 1013 # number of demand (read+write) MSHR misses system.cpu.iq.iqInstsAdded 366915906 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.iq.iqInstsIssued 331723490 # Number of instructions issued
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqSquashedInstsIssued 173771 # Number of squashed instructions issued
system.cpu.icache.occ_blocks::0 812.031019 # Average occupied blocks per context system.cpu.iq.iqSquashedInstsExamined 88480197 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.occ_percent::0 0.396500 # Average percentage of cache occupancy system.cpu.iq.iqSquashedOperandsExamined 124853434 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_accesses 30855910 # number of overall (read+write) accesses system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_avg_miss_latency 36182.458888 # average overall miss latency system.cpu.iq.issued_per_cycle::samples 161537602 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency system.cpu.iq.issued_per_cycle::mean 2.053537 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.issued_per_cycle::stdev 1.792236 # Number of insts issued each cycle
system.cpu.icache.overall_hits 30854633 # number of overall hits system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 46205000 # number of overall miss cycles system.cpu.iq.issued_per_cycle::0 44403783 27.49% 27.49% # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::1 26523335 16.42% 43.91% # Number of insts issued each cycle
system.cpu.icache.overall_misses 1277 # number of overall misses system.cpu.iq.issued_per_cycle::2 27554043 17.06% 60.96% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 264 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::3 26723041 16.54% 77.51% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 35667500 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::4 19519323 12.08% 89.59% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::5 11121820 6.88% 96.48% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 1013 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::6 3849891 2.38% 98.86% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::7 1601720 0.99% 99.85% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::8 240646 0.15% 100.00% # Number of insts issued each cycle
system.cpu.icache.replacements 63 # number of replacements system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 1012 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.icache.tagsinuse 812.031019 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::total 161537602 # Number of insts issued each cycle
system.cpu.icache.total_refs 30854633 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1168640 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 2866285 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 32808514 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 2.009454 # Inst execution rate
system.cpu.iew.exec_refs 141715314 # number of memory reference insts executed
system.cpu.iew.exec_stores 34352421 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 739357 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 121527888 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 440749 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 39643183 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 367028456 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 107362893 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4685170 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 327123971 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 4283 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 66782 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 12492114 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 101572 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 43812375 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 237293 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 3275 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 30748500 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 8203432 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 330470543 # num instructions consuming a value
system.cpu.iew.wb_count 324204287 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.735351 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 243011799 # num instructions producing a value
system.cpu.iew.wb_rate 1.991519 # insts written-back per cycle
system.cpu.iew.wb_sent 325408414 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 572686347 # number of integer regfile reads
system.cpu.int_regfile_writes 291536884 # number of integer regfile writes
system.cpu.ipc 1.708879 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.708879 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 331809141 # Type of FU issued
system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 1744992 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 20533 1.17% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
@ -329,145 +131,343 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1580289 90.40% 91.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 147351 8.43% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 333537329 # Number of integer alu accesses system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
system.cpu.iq.int_inst_queue_reads 827162429 # Number of integer instruction queue reads system.cpu.iq.FU_type_0::IntAlu 188283718 56.76% 56.76% # Type of FU issued
system.cpu.iq.int_inst_queue_wakeup_accesses 324204207 # Number of integer instruction queue wakeup accesses system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.int_inst_queue_writes 455842500 # Number of integer instruction queue writes system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqInstsAdded 367027991 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqInstsIssued 331809141 # Number of instructions issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqSquashedInstsExamined 88592670 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqSquashedInstsIssued 175554 # Number of squashed instructions issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.iqSquashedOperandsExamined 124945161 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::samples 161623809 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::mean 2.052972 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.issued_per_cycle::total 161623809 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.rate 2.038234 # Inst issue rate system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.l2cache.ReadExReq_accesses 106011 # number of ReadExReq accesses(hits+misses) system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786 # average ReadExReq miss latency system.cpu.iq.FU_type_0::MemRead 108609030 32.74% 89.51% # Type of FU issued
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095 # average ReadExReq mshr miss latency system.cpu.iq.FU_type_0::MemWrite 34814023 10.49% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_hits 63955 # number of ReadExReq hits system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_miss_latency 1437979500 # number of ReadExReq miss cycles system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_miss_rate 0.396714 # miss rate for ReadExReq accesses system.cpu.iq.FU_type_0::total 331723490 # Type of FU issued
system.cpu.l2cache.ReadExReq_misses 42056 # number of ReadExReq misses system.cpu.iq.rate 2.038782 # Inst issue rate
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308610000 # number of ReadExReq MSHR miss cycles system.cpu.iq.fu_busy_cnt 1748173 # FU busy when requested
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396714 # mshr miss rate for ReadExReq accesses system.cpu.iq.fu_busy_rate 0.005270 # FU busy rate (busy events/executed inst)
system.cpu.l2cache.ReadExReq_mshr_misses 42056 # number of ReadExReq MSHR misses system.cpu.iq.int_inst_queue_reads 826906318 # Number of integer instruction queue reads
system.cpu.l2cache.ReadReq_accesses 1973004 # number of ReadReq accesses(hits+misses) system.cpu.iq.int_inst_queue_writes 455618768 # Number of integer instruction queue writes
system.cpu.l2cache.ReadReq_avg_miss_latency 34215.506485 # average ReadReq miss latency system.cpu.iq.int_inst_queue_wakeup_accesses 324136676 # Number of integer instruction queue wakeup accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.372893 # average ReadReq mshr miss latency system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
system.cpu.l2cache.ReadReq_hits 1938541 # number of ReadReq hits system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
system.cpu.l2cache.ReadReq_miss_latency 1179169000 # number of ReadReq miss cycles system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
system.cpu.l2cache.ReadReq_miss_rate 0.017467 # miss rate for ReadReq accesses system.cpu.iq.int_alu_accesses 333454859 # Number of integer alu accesses
system.cpu.l2cache.ReadReq_misses 34463 # number of ReadReq misses system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1069158500 # number of ReadReq MSHR miss cycles system.cpu.iew.lsq.thread0.forwLoads 43811715 # Number of loads that had data forwarded from stores
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017467 # mshr miss rate for ReadReq accesses system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.l2cache.ReadReq_mshr_misses 34463 # number of ReadReq MSHR misses system.cpu.iew.lsq.thread0.squashedLoads 30702001 # Number of loads squashed
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) system.cpu.iew.lsq.thread0.ignoredResponses 37170 # Number of memory responses ignored because the instruction is squashed
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.iew.lsq.thread0.memOrderViolation 238201 # Number of memory ordering violations
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.iew.lsq.thread0.squashedStores 8193796 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3292 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 14215 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 12470054 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 739461 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 101351 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 366916371 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 440258 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 121481389 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 39633547 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4278 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 66728 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 238201 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2276962 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 580211 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2857173 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 327058428 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 107336037 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4665062 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 141682074 # number of memory reference insts executed
system.cpu.iew.exec_branches 32801587 # Number of branches executed
system.cpu.iew.exec_stores 34346037 # Number of stores executed
system.cpu.iew.exec_rate 2.010110 # Inst execution rate
system.cpu.iew.wb_sent 325338572 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 324136756 # cumulative count of insts written-back
system.cpu.iew.wb_producers 242967422 # num instructions producing a value
system.cpu.iew.wb_consumers 330454967 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.992153 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.735251 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 88730028 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2457587 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 149067548 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.866218 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.482505 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 63468061 42.58% 42.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 26994600 18.11% 60.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19490262 13.07% 73.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13117480 8.80% 82.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4245570 2.85% 85.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3438248 2.31% 87.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3061065 2.05% 89.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1693051 1.14% 90.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13559211 9.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 149067548 # Number of insts commited each cycle
system.cpu.commit.count 278192519 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219139 # Number of memory references committed
system.cpu.commit.loads 90779388 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 29309710 # Number of branches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 13559211 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 502430884 # The number of ROB reads
system.cpu.rob.rob_writes 746329282 # The number of ROB writes
system.cpu.timesIdled 40054 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1169116 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
system.cpu.cpi 0.584871 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.584871 # CPI: Total CPI of All Threads
system.cpu.ipc 1.709779 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.709779 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 572578713 # number of integer regfile reads
system.cpu.int_regfile_writes 291474353 # number of integer regfile writes
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
system.cpu.fp_regfile_writes 41 # number of floating regfile writes
system.cpu.misc_regfile_reads 211120280 # number of misc regfile reads
system.cpu.icache.replacements 60 # number of replacements
system.cpu.icache.tagsinuse 811.599985 # Cycle average of tags in use
system.cpu.icache.total_refs 30834919 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1009 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 30559.880079 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 811.599985 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.396289 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 30834919 # number of ReadReq hits
system.cpu.icache.demand_hits 30834919 # number of demand (read+write) hits
system.cpu.icache.overall_hits 30834919 # number of overall hits
system.cpu.icache.ReadReq_misses 1275 # number of ReadReq misses
system.cpu.icache.demand_misses 1275 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1275 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 46105500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 46105500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 46105500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 30836194 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 30836194 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 30836194 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36161.176471 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36161.176471 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36161.176471 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 265 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 265 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 265 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1010 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1010 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1010 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 35558500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 35558500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 35558500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35206.435644 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2073960 # number of replacements
system.cpu.dcache.tagsinuse 4075.298640 # Cycle average of tags in use
system.cpu.dcache.total_refs 92303486 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2078056 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 44.418190 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 30307591000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4075.298640 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994946 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 61101027 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 31202450 # number of WriteReq hits
system.cpu.dcache.demand_hits 92303477 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 92303477 # number of overall hits
system.cpu.dcache.ReadReq_misses 2219212 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 237301 # number of WriteReq misses
system.cpu.dcache.demand_misses 2456513 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2456513 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14180205500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4209484208 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 18389689708 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 18389689708 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 63320239 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 94759990 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 94759990 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.035047 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.007548 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.025924 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.025924 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 6389.748028 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17739.007455 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 7486.095009 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 7486.095009 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 290000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3411.764706 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1448049 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 247154 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 131299 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 378453 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 378453 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1972058 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106002 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2078060 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2078060 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 5532610500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1870145708 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 7402756208 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 7402756208 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.031144 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003372 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.021930 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.021930 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.500903 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17642.551159 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 49058 # number of replacements
system.cpu.l2cache.tagsinuse 18069.203236 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3319340 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 43.073070 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 6443.195976 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11626.007260 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.196631 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.354798 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1938598 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1448049 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 63959 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2002557 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2002557 # number of overall hits
system.cpu.l2cache.ReadReq_misses 34456 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_misses 42055 # number of ReadExReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.demand_misses 76511 # number of demand (read+write) misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.overall_misses 76511 # number of overall misses
system.cpu.l2cache.Writeback_accesses 1448011 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadReq_miss_latency 1178964000 # number of ReadReq miss cycles
system.cpu.l2cache.Writeback_hits 1448011 # number of Writeback hits system.cpu.l2cache.ReadExReq_miss_latency 1437688500 # number of ReadExReq miss cycles
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.l2cache.demand_miss_latency 2616652500 # number of demand (read+write) miss cycles
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.overall_miss_latency 2616652500 # number of overall miss cycles
system.cpu.l2cache.avg_refs 43.067418 # Average number of references to valid blocks. system.cpu.l2cache.ReadReq_accesses 1973054 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.Writeback_accesses 1448049 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2079068 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2079068 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.017463 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.396693 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.036801 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.036801 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34216.508010 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34185.911307 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34199.690241 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34199.690241 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 2079015 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34202.596741 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 2002496 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2617148500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.036805 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 76519 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2377768500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.036805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 76519 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.writebacks 29183 # number of writebacks
system.cpu.l2cache.occ_blocks::0 6434.571377 # Average occupied blocks per context system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.occ_blocks::1 11614.477696 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.196368 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.354446 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2079015 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34202.596741 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2002496 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2617148500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.036805 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 76519 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2377768500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_misses 34456 # number of ReadReq MSHR misses
system.cpu.l2cache.overall_mshr_miss_rate 0.036805 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.overall_mshr_misses 76519 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42055 # number of ReadExReq MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.demand_mshr_misses 76511 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 76511 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 49066 # number of replacements system.cpu.l2cache.ReadReq_mshr_miss_latency 1068941000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.sampled_refs 77071 # Sample count of references to valid blocks. system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308447000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2377388000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2377388000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017463 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396693 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.036801 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.036801 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.363130 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31112.757104 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18049.049074 # Cycle average of tags in use system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.total_refs 3319249 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 29185 # number of writebacks
system.cpu.memDep0.conflictingLoads 49162785 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 10611644 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 121527888 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 39643183 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 211169577 # number of misc regfile reads
system.cpu.numCycles 162792449 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 3023364 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 130274 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 72054036 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 941229334 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 383108308 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 343773743 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 63044913 # Number of cycles rename is running
system.cpu.rename.SquashCycles 12492114 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 11002939 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 95429551 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 586 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 941228748 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 6443 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
system.cpu.rename.skidInsts 25868384 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 502617672 # The number of ROB reads
system.cpu.rob.rob_writes 746575877 # The number of ROB writes
system.cpu.timesIdled 40062 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 14:22:00 M5 started May 16 2011 15:29:17
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -73,4 +73,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 321578293500 because target called exit() Exiting @ tick 320953109000 because target called exit()

1014
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

18
tests/long/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing/simout
Redirecting stderr to build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -5,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Apr 23 2011 16:56:34 M5 compiled May 17 2011 12:22:59
M5 started Apr 23 2011 17:38:09 M5 started May 17 2011 13:21:24
M5 executing on victors M5 executing on nadc-0309
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -29,6 +31,14 @@ Echoing of input sentence turned on.
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it * how fast the program is it
* I am wondering whether to invite to the party * I am wondering whether to invite to the party
* I gave him for his birthday it * I gave him for his birthday it
@ -73,4 +83,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 584102039000 because target called exit() Exiting @ tick 584023415000 because target called exit()

906
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,475 +1,475 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 88955 # Simulator instruction rate (inst/s) sim_seconds 0.584023 # Number of seconds simulated
host_mem_usage 246024 # Number of bytes of host memory used sim_ticks 584023415000 # Number of ticks simulated
host_seconds 17188.43 # Real time elapsed on the host
host_tick_rate 33982273 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 204231 # Simulator instruction rate (inst/s)
host_tick_rate 78009509 # Simulator tick rate (ticks/s)
host_mem_usage 293660 # Number of bytes of host memory used
host_seconds 7486.57 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated sim_insts 1528988756 # Number of instructions simulated
sim_seconds 0.584102 # Number of seconds simulated system.cpu.workload.num_syscalls 551 # Number of system calls
sim_ticks 584102039000 # Number of ticks simulated system.cpu.numCycles 1168046831 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 253390632 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 253390632 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16658352 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 238513057 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 219596279 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 218742072 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 237579384 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 16731555 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 252612908 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 252612908 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.commit.branches 149758588 # Number of branches committed system.cpu.fetch.icacheStallCycles 188480819 # Number of cycles fetch is stalled on an Icache miss
system.cpu.commit.bw_lim_events 41097639 # number cycles where commit BW limit reached system.cpu.fetch.Insts 1362450524 # Number of instructions fetch has processed
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.fetch.Branches 253390632 # Number of branches that fetch encountered
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions system.cpu.fetch.predictedBranches 219596279 # Number of branches that fetch has predicted taken
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards system.cpu.fetch.Cycles 442052723 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit system.cpu.fetch.SquashCycles 19279680 # Number of cycles fetch has spent squashing
system.cpu.commit.committed_per_cycle::samples 1035309655 # Number of insts commited each cycle system.cpu.fetch.MiscStallCycles 77230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.commit.committed_per_cycle::mean 1.476842 # Number of insts commited each cycle system.cpu.fetch.CacheLines 188480819 # Number of cache lines fetched
system.cpu.commit.committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle system.cpu.fetch.IcacheSquashes 3788271 # Number of outstanding Icache misses that were squashed
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.fetch.rateDist::samples 1143904596 # Number of instructions fetched each cycle (Total)
system.cpu.commit.committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle system.cpu.fetch.rateDist::mean 2.224031 # Number of instructions fetched each cycle (Total)
system.cpu.commit.committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle system.cpu.fetch.rateDist::stdev 3.207932 # Number of instructions fetched each cycle (Total)
system.cpu.commit.committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1035309655 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.loads 384102160 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 533262345 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.764037 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 323639192 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15916.826695 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8444.942006 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 320628262 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 47924451000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.009303 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 3010930 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1248670 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 14882183500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005445 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1762260 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 23726.182533 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18050.899847 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 147539972 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 38441849000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010862 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1620229 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 607112 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 18287673500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006792 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1013117 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 185.317160 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 472799393 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18648.960228 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency
system.cpu.dcache.demand_hits 468168234 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 86366300000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009795 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4631159 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1855782 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 33169857000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005870 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2775377 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998173 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 468168234 # number of overall hits
system.cpu.dcache.overall_miss_latency 86366300000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009795 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4631159 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1855782 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 33169857000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005870 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2775377 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2529347 # number of replacements
system.cpu.dcache.sampled_refs 2533443 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4088.515779 # Cycle average of tags in use
system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2231104 # number of writebacks
system.cpu.decode.BlockedCycles 187291575 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 2489806075 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 422005844 # Number of cycles decode is idle
system.cpu.decode.RunCycles 404270583 # Number of cycles decode is running
system.cpu.decode.SquashCycles 108207267 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 21741653 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 252612908 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched
system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 3788635 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1360923559 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 78504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 19199509 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.216240 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 188594062 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 218742072 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.164971 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1143516922 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.221243 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.208291 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 707206433 61.84% 61.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 706004786 61.72% 61.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32665502 2.86% 64.70% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 32751719 2.86% 64.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 37223305 3.26% 67.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 38229862 3.34% 67.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 33654778 2.94% 70.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 34570255 3.02% 70.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 21116720 1.85% 72.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 20874859 1.82% 72.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 40194771 3.52% 76.26% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 39604957 3.46% 76.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 44517058 3.89% 80.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 44518737 3.89% 80.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36097891 3.16% 83.31% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 36275151 3.17% 83.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 190840464 16.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 191074270 16.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1143516922 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1143904596 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 40 # number of floating regfile reads system.cpu.fetch.branchRate 0.216935 # Number of branch fetches per cycle
system.cpu.icache.ReadReq_accesses 188594062 # number of ReadReq accesses(hits+misses) system.cpu.fetch.rate 1.166435 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_avg_miss_latency 6510.591789 # average ReadReq miss latency system.cpu.decode.IdleCycles 421330270 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3406.338578 # average ReadReq mshr miss latency system.cpu.decode.BlockedCycles 186446419 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_hits 188336504 # number of ReadReq hits system.cpu.decode.RunCycles 405934175 # Number of cycles decode is running
system.cpu.icache.ReadReq_miss_latency 1676855000 # number of ReadReq miss cycles system.cpu.decode.UnblockCycles 21628969 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_rate 0.001366 # miss rate for ReadReq accesses system.cpu.decode.SquashCycles 108564763 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_misses 257558 # number of ReadReq misses system.cpu.decode.DecodedInsts 2493904791 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits system.cpu.rename.SquashCycles 108564763 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_miss_latency 872465500 # number of ReadReq MSHR miss cycles system.cpu.rename.IdleCycles 460258453 # Number of cycles rename is idle
system.cpu.icache.ReadReq_mshr_miss_rate 0.001358 # mshr miss rate for ReadReq accesses system.cpu.rename.BlockCycles 50662056 # Number of cycles rename is blocking
system.cpu.icache.ReadReq_mshr_misses 256130 # number of ReadReq MSHR misses system.cpu.rename.serializeStallCycles 15556 # count of cycles rename stalled for serializing inst
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.RunCycles 387000173 # Number of cycles rename is running
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.UnblockCycles 137403595 # Number of cycles rename is unblocking
system.cpu.icache.avg_refs 16890.533363 # Average number of references to valid blocks. system.cpu.rename.RenamedInsts 2428714828 # Number of instructions processed by rename
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.ROBFullEvents 8220 # Number of times rename has blocked due to ROB full
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 53929654 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 70829494 # Number of times rename has blocked due to LSQ full
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedOperands 2267135297 # Number of destination operands rename has renamed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.RenameLookups 5702873531 # Number of register rename lookups that rename has made
system.cpu.icache.demand_accesses 188594062 # number of demand (read+write) accesses system.cpu.rename.int_rename_lookups 5702857140 # Number of integer rename lookups
system.cpu.icache.demand_avg_miss_latency 6510.591789 # average overall miss latency system.cpu.rename.fp_rename_lookups 16391 # Number of floating rename lookups
system.cpu.icache.demand_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.icache.demand_hits 188336504 # number of demand (read+write) hits system.cpu.rename.UndoneMaps 839836270 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_miss_latency 1676855000 # number of demand (read+write) miss cycles system.cpu.rename.serializingInsts 2552 # count of serializing insts renamed
system.cpu.icache.demand_miss_rate 0.001366 # miss rate for demand accesses system.cpu.rename.tempSerializingInsts 2513 # count of temporary serializing insts renamed
system.cpu.icache.demand_misses 257558 # number of demand (read+write) misses system.cpu.rename.skidInsts 298757683 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits system.cpu.memDep0.insertedLoads 586893998 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_latency 872465500 # number of demand (read+write) MSHR miss cycles system.cpu.memDep0.insertedStores 222778511 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_rate 0.001358 # mshr miss rate for demand accesses system.cpu.memDep0.conflictingLoads 352697963 # Number of conflicting loads.
system.cpu.icache.demand_mshr_misses 256130 # number of demand (read+write) MSHR misses system.cpu.memDep0.conflictingStores 138822292 # Number of conflicting stores.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.iq.iqInstsAdded 2327078199 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.iq.iqNonSpecInstsAdded 9768 # Number of non-speculative instructions added to the IQ
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqInstsIssued 1903699453 # Number of instructions issued
system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context system.cpu.iq.iqSquashedInstsIssued 749156 # Number of squashed instructions issued
system.cpu.icache.occ_percent::0 0.469099 # Average percentage of cache occupancy system.cpu.iq.iqSquashedInstsExamined 795322101 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses system.cpu.iq.iqSquashedOperandsExamined 1354689551 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency system.cpu.iq.iqSquashedNonSpecRemoved 9215 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency system.cpu.iq.issued_per_cycle::samples 1143904596 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.issued_per_cycle::mean 1.664212 # Number of insts issued each cycle
system.cpu.icache.overall_hits 188336504 # number of overall hits system.cpu.iq.issued_per_cycle::stdev 1.649949 # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 1676855000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001366 # miss rate for overall accesses
system.cpu.icache.overall_misses 257558 # number of overall misses
system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 872465500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001358 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 256130 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 9707 # number of replacements
system.cpu.icache.sampled_refs 11150 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 960.715295 # Cycle average of tags in use
system.cpu.icache.total_refs 188329447 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 6 # number of writebacks
system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 173444431 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 1.602205 # Inst execution rate
system.cpu.iew.exec_refs 612750445 # number of memory reference insts executed
system.cpu.iew.exec_stores 165978925 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2269927 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 223085364 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2324941378 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 446771520 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 30325762 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1871702722 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 1004270 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 42321 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 108207267 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 1500742 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 122021898 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 146459 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 2443893 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 1254 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 202017116 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 73925179 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 2110704618 # num instructions consuming a value
system.cpu.iew.wb_count 1858331416 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.678632 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1432391344 # num instructions producing a value
system.cpu.iew.wb_rate 1.590759 # insts written-back per cycle
system.cpu.iew.wb_sent 1864643959 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads
system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes
system.cpu.ipc 1.308837 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.308837 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1902028484 # Type of FU issued
system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 156 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 7351 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 11137895 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 1910818238 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4959453857 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1858331376 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 3120531509 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 2324931719 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1902028484 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 9659 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 793159883 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 742228 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9106 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1353359987 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 1143516922 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.663315 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 364118171 31.83% 31.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 266012583 23.25% 55.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 191391841 16.73% 71.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 151042401 13.20% 85.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 94875410 8.29% 93.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 46737983 4.09% 97.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 20365340 1.78% 99.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 8494546 0.74% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 866321 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1143516922 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 1143904596 # Number of insts issued each cycle
system.cpu.iq.rate 1.628165 # Inst issue rate system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_accesses 775816 # number of ReadExReq accesses(hits+misses) system.cpu.iq.fu_full::IntAlu 1290623 11.43% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889 # average ReadExReq miss latency system.cpu.iq.fu_full::IntMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640 # average ReadExReq mshr miss latency system.cpu.iq.fu_full::IntDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_hits 528344 # number of ReadExReq hits system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_miss_latency 8477993500 # number of ReadExReq miss cycles system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_miss_rate 0.318983 # miss rate for ReadExReq accesses system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_misses 247472 # number of ReadExReq misses system.cpu.iq.fu_full::FloatMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7672259500 # number of ReadExReq MSHR miss cycles system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318983 # mshr miss rate for ReadExReq accesses system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_mshr_misses 247472 # number of ReadExReq MSHR misses system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_accesses 1768657 # number of ReadReq accesses(hits+misses) system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_avg_miss_latency 34159.791245 # average ReadReq miss latency system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.301453 # average ReadReq mshr miss latency system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_hits 1429599 # number of ReadReq hits system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_miss_latency 11582150500 # number of ReadReq miss cycles system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_miss_rate 0.191704 # miss rate for ReadReq accesses system.cpu.iq.fu_full::SimdMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_misses 339058 # number of ReadReq misses system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_mshr_miss_latency 10512595500 # number of ReadReq MSHR miss cycles system.cpu.iq.fu_full::SimdShift 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191704 # mshr miss rate for ReadReq accesses system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_mshr_misses 339058 # number of ReadReq MSHR misses system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_accesses 244851 # number of UpgradeReq accesses(hits+misses) system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.349749 # average UpgradeReq miss latency system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.844007 # average UpgradeReq mshr miss latency system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_hits 1225 # number of UpgradeReq hits system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_miss_latency 10317500 # number of UpgradeReq miss cycles system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_miss_rate 0.994997 # miss rate for UpgradeReq accesses system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_misses 243626 # number of UpgradeReq misses system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7553342500 # number of UpgradeReq MSHR miss cycles system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994997 # mshr miss rate for UpgradeReq accesses system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_mshr_misses 243626 # number of UpgradeReq MSHR misses system.cpu.iq.fu_full::MemRead 7282650 64.51% 75.94% # attempts to use FU when none available
system.cpu.l2cache.Writeback_accesses 2231110 # number of Writeback accesses(hits+misses) system.cpu.iq.fu_full::MemWrite 2716745 24.06% 100.00% # attempts to use FU when none available
system.cpu.l2cache.Writeback_hits 2231110 # number of Writeback hits system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.iq.FU_type_0::No_OpClass 2276794 0.12% 0.12% # Type of FU issued
system.cpu.l2cache.avg_refs 5.363240 # Average number of references to valid blocks. system.cpu.iq.FU_type_0::IntAlu 1273262556 66.88% 67.00% # Type of FU issued
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.00% # Type of FU issued
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 457990895 24.06% 91.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170169208 8.94% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1903699453 # Type of FU issued
system.cpu.iq.rate 1.629814 # Inst issue rate
system.cpu.iq.fu_busy_cnt 11290018 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005931 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4963342528 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3124994935 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1860002555 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 148 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6470 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 35 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1912712604 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 73 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 121974892 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 202791838 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 144755 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2595349 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 73620402 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1258 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 108564763 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9612649 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1584002 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2327087967 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2265532 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 586893998 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222780587 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 9768 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1061349 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 44764 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2595349 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 15395124 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2700605 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18095729 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1873365131 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 447946174 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 30334322 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 613940816 # number of memory reference insts executed
system.cpu.iew.exec_branches 173514694 # Number of branches executed
system.cpu.iew.exec_stores 165994642 # Number of stores executed
system.cpu.iew.exec_rate 1.603844 # Inst execution rate
system.cpu.iew.wb_sent 1866291041 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1860002590 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1434917653 # num instructions producing a value
system.cpu.iew.wb_consumers 2113204026 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.592404 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.679025 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 798102573 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16689612 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1035339833 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.476799 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.996303 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 433023044 41.82% 41.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 272005097 26.27% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 102852786 9.93% 78.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 102343925 9.89% 87.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 37875553 3.66% 91.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24412247 2.36% 93.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10662009 1.03% 94.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10610565 1.02% 95.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 41554607 4.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1035339833 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262345 # Number of memory references committed
system.cpu.commit.loads 384102160 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 149758588 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 41554607 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3320876555 # The number of ROB reads
system.cpu.rob.rob_writes 4762809697 # The number of ROB writes
system.cpu.timesIdled 612261 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24142235 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.763934 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.763934 # CPI: Total CPI of All Threads
system.cpu.ipc 1.309013 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.309013 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3113980511 # number of integer regfile reads
system.cpu.int_regfile_writes 1735312737 # number of integer regfile writes
system.cpu.fp_regfile_reads 35 # number of floating regfile reads
system.cpu.misc_regfile_reads 1026187894 # number of misc regfile reads
system.cpu.icache.replacements 9719 # number of replacements
system.cpu.icache.tagsinuse 962.212052 # Cycle average of tags in use
system.cpu.icache.total_refs 188218304 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11170 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 16850.340555 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 962.212052 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.469830 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 188225426 # number of ReadReq hits
system.cpu.icache.demand_hits 188225426 # number of demand (read+write) hits
system.cpu.icache.overall_hits 188225426 # number of overall hits
system.cpu.icache.ReadReq_misses 255393 # number of ReadReq misses
system.cpu.icache.demand_misses 255393 # number of demand (read+write) misses
system.cpu.icache.overall_misses 255393 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 1672074500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 1672074500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 1672074500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 188480819 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 188480819 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 188480819 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001355 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001355 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001355 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 6547.064720 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 6547.064720 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 6547.064720 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 6 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1431 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1431 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1431 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 253962 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 253962 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 253962 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 874487000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 874487000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 874487000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001347 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.001347 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.001347 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3443.377356 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3443.377356 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3443.377356 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2526689 # number of replacements
system.cpu.dcache.tagsinuse 4088.695138 # Cycle average of tags in use
system.cpu.dcache.total_refs 470723878 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2530785 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 185.999158 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2167120000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4088.695138 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998217 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 321863634 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 147543808 # number of WriteReq hits
system.cpu.dcache.demand_hits 469407442 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 469407442 # number of overall hits
system.cpu.dcache.ReadReq_misses 3006802 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1616393 # number of WriteReq misses
system.cpu.dcache.demand_misses 4623195 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 4623195 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 47968938500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 38293464500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 86262403000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 86262403000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 324870436 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 474030637 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 474030637 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.009255 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.010837 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.009753 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.009753 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 15953.474323 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 23690.689393 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18658.612280 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18658.612280 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 2229828 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1247246 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 605486 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1852732 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1852732 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1759556 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1010907 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2770463 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2770463 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14841103500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 18213023500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 33054127000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 33054127000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005416 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006777 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005844 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005844 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8434.572983 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18016.517345 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11930.903607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11930.903607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 574908 # number of replacements
system.cpu.l2cache.tagsinuse 21475.483997 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3187378 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 594034 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.365649 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 306954721000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7759.424179 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13716.059817 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.236799 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.418581 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1427745 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 2229834 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1220 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 528395 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1956140 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1956140 # number of overall hits
system.cpu.l2cache.ReadReq_misses 338148 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 241457 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 247534 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 585682 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 585682 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 11551208500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 10591500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 8481401000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 20032609500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 20032609500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1765893 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 2229834 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 242677 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 775929 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2541822 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2541822 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.191488 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.994973 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.319016 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.230418 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.230418 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34160.215349 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.864953 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.579953 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34203.901605 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34203.901605 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 2544473 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34201.394643 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 1957943 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 20060144000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.230511 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 586530 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 18184855000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.230511 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 586530 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.writebacks 412029 # number of writebacks
system.cpu.l2cache.occ_blocks::0 7751.549385 # Average occupied blocks per context system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.occ_blocks::1 13703.522900 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.236559 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.418198 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2544473 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34201.394643 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1957943 # number of overall hits
system.cpu.l2cache.overall_miss_latency 20060144000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.230511 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 586530 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 18184855000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_misses 338148 # number of ReadReq MSHR misses
system.cpu.l2cache.overall_mshr_miss_rate 0.230511 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_mshr_misses 241457 # number of UpgradeReq MSHR misses
system.cpu.l2cache.overall_mshr_misses 586530 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 247534 # number of ReadExReq MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.demand_mshr_misses 585682 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 585682 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 575744 # number of replacements system.cpu.l2cache.ReadReq_mshr_miss_latency 10484352000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.sampled_refs 594863 # Sample count of references to valid blocks. system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7486160000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7674186000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18158538000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18158538000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191488 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994973 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319016 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.230418 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.230418 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.216651 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.112533 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.553185 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.090957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.090957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 21455.072285 # Cycle average of tags in use system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.total_refs 3190393 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 306991433000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 412280 # number of writebacks
system.cpu.memDep0.conflictingLoads 354716110 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 139191834 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 586119276 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 223082546 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1024751398 # number of misc regfile reads
system.cpu.numCycles 1168204079 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 50725953 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 53866080 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 461056510 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 8215 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 5693696762 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 2424853504 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 2263021553 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 385257729 # Number of cycles rename is running
system.cpu.rename.SquashCycles 108207267 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 138255029 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 835722526 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 18042 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 5693678720 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 14434 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 2322 # count of serializing insts renamed
system.cpu.rename.skidInsts 301380597 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 2286 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3319156234 # The number of ROB reads
system.cpu.rob.rob_writes 4758159890 # The number of ROB writes
system.cpu.timesIdled 639156 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 14:39:34 M5 started May 16 2011 19:29:23
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -19,4 +19,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.110000 OO-style eon Time= 0.110000
Exiting @ tick 117809491500 because target called exit() Exiting @ tick 117852123500 because target called exit()

963
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,339 +1,153 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 211489 # Simulator instruction rate (inst/s) sim_seconds 0.117852 # Number of seconds simulated
host_mem_usage 270680 # Number of bytes of host memory used sim_ticks 117852123500 # Number of ticks simulated
host_seconds 1650.52 # Real time elapsed on the host
host_tick_rate 71377158 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 349066263 # Number of instructions simulated host_inst_rate 49475 # Simulator instruction rate (inst/s)
sim_seconds 0.117809 # Number of seconds simulated host_tick_rate 16703679 # Simulator tick rate (ticks/s)
sim_ticks 117809491500 # Number of ticks simulated host_mem_usage 264264 # Number of bytes of host memory used
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. host_seconds 7055.46 # Real time elapsed on the host
system.cpu.BPredUnit.BTBHits 21062889 # Number of BTB hits sim_insts 349066258 # Number of instructions simulated
system.cpu.BPredUnit.BTBLookups 27322695 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 72292 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3475103 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 20805254 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 37744082 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 7419277 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 3443737 # The number of times a branch was mispredicted
system.cpu.commit.branches 30521923 # Number of branches committed
system.cpu.commit.bw_lim_events 10435258 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 349066875 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3555485 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 39704049 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 228514950 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.527545 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.133009 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 102801955 44.99% 44.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 53028094 23.21% 68.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 21141032 9.25% 77.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 16471755 7.21% 84.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11485651 5.03% 89.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6931925 3.03% 92.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3277801 1.43% 94.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2941479 1.29% 95.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10435258 4.57% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 228514950 # Number of insts commited each cycle
system.cpu.commit.count 349066875 # Number of instructions committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.int_insts 279586113 # Number of committed integer instructions.
system.cpu.commit.loads 94649044 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.refs 177024913 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 349066263 # Number of Instructions Simulated
system.cpu.committedInsts_total 349066263 # Number of Instructions Simulated
system.cpu.cpi 0.674998 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.674998 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 11411 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 11409 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 96380397 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33471.948212 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30902.675014 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96377153 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 108583000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000034 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 3244 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1487 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 54296000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1757 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 11147 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 11147 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32597.187038 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.657728 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 82033751 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 617651500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 18948 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 16114 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 100478500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2834 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 38865.924635 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 178433096 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 32725.058580 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33712.589850 # average overall mshr miss latency
system.cpu.dcache.demand_hits 178410904 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 726234500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses
system.cpu.dcache.demand_misses 22192 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 17601 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 154774500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4591 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 3098.465756 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.756461 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 178433096 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32725.058580 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33712.589850 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 178410904 # number of overall hits
system.cpu.dcache.overall_miss_latency 726234500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses
system.cpu.dcache.overall_misses 22192 # number of overall misses
system.cpu.dcache.overall_mshr_hits 17601 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 154774500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4591 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1403 # number of replacements
system.cpu.dcache.sampled_refs 4591 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3098.465756 # Cycle average of tags in use
system.cpu.dcache.total_refs 178433460 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1024 # number of writebacks
system.cpu.decode.BlockedCycles 69331294 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 73618 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 7489475 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 420268511 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 84393046 # Number of cycles decode is idle
system.cpu.decode.RunCycles 73199019 # Number of cycles decode is running
system.cpu.decode.SquashCycles 6976526 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 216081 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 1591590 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 37744082 # Number of branches that fetch encountered system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.fetch.CacheLines 40002335 # Number of cache lines fetched system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.fetch.Cycles 76861965 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.fetch.IcacheSquashes 627285 # Number of outstanding Icache misses that were squashed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.fetch.Insts 328341754 # Number of instructions fetch has processed system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.fetch.SquashCycles 3612258 # Number of cycles fetch has spent squashing system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.fetch.branchRate 0.160191 # Number of branch fetches per cycle system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.fetch.icacheStallCycles 40002335 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.fetch.predictedBranches 28482166 # Number of branches that fetch has predicted taken system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.fetch.rate 1.393528 # Number of inst fetches per cycle system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.fetch.rateDist::samples 235491475 # Number of instructions fetched each cycle (Total) system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.fetch.rateDist::mean 1.819242 # Number of instructions fetched each cycle (Total) system.cpu.dtb.hits 0 # DTB hits
system.cpu.fetch.rateDist::stdev 3.041438 # Number of instructions fetched each cycle (Total) system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 235704248 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 37732885 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 20795463 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3471100 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 27302215 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 21001151 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 7420100 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 72463 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 39991725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 328152707 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37732885 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 28421251 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 76800425 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3608252 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 39991725 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 624732 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 235576888 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.817631 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.040837 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 159219706 67.61% 67.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 159366483 67.65% 67.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9262838 3.93% 71.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 9270231 3.94% 71.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5962224 2.53% 74.08% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 5914286 2.51% 74.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6640011 2.82% 76.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 6643493 2.82% 76.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5459111 2.32% 79.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 5462624 2.32% 79.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4841931 2.06% 81.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 4799627 2.04% 81.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3740667 1.59% 82.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 3754754 1.59% 82.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4101328 1.74% 84.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 4137731 1.76% 84.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 36263659 15.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 36227659 15.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 235491475 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 235576888 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 189753142 # number of floating regfile reads system.cpu.fetch.branchRate 0.160086 # Number of branch fetches per cycle
system.cpu.fp_regfile_writes 134299135 # number of floating regfile writes system.cpu.fetch.rate 1.392222 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_accesses 40002335 # number of ReadReq accesses(hits+misses) system.cpu.decode.IdleCycles 84492760 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_miss_latency 11799.645611 # average ReadReq miss latency system.cpu.decode.BlockedCycles 69387883 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8377.979424 # average ReadReq mshr miss latency system.cpu.decode.RunCycles 73181829 # Number of cycles decode is running
system.cpu.icache.ReadReq_hits 39986251 # number of ReadReq hits system.cpu.decode.UnblockCycles 1548924 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_latency 189785500 # number of ReadReq miss cycles system.cpu.decode.SquashCycles 6965492 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_miss_rate 0.000402 # miss rate for ReadReq accesses system.cpu.decode.BranchResolved 7488186 # Number of times decode resolved a branch
system.cpu.icache.ReadReq_misses 16084 # number of ReadReq misses system.cpu.decode.BranchMispred 73175 # Number of times decode detected a branch misprediction
system.cpu.icache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits system.cpu.decode.DecodedInsts 420043685 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_latency 131107000 # number of ReadReq MSHR miss cycles system.cpu.decode.SquashedInsts 215754 # Number of squashed instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_rate 0.000391 # mshr miss rate for ReadReq accesses system.cpu.rename.SquashCycles 6965492 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_misses 15649 # number of ReadReq MSHR misses system.cpu.rename.IdleCycles 90152933 # Number of cycles rename is idle
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.BlockCycles 976284 # Number of cycles rename is blocking
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.serializeStallCycles 57875196 # count of cycles rename stalled for serializing inst
system.cpu.icache.avg_refs 2555.195284 # Average number of references to valid blocks. system.cpu.rename.RunCycles 69216447 # Number of cycles rename is running
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.UnblockCycles 10390536 # Number of cycles rename is unblocking
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedInsts 409431138 # Number of instructions processed by rename
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 10006 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 5114847 # Number of times rename has blocked due to LSQ full
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.FullRegisterEvents 42 # Number of times there has been no free registers
system.cpu.icache.demand_accesses 40002335 # number of demand (read+write) accesses system.cpu.rename.RenamedOperands 449313195 # Number of destination operands rename has renamed
system.cpu.icache.demand_avg_miss_latency 11799.645611 # average overall miss latency system.cpu.rename.RenameLookups 2409887049 # Number of register rename lookups that rename has made
system.cpu.icache.demand_avg_mshr_miss_latency 8377.979424 # average overall mshr miss latency system.cpu.rename.int_rename_lookups 1322854173 # Number of integer rename lookups
system.cpu.icache.demand_hits 39986251 # number of demand (read+write) hits system.cpu.rename.fp_rename_lookups 1087032876 # Number of floating rename lookups
system.cpu.icache.demand_miss_latency 189785500 # number of demand (read+write) miss cycles system.cpu.rename.CommittedMaps 384568949 # Number of HB maps that are committed
system.cpu.icache.demand_miss_rate 0.000402 # miss rate for demand accesses system.cpu.rename.UndoneMaps 64744241 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_misses 16084 # number of demand (read+write) misses system.cpu.rename.serializingInsts 3898927 # count of serializing insts renamed
system.cpu.icache.demand_mshr_hits 435 # number of demand (read+write) MSHR hits system.cpu.rename.tempSerializingInsts 3897858 # count of temporary serializing insts renamed
system.cpu.icache.demand_mshr_miss_latency 131107000 # number of demand (read+write) MSHR miss cycles system.cpu.rename.skidInsts 35694607 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_miss_rate 0.000391 # mshr miss rate for demand accesses system.cpu.memDep0.insertedLoads 106772052 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_misses 15649 # number of demand (read+write) MSHR misses system.cpu.memDep0.insertedStores 90018438 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.memDep0.conflictingLoads 11281294 # Number of conflicting loads.
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.memDep0.conflictingStores 21363407 # Number of conflicting stores.
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqInstsAdded 384862513 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.occ_blocks::0 1826.046295 # Average occupied blocks per context system.cpu.iq.iqNonSpecInstsAdded 3813526 # Number of non-speculative instructions added to the IQ
system.cpu.icache.occ_percent::0 0.891624 # Average percentage of cache occupancy system.cpu.iq.iqInstsIssued 372770888 # Number of instructions issued
system.cpu.icache.overall_accesses 40002335 # number of overall (read+write) accesses system.cpu.iq.iqSquashedInstsIssued 1408906 # Number of squashed instructions issued
system.cpu.icache.overall_avg_miss_latency 11799.645611 # average overall miss latency system.cpu.iq.iqSquashedInstsExamined 37984896 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.overall_avg_mshr_miss_latency 8377.979424 # average overall mshr miss latency system.cpu.iq.iqSquashedOperandsExamined 125485450 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.iqSquashedNonSpecRemoved 258042 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_hits 39986251 # number of overall hits system.cpu.iq.issued_per_cycle::samples 235576888 # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 189785500 # number of overall miss cycles system.cpu.iq.issued_per_cycle::mean 1.582375 # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.000402 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::stdev 1.822791 # Number of insts issued each cycle
system.cpu.icache.overall_misses 16084 # number of overall misses system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 435 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::0 95699423 40.62% 40.62% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 131107000 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::1 48065676 20.40% 61.03% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.000391 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::2 27569248 11.70% 72.73% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 15649 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::3 20762200 8.81% 81.54% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::4 21955543 9.32% 90.86% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::5 12942689 5.49% 96.36% # Number of insts issued each cycle
system.cpu.icache.replacements 13784 # number of replacements system.cpu.iq.issued_per_cycle::6 5977724 2.54% 98.89% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 15649 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::7 1956925 0.83% 99.73% # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::8 647460 0.27% 100.00% # Number of insts issued each cycle
system.cpu.icache.tagsinuse 1826.046295 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.total_refs 39986251 # Total number of references to valid blocks. system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iq.issued_per_cycle::total 235576888 # Number of insts issued each cycle
system.cpu.idleCycles 127509 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 3670203 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 31934668 # Number of branches executed
system.cpu.iew.exec_nop 47192 # number of nop insts executed
system.cpu.iew.exec_rate 1.564151 # Inst execution rate
system.cpu.iew.exec_refs 185570349 # number of memory reference insts executed
system.cpu.iew.exec_stores 84541959 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 10926 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 106791761 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 3802356 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6858543 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 90029129 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 388774140 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 101028390 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4246307 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 368543664 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 71 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 337 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 6976526 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 499 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 168 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 4560961 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 25223 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 199743 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 301 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 12142716 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 7653260 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 199743 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 359811 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3310392 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 317090964 # num instructions consuming a value
system.cpu.iew.wb_count 365218926 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.522267 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 165606023 # num instructions producing a value
system.cpu.iew.wb_rate 1.550040 # insts written-back per cycle
system.cpu.iew.wb_sent 366001659 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 1759246608 # number of integer regfile reads
system.cpu.int_regfile_writes 232102222 # number of integer regfile writes
system.cpu.ipc 1.481486 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.481486 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 126463418 33.92% 33.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2147037 0.58% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6836747 1.83% 36.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8624018 2.31% 38.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3527986 0.95% 39.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1580654 0.42% 40.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21035747 5.64% 45.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7283008 1.95% 47.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7262175 1.95% 49.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 102247784 27.43% 77.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 85606108 22.96% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 372789971 # Type of FU issued
system.cpu.iq.fp_alu_accesses 127821933 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 249342196 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 118185962 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 133232335 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 13475549 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.036148 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2445 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2414 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available
@ -353,170 +167,363 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # at
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 11285 0.08% 0.14% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 11301 0.09% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.14% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 187 0.00% 0.14% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 197 0.00% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 1509 0.01% 0.15% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 1510 0.01% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.15% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 142639 1.06% 1.21% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 142649 1.07% 1.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 1245 0.01% 1.22% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 1224 0.01% 1.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 303363 2.25% 3.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 303363 2.28% 3.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7221179 53.59% 57.06% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 7115466 53.58% 57.10% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5786651 42.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 5697057 42.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 258443587 # Number of integer alu accesses system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.int_inst_queue_reads 746613752 # Number of integer instruction queue reads system.cpu.iq.FU_type_0::IntAlu 126467737 33.93% 33.93% # Type of FU issued
system.cpu.iq.int_inst_queue_wakeup_accesses 247032964 # Number of integer instruction queue wakeup accesses system.cpu.iq.FU_type_0::IntMult 2147032 0.58% 34.50% # Type of FU issued
system.cpu.iq.int_inst_queue_writes 293633638 # Number of integer instruction queue writes system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqInstsAdded 384913340 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqInstsIssued 372789971 # Number of instructions issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqNonSpecInstsAdded 3813608 # Number of non-speculative instructions added to the IQ system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqSquashedInstsExamined 38043864 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqSquashedInstsIssued 1408982 # Number of squashed instructions issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqSquashedNonSpecRemoved 258123 # Number of squashed non-spec instructions that were removed system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.iqSquashedOperandsExamined 125676657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::samples 235491475 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::mean 1.583030 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::stdev 1.821450 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::0 95677321 40.63% 40.63% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::1 47888075 20.34% 60.96% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::2 27520727 11.69% 72.65% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::3 20838545 8.85% 81.50% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::4 22281426 9.46% 90.96% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::5 12633898 5.36% 96.33% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.issued_per_cycle::6 6146913 2.61% 98.94% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAdd 6836061 1.83% 36.34% # Type of FU issued
system.cpu.iq.issued_per_cycle::7 1868425 0.79% 99.73% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.34% # Type of FU issued
system.cpu.iq.issued_per_cycle::8 636145 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCmp 8620472 2.31% 38.65% # Type of FU issued
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCvt 3526603 0.95% 39.59% # Type of FU issued
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatDiv 1580695 0.42% 40.02% # Type of FU issued
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMisc 21030277 5.64% 45.66% # Type of FU issued
system.cpu.iq.issued_per_cycle::total 235491475 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMult 7283358 1.95% 47.61% # Type of FU issued
system.cpu.iq.rate 1.582173 # Inst issue rate system.cpu.iq.FU_type_0::SimdFloatMultAcc 7262499 1.95% 49.56% # Type of FU issued
system.cpu.itb.accesses 0 # DTB accesses system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.61% # Type of FU issued
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.iq.FU_type_0::MemRead 102234129 27.43% 77.04% # Type of FU issued
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.iq.FU_type_0::MemWrite 85606734 22.96% 100.00% # Type of FU issued
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.iq.FU_type_0::total 372770888 # Type of FU issued
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.iq.rate 1.581520 # Inst issue rate
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.iq.fu_busy_cnt 13280227 # FU busy when requested
system.cpu.itb.hits 0 # DTB hits system.cpu.iq.fu_busy_rate 0.035626 # FU busy rate (busy events/executed inst)
system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.iq.int_inst_queue_reads 746488455 # Number of integer instruction queue reads
system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.iq.int_inst_queue_writes 293551634 # Number of integer instruction queue writes
system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.iq.int_inst_queue_wakeup_accesses 247041034 # Number of integer instruction queue wakeup accesses
system.cpu.itb.misses 0 # DTB misses system.cpu.iq.fp_inst_queue_reads 249319342 # Number of floating instruction queue reads
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.iq.fp_inst_queue_writes 133204458 # Number of floating instruction queue writes
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.iq.fp_inst_queue_wakeup_accesses 118172579 # Number of floating instruction queue wakeup accesses
system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.iq.int_alu_accesses 258240891 # Number of integer alu accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.iq.fp_alu_accesses 127810224 # Number of floating point alu accesses
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.iew.lsq.thread0.forwLoads 4605348 # Number of loads that had data forwarded from stores
system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.itb.write_hits 0 # DTB write hits system.cpu.iew.lsq.thread0.squashedLoads 12123008 # Number of loads squashed
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.iew.lsq.thread0.ignoredResponses 25231 # Number of memory responses ignored because the instruction is squashed
system.cpu.l2cache.ReadExReq_accesses 2834 # number of ReadExReq accesses(hits+misses) system.cpu.iew.lsq.thread0.memOrderViolation 199737 # Number of memory ordering violations
system.cpu.l2cache.ReadExReq_avg_miss_latency 34401.668442 # average ReadExReq miss latency system.cpu.iew.lsq.thread0.squashedStores 7642570 # Number of stores squashed
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31268.903088 # average ReadExReq mshr miss latency system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 301 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 168 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 6965492 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 10869 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 480 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 388723243 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 6854795 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 106772052 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 90018438 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3802280 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 199737 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3305937 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 361135 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3667072 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 368528754 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 101011008 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4242134 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 47204 # number of nop insts executed
system.cpu.iew.exec_refs 185554303 # number of memory reference insts executed
system.cpu.iew.exec_branches 31933479 # Number of branches executed
system.cpu.iew.exec_stores 84543295 # Number of stores executed
system.cpu.iew.exec_rate 1.563522 # Inst execution rate
system.cpu.iew.wb_sent 365991200 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 365213613 # cumulative count of insts written-back
system.cpu.iew.wb_producers 165367337 # num instructions producing a value
system.cpu.iew.wb_consumers 317313225 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.549457 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.521149 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 349066870 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 39653224 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3555484 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3440231 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 228611397 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.526901 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.127678 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 102653839 44.90% 44.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 52967573 23.17% 68.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 21494828 9.40% 77.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 16426131 7.19% 84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11610822 5.08% 89.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6946497 3.04% 92.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3261718 1.43% 94.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2914745 1.27% 95.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10335244 4.52% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 228611397 # Number of insts commited each cycle
system.cpu.commit.count 349066870 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 177024911 # Number of memory references committed
system.cpu.commit.loads 94649043 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.branches 30521922 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279586109 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.bw_lim_events 10335244 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 606993724 # The number of ROB reads
system.cpu.rob.rob_writes 784416922 # The number of ROB writes
system.cpu.timesIdled 2785 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 127360 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 349066258 # Number of Instructions Simulated
system.cpu.committedInsts_total 349066258 # Number of Instructions Simulated
system.cpu.cpi 0.675242 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.675242 # CPI: Total CPI of All Threads
system.cpu.ipc 1.480950 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.480950 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1759160975 # number of integer regfile reads
system.cpu.int_regfile_writes 232094825 # number of integer regfile writes
system.cpu.fp_regfile_reads 189729002 # number of floating regfile reads
system.cpu.fp_regfile_writes 134274190 # number of floating regfile writes
system.cpu.misc_regfile_reads 986066945 # number of misc regfile reads
system.cpu.misc_regfile_writes 34422257 # number of misc regfile writes
system.cpu.icache.replacements 13781 # number of replacements
system.cpu.icache.tagsinuse 1824.800983 # Cycle average of tags in use
system.cpu.icache.total_refs 39975644 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2555.497283 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1824.800983 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.891016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 39975644 # number of ReadReq hits
system.cpu.icache.demand_hits 39975644 # number of demand (read+write) hits
system.cpu.icache.overall_hits 39975644 # number of overall hits
system.cpu.icache.ReadReq_misses 16081 # number of ReadReq misses
system.cpu.icache.demand_misses 16081 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16081 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 189840000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 189840000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 189840000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 39991725 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 39991725 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 39991725 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000402 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000402 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000402 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 11805.235993 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 11805.235993 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 11805.235993 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 435 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 435 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 15646 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 15646 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 15646 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 131146500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 131146500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 131146500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000391 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000391 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000391 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8382.110444 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1396 # number of replacements
system.cpu.dcache.tagsinuse 3097.520126 # Cycle average of tags in use
system.cpu.dcache.total_refs 178371323 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4582 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 38928.704278 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3097.520126 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.756230 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 96315033 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 82033723 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 11410 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 178348756 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 178348756 # number of overall hits
system.cpu.dcache.ReadReq_misses 3256 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 18976 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 22232 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 22232 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 108888000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 618616000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 727504000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 727504000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 96318289 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 11412 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 178370988 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 178370988 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000034 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 33442.260442 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 32599.915683 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 32723.281756 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 32723.281756 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1019 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1507 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 16140 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 17647 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 17647 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1749 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2836 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4585 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4585 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 54106000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 100544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 154650000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 154650000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30935.391652 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35452.750353 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 54 # number of replacements
system.cpu.l2cache.tagsinuse 3793.062863 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13102 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5236 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.502292 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3424.878969 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 368.183894 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.104519 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011236 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 13017 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1019 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 96909500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_hits 13034 # number of demand (read+write) hits
system.cpu.l2cache.ReadExReq_miss_rate 0.994001 # miss rate for ReadExReq accesses system.cpu.l2cache.overall_hits 13034 # number of overall hits
system.cpu.l2cache.ReadExReq_misses 2817 # number of ReadExReq misses system.cpu.l2cache.ReadReq_misses 4374 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88084500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994001 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 2816 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_misses 2817 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_misses 7190 # number of demand (read+write) misses
system.cpu.l2cache.ReadReq_accesses 17406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.overall_misses 7190 # number of overall misses
system.cpu.l2cache.ReadReq_avg_miss_latency 34339.881224 # average ReadReq miss latency system.cpu.l2cache.ReadReq_miss_latency 150210000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.877485 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 96886500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_hits 13028 # number of ReadReq hits system.cpu.l2cache.demand_miss_latency 247096500 # number of demand (read+write) miss cycles
system.cpu.l2cache.ReadReq_miss_latency 150340000 # number of ReadReq miss cycles system.cpu.l2cache.overall_miss_latency 247096500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.251522 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_accesses 17391 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_misses 4378 # number of ReadReq misses system.cpu.l2cache.Writeback_accesses 1019 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_mshr_miss_latency 134776000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_accesses 2833 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.248535 # mshr miss rate for ReadReq accesses system.cpu.l2cache.demand_accesses 20224 # number of demand (read+write) accesses
system.cpu.l2cache.ReadReq_mshr_misses 4326 # number of ReadReq MSHR misses system.cpu.l2cache.overall_accesses 20224 # number of overall (read+write) accesses
system.cpu.l2cache.Writeback_accesses 1024 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadReq_miss_rate 0.251509 # miss rate for ReadReq accesses
system.cpu.l2cache.Writeback_hits 1024 # number of Writeback hits system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_miss_rate 0.993999 # miss rate for ReadExReq accesses
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.demand_miss_rate 0.355518 # miss rate for demand accesses
system.cpu.l2cache.avg_refs 2.500763 # Average number of references to valid blocks. system.cpu.l2cache.overall_miss_rate 0.355518 # miss rate for overall accesses
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.ReadReq_avg_miss_latency 34341.563786 # average ReadReq miss latency
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.717330 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34366.689847 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34366.689847 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 20240 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34364.072272 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31199.846003 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 13045 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 247249500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.355484 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7195 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 222860500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.352915 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7143 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 3426.953059 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 371.809740 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.104582 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011347 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 20240 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34364.072272 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31199.846003 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 13045 # number of overall hits
system.cpu.l2cache.overall_miss_latency 247249500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.355484 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7195 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 52 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 222860500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.352915 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7143 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 53 # number of replacements
system.cpu.l2cache.sampled_refs 5244 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3798.762799 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13114 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 11716702 # Number of conflicting loads. system.cpu.l2cache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
system.cpu.memDep0.conflictingStores 21387957 # Number of conflicting stores. system.cpu.l2cache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits
system.cpu.memDep0.insertedLoads 106791761 # Number of loads inserted to the mem dependence unit. system.cpu.l2cache.overall_mshr_hits 51 # number of overall MSHR hits
system.cpu.memDep0.insertedStores 90029129 # Number of stores inserted to the mem dependence unit. system.cpu.l2cache.ReadReq_mshr_misses 4323 # number of ReadReq MSHR misses
system.cpu.misc_regfile_reads 986366370 # number of misc regfile reads system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
system.cpu.misc_regfile_writes 34422259 # number of misc regfile writes system.cpu.l2cache.ReadExReq_mshr_misses 2816 # number of ReadExReq MSHR misses
system.cpu.numCycles 235618984 # number of cpu cycles simulated system.cpu.l2cache.demand_mshr_misses 7139 # number of demand (read+write) MSHR misses
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.l2cache.overall_mshr_misses 7139 # number of overall MSHR misses
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.rename.BlockCycles 1027175 # Number of cycles rename is blocking system.cpu.l2cache.ReadReq_mshr_miss_latency 134686000 # number of ReadReq MSHR miss cycles
system.cpu.rename.CommittedMaps 384568957 # Number of HB maps that are committed system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
system.cpu.rename.FullRegisterEvents 42 # Number of times there has been no free registers system.cpu.l2cache.ReadExReq_mshr_miss_latency 88056000 # number of ReadExReq MSHR miss cycles
system.cpu.rename.IQFullEvents 10287 # Number of times rename has blocked due to IQ full system.cpu.l2cache.demand_mshr_miss_latency 222742000 # number of demand (read+write) MSHR miss cycles
system.cpu.rename.IdleCycles 90102617 # Number of cycles rename is idle system.cpu.l2cache.overall_mshr_miss_latency 222742000 # number of overall MSHR miss cycles
system.cpu.rename.LSQFullEvents 5005619 # Number of times rename has blocked due to LSQ full system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.rename.RenameLookups 2410888164 # Number of register rename lookups that rename has made system.cpu.l2cache.ReadReq_mshr_miss_rate 0.248577 # mshr miss rate for ReadReq accesses
system.cpu.rename.RenamedInsts 409625398 # Number of instructions processed by rename system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.rename.RenamedOperands 449508319 # Number of destination operands rename has renamed system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993999 # mshr miss rate for ReadExReq accesses
system.cpu.rename.RunCycles 69271276 # Number of cycles rename is running system.cpu.l2cache.demand_mshr_miss_rate 0.352996 # mshr miss rate for demand accesses
system.cpu.rename.SquashCycles 6976526 # Number of cycles rename is squashing system.cpu.l2cache.overall_mshr_miss_rate 0.352996 # mshr miss rate for overall accesses
system.cpu.rename.UnblockCycles 10236681 # Number of cycles rename is unblocking system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.678927 # average ReadReq mshr miss latency
system.cpu.rename.UndoneMaps 64939357 # Number of HB maps that are undone due to squashing system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.rename.fp_rename_lookups 1087176407 # Number of floating rename lookups system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.886364 # average ReadExReq mshr miss latency
system.cpu.rename.int_rename_lookups 1323711757 # Number of integer rename lookups system.cpu.l2cache.demand_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency
system.cpu.rename.serializeStallCycles 57877200 # count of cycles rename stalled for serializing inst system.cpu.l2cache.overall_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency
system.cpu.rename.serializingInsts 3899205 # count of serializing insts renamed system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.rename.skidInsts 35615164 # count of insts added to the skid buffer system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.rename.tempSerializingInsts 3898099 # count of temporary serializing insts renamed system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.rob.rob_reads 606848093 # The number of ROB reads system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.rob.rob_writes 784529626 # The number of ROB writes
system.cpu.timesIdled 2791 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 191 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 14:08:54 M5 started May 16 2011 15:11:57
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -1391,4 +1391,4 @@ info: Increasing stack size by one page.
2000: 760651391 2000: 760651391
1000: 4031656975 1000: 4031656975
0: 2206428413 0: 2206428413
Exiting @ tick 796501458500 because target called exit() Exiting @ tick 795626752000 because target called exit()

1010
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -7,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 15:24:46 M5 started May 16 2011 15:12:09
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Exiting @ tick 36353754500 because target called exit() Exiting @ tick 36348210000 because target called exit()

1011
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 15:15:49 M5 started May 16 2011 19:27:10
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -30,4 +30,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 567799725500 because target called exit() Exiting @ tick 566011920000 because target called exit()

944
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,340 +1,154 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 218238 # Simulator instruction rate (inst/s) sim_seconds 0.566012 # Number of seconds simulated
host_mem_usage 262044 # Number of bytes of host memory used sim_ticks 566011920000 # Number of ticks simulated
host_seconds 7895.40 # Real time elapsed on the host
host_tick_rate 71915281 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1723073864 # Number of instructions simulated host_inst_rate 52057 # Simulator instruction rate (inst/s)
sim_seconds 0.567800 # Number of seconds simulated host_tick_rate 17100212 # Simulator tick rate (ticks/s)
sim_ticks 567799725500 # Number of ticks simulated host_mem_usage 255500 # Number of bytes of host memory used
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. host_seconds 33099.70 # Real time elapsed on the host
system.cpu.BPredUnit.BTBHits 215471079 # Number of BTB hits sim_insts 1723073884 # Number of instructions simulated
system.cpu.BPredUnit.BTBLookups 251238209 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 391 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 18325747 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 236131073 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 286913964 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 18098794 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 18325219 # The number of times a branch was mispredicted
system.cpu.commit.branches 213462368 # Number of branches committed
system.cpu.commit.bw_lim_events 71826225 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 1723073882 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 460 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 387631176 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 1070469701 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.609643 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.327352 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 480995228 44.93% 44.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 256180333 23.93% 68.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110567341 10.33% 79.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 54815725 5.12% 84.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28914668 2.70% 87.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 29042780 2.71% 89.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 21062487 1.97% 91.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 17064914 1.59% 93.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 71826225 6.71% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1070469701 # Number of insts commited each cycle
system.cpu.commit.count 1723073882 # Number of instructions committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.int_insts 1536941865 # Number of committed integer instructions.
system.cpu.commit.loads 485926774 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.refs 660773823 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1723073864 # Number of Instructions Simulated
system.cpu.committedInsts_total 1723073864 # Number of Instructions Simulated
system.cpu.cpi 0.659054 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.659054 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 70 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 67 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.042857 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 520005687 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 17036.313346 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11712.292709 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509774132 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 174307977000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019676 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 10231555 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 2567467 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 89764042000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014738 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7664088 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 65 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 24384.889096 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22421.774164 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 167960973 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 112781916549 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.026799 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4625074 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2732851 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 42426996773 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1892223 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4138.422705 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20785.714286 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 70.920174 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 35824 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 148254855 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 145500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 692591734 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19324.026571 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13832.852319 # average overall mshr miss latency
system.cpu.dcache.demand_hits 677735105 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 287089893549 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.021451 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14856629 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5300318 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 132191038773 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013798 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9556311 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 4083.025990 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.996833 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 692591734 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19324.026571 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13832.852319 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 677735105 # number of overall hits
system.cpu.dcache.overall_miss_latency 287089893549 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.021451 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14856629 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5300318 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 132191038773 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013798 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9556311 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9552215 # number of replacements
system.cpu.dcache.sampled_refs 9556311 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4083.025990 # Cycle average of tags in use
system.cpu.dcache.total_refs 677735237 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6495250000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3126399 # number of writebacks
system.cpu.decode.BlockedCycles 74308472 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 637 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 43193928 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 2255287801 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 552391486 # Number of cycles decode is idle
system.cpu.decode.RunCycles 436619657 # Number of cycles decode is running
system.cpu.decode.SquashCycles 60139906 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 2271 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 7150085 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 286913964 # Number of branches that fetch encountered system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.fetch.CacheLines 267974440 # Number of cache lines fetched system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.fetch.Cycles 453847586 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.fetch.IcacheSquashes 5761362 # Number of outstanding Icache misses that were squashed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.fetch.Insts 2078528457 # Number of instructions fetch has processed system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.fetch.SquashCycles 20230062 # Number of cycles fetch has spent squashing system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.fetch.branchRate 0.252654 # Number of branch fetches per cycle system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.fetch.icacheStallCycles 267974440 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.fetch.predictedBranches 233569873 # Number of branches that fetch has predicted taken system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.fetch.rate 1.830336 # Number of inst fetches per cycle system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.fetch.rateDist::samples 1130609606 # Number of instructions fetched each cycle (Total) system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.fetch.rateDist::mean 2.039152 # Number of instructions fetched each cycle (Total) system.cpu.dtb.hits 0 # DTB hits
system.cpu.fetch.rateDist::stdev 2.930908 # Number of instructions fetched each cycle (Total) system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1132023841 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 287218932 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 236434259 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18348095 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 250920104 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 213740165 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18278609 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 393 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 265451297 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2081730004 # Number of instructions fetch has processed
system.cpu.fetch.Branches 287218932 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 232018774 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 452716467 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 20281434 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 265451297 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5801201 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1120688032 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.061143 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.942664 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 676762075 59.86% 59.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 667971623 59.60% 59.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 34315412 3.04% 62.89% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 32961041 2.94% 62.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 55733130 4.93% 67.82% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 55903718 4.99% 67.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 58083869 5.14% 72.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 56895013 5.08% 72.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 45528699 4.03% 76.99% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 45557119 4.07% 76.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 55300610 4.89% 81.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 54242890 4.84% 81.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 46771165 4.14% 86.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 48750643 4.35% 85.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18710110 1.65% 87.67% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 18749981 1.67% 87.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 139404536 12.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 139656004 12.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1130609606 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1120688032 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 48 # number of floating regfile reads system.cpu.fetch.branchRate 0.253722 # Number of branch fetches per cycle
system.cpu.fp_regfile_writes 48 # number of floating regfile writes system.cpu.fetch.rate 1.838945 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_accesses 267974440 # number of ReadReq accesses(hits+misses) system.cpu.decode.IdleCycles 546126816 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_miss_latency 35169.574700 # average ReadReq miss latency system.cpu.decode.BlockedCycles 71463989 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34452.712100 # average ReadReq mshr miss latency system.cpu.decode.RunCycles 435974123 # Number of cycles decode is running
system.cpu.icache.ReadReq_hits 267973523 # number of ReadReq hits system.cpu.decode.UnblockCycles 6702645 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_latency 32250500 # number of ReadReq miss cycles system.cpu.decode.SquashCycles 60420459 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.decode.BranchResolved 43189829 # Number of times decode resolved a branch
system.cpu.icache.ReadReq_misses 917 # number of ReadReq misses system.cpu.decode.BranchMispred 635 # Number of times decode detected a branch misprediction
system.cpu.icache.ReadReq_mshr_hits 198 # number of ReadReq MSHR hits system.cpu.decode.DecodedInsts 2259641783 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_latency 24771500 # number of ReadReq MSHR miss cycles system.cpu.decode.SquashedInsts 2302 # Number of squashed instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.rename.SquashCycles 60420459 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_misses 719 # number of ReadReq MSHR misses system.cpu.rename.IdleCycles 563998095 # Number of cycles rename is idle
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.BlockCycles 40175582 # Number of cycles rename is blocking
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.serializeStallCycles 14256 # count of cycles rename stalled for serializing inst
system.cpu.icache.avg_refs 372703.091794 # Average number of references to valid blocks. system.cpu.rename.RunCycles 424146965 # Number of cycles rename is running
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.UnblockCycles 31932675 # Number of cycles rename is unblocking
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedInsts 2194117520 # Number of instructions processed by rename
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.ROBFullEvents 11722 # Number of times rename has blocked due to ROB full
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 3482918 # Number of times rename has blocked due to IQ full
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.LSQFullEvents 25684334 # Number of times rename has blocked due to LSQ full
system.cpu.icache.demand_accesses 267974440 # number of demand (read+write) accesses system.cpu.rename.RenamedOperands 2171048745 # Number of destination operands rename has renamed
system.cpu.icache.demand_avg_miss_latency 35169.574700 # average overall miss latency system.cpu.rename.RenameLookups 10125608138 # Number of register rename lookups that rename has made
system.cpu.icache.demand_avg_mshr_miss_latency 34452.712100 # average overall mshr miss latency system.cpu.rename.int_rename_lookups 10125607580 # Number of integer rename lookups
system.cpu.icache.demand_hits 267973523 # number of demand (read+write) hits system.cpu.rename.fp_rename_lookups 558 # Number of floating rename lookups
system.cpu.icache.demand_miss_latency 32250500 # number of demand (read+write) miss cycles system.cpu.rename.CommittedMaps 1706320007 # Number of HB maps that are committed
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.rename.UndoneMaps 464728733 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_misses 917 # number of demand (read+write) misses system.cpu.rename.serializingInsts 633 # count of serializing insts renamed
system.cpu.icache.demand_mshr_hits 198 # number of demand (read+write) MSHR hits system.cpu.rename.tempSerializingInsts 629 # count of temporary serializing insts renamed
system.cpu.icache.demand_mshr_miss_latency 24771500 # number of demand (read+write) MSHR miss cycles system.cpu.rename.skidInsts 66642282 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.memDep0.insertedLoads 598549667 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_misses 719 # number of demand (read+write) MSHR misses system.cpu.memDep0.insertedStores 212535274 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.memDep0.conflictingLoads 87730642 # Number of conflicting loads.
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.memDep0.conflictingStores 84698913 # Number of conflicting stores.
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqInstsAdded 2112468775 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.occ_blocks::0 573.603161 # Average occupied blocks per context system.cpu.iq.iqNonSpecInstsAdded 616 # Number of non-speculative instructions added to the IQ
system.cpu.icache.occ_percent::0 0.280080 # Average percentage of cache occupancy system.cpu.iq.iqInstsIssued 1975042527 # Number of instructions issued
system.cpu.icache.overall_accesses 267974440 # number of overall (read+write) accesses system.cpu.iq.iqSquashedInstsIssued 852567 # Number of squashed instructions issued
system.cpu.icache.overall_avg_miss_latency 35169.574700 # average overall miss latency system.cpu.iq.iqSquashedInstsExamined 380766314 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.overall_avg_mshr_miss_latency 34452.712100 # average overall mshr miss latency system.cpu.iq.iqSquashedOperandsExamined 858455180 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_hits 267973523 # number of overall hits system.cpu.iq.issued_per_cycle::samples 1120688032 # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 32250500 # number of overall miss cycles system.cpu.iq.issued_per_cycle::mean 1.762348 # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::stdev 1.680120 # Number of insts issued each cycle
system.cpu.icache.overall_misses 917 # number of overall misses system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 198 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::0 337912961 30.15% 30.15% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 24771500 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::1 234234895 20.90% 51.05% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::2 220010483 19.63% 70.69% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 719 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::3 141420525 12.62% 83.30% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::4 101836492 9.09% 92.39% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::5 53894209 4.81% 97.20% # Number of insts issued each cycle
system.cpu.icache.replacements 10 # number of replacements system.cpu.iq.issued_per_cycle::6 20983167 1.87% 99.07% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 719 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::7 9353324 0.83% 99.91% # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::8 1041976 0.09% 100.00% # Number of insts issued each cycle
system.cpu.icache.tagsinuse 573.603161 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.total_refs 267973523 # Total number of references to valid blocks. system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iq.issued_per_cycle::total 1120688032 # Number of insts issued each cycle
system.cpu.idleCycles 4989846 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 20125806 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 235514393 # Number of branches executed
system.cpu.iew.exec_nop 296 # number of nop insts executed
system.cpu.iew.exec_rate 1.713630 # Inst execution rate
system.cpu.iew.exec_refs 742460046 # number of memory reference insts executed
system.cpu.iew.exec_stores 185795418 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 18248815 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 598179019 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 540 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6117477 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 212168948 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2110540592 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 556664628 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 28602946 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1945996752 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 245772 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 55469 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 60139906 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 1077846 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 273714 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 32169435 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 459248 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 1853009 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 112252244 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 37321899 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1853009 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3267376 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 16858430 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 1884646665 # num instructions consuming a value
system.cpu.iew.wb_count 1921636859 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.642567 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1211011051 # num instructions producing a value
system.cpu.iew.wb_rate 1.692178 # insts written-back per cycle
system.cpu.iew.wb_sent 1926273504 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 9735130843 # number of integer regfile reads
system.cpu.int_regfile_writes 1902150318 # number of integer regfile writes
system.cpu.ipc 1.517325 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.517325 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1219271237 61.75% 61.75% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1051701 0.05% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 12 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 566539676 28.69% 90.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 187737057 9.51% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1974599698 # Type of FU issued
system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 168 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 24432078 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012373 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 518261 2.12% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 517494 2.12% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 2 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available
@ -362,161 +176,347 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.12% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 23578927 96.51% 98.63% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 23433886 96.11% 98.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 334888 1.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 430313 1.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 1999031702 # Number of integer alu accesses system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.int_inst_queue_reads 5105133398 # Number of integer instruction queue reads system.cpu.iq.FU_type_0::IntAlu 1219473147 61.74% 61.74% # Type of FU issued
system.cpu.iq.int_inst_queue_wakeup_accesses 1921636797 # Number of integer instruction queue wakeup accesses system.cpu.iq.FU_type_0::IntMult 1083372 0.05% 61.80% # Type of FU issued
system.cpu.iq.int_inst_queue_writes 2491239828 # Number of integer instruction queue writes system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqInstsAdded 2110539690 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqInstsIssued 1974599698 # Number of instructions issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqNonSpecInstsAdded 606 # Number of non-speculative instructions added to the IQ system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqSquashedInstsExamined 378853333 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqSquashedInstsIssued 892460 # Number of squashed instructions issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqSquashedNonSpecRemoved 146 # Number of squashed non-spec instructions that were removed system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.iqSquashedOperandsExamined 851689687 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::samples 1130609606 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::mean 1.746491 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::stdev 1.678752 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::0 343530730 30.38% 30.38% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::1 241793067 21.39% 51.77% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::2 218551738 19.33% 71.10% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::3 140017220 12.38% 83.49% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::4 100970740 8.93% 92.42% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::5 54673459 4.84% 97.25% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::6 20221073 1.79% 99.04% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::7 9737830 0.86% 99.90% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::8 1113749 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.80% # Type of FU issued
system.cpu.iq.issued_per_cycle::total 1130609606 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.rate 1.738817 # Inst issue rate system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.itb.accesses 0 # DTB accesses system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.iq.FU_type_0::MemRead 566098039 28.66% 90.46% # Type of FU issued
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.iq.FU_type_0::MemWrite 188387953 9.54% 100.00% # Type of FU issued
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.iq.FU_type_0::total 1975042527 # Type of FU issued
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.iq.rate 1.744700 # Inst issue rate
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.iq.fu_busy_cnt 24381694 # FU busy when requested
system.cpu.itb.hits 0 # DTB hits system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst)
system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.iq.int_inst_queue_reads 5096007233 # Number of integer instruction queue reads
system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.iq.int_inst_queue_writes 2495143403 # Number of integer instruction queue writes
system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.iq.int_inst_queue_wakeup_accesses 1922135162 # Number of integer instruction queue wakeup accesses
system.cpu.itb.misses 0 # DTB misses system.cpu.iq.fp_inst_queue_reads 114 # Number of floating instruction queue reads
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses
system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.iq.int_alu_accesses 1999424161 # Number of integer alu accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.iew.lsq.thread0.forwLoads 34829517 # Number of loads that had data forwarded from stores
system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.itb.write_hits 0 # DTB write hits system.cpu.iew.lsq.thread0.squashedLoads 112622888 # Number of loads squashed
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.iew.lsq.thread0.ignoredResponses 463072 # Number of memory responses ignored because the instruction is squashed
system.cpu.l2cache.ReadExReq_accesses 1892225 # number of ReadExReq accesses(hits+misses) system.cpu.iew.lsq.thread0.memOrderViolation 1914554 # Number of memory ordering violations
system.cpu.l2cache.ReadExReq_avg_miss_latency 34668.138336 # average ReadExReq miss latency system.cpu.iew.lsq.thread0.squashedStores 37688221 # Number of stores squashed
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31525.497909 # average ReadExReq mshr miss latency system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.l2cache.ReadExReq_hits 980562 # number of ReadExReq hits system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.l2cache.ReadExReq_miss_latency 31605659000 # number of ReadExReq miss cycles system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.l2cache.ReadExReq_miss_rate 0.481794 # miss rate for ReadExReq accesses system.cpu.iew.lsq.thread0.cacheBlocked 273360 # Number of times an access to memory failed due to the cache being blocked
system.cpu.l2cache.ReadExReq_misses 911663 # number of ReadExReq misses system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28740630000 # number of ReadExReq MSHR miss cycles system.cpu.iew.iewSquashCycles 60420459 # Number of cycles IEW is squashing
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481794 # mshr miss rate for ReadExReq accesses system.cpu.iew.iewBlockCycles 18632955 # Number of cycles IEW is blocking
system.cpu.l2cache.ReadExReq_mshr_misses 911663 # number of ReadExReq MSHR misses system.cpu.iew.iewUnblockCycles 1195402 # Number of cycles IEW is unblocking
system.cpu.l2cache.ReadReq_accesses 7664805 # number of ReadReq accesses(hits+misses) system.cpu.iew.iewDispatchedInsts 2112469674 # Number of instructions dispatched to IQ
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.590029 # average ReadReq miss latency system.cpu.iew.iewDispSquashedInsts 6157143 # Number of squashed instructions skipped by dispatch
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.423829 # average ReadReq mshr miss latency system.cpu.iew.iewDispLoadInsts 598549667 # Number of dispatched load instructions
system.cpu.l2cache.ReadReq_hits 5643096 # number of ReadReq hits system.cpu.iew.iewDispStoreInsts 212535274 # Number of dispatched store instructions
system.cpu.l2cache.ReadReq_miss_latency 69398376000 # number of ReadReq miss cycles system.cpu.iew.iewDispNonSpecInsts 546 # Number of dispatched non-speculative instructions
system.cpu.l2cache.ReadReq_miss_rate 0.263765 # miss rate for ReadReq accesses system.cpu.iew.iewIQFullEvents 334650 # Number of times the IQ has become full, causing a stall
system.cpu.l2cache.ReadReq_misses 2021709 # number of ReadReq misses system.cpu.iew.iewLSQFullEvents 56652 # Number of times the LSQ has become full, causing a stall
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.iew.memOrderViolationEvents 1914554 # Number of memory order violations
system.cpu.l2cache.ReadReq_mshr_miss_latency 62984867500 # number of ReadReq MSHR miss cycles system.cpu.iew.predictedTakenIncorrect 16889121 # Number of branches that were predicted taken incorrectly
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263764 # mshr miss rate for ReadReq accesses system.cpu.iew.predictedNotTakenIncorrect 3256921 # Number of branches that were predicted not taken incorrectly
system.cpu.l2cache.ReadReq_mshr_misses 2021699 # number of ReadReq MSHR misses system.cpu.iew.branchMispredicts 20146042 # Number of branch mispredicts detected at execute
system.cpu.l2cache.Writeback_accesses 3126399 # number of Writeback accesses(hits+misses) system.cpu.iew.iewExecutedInsts 1946822051 # Number of executed instructions
system.cpu.l2cache.Writeback_hits 3126399 # number of Writeback hits system.cpu.iew.iewExecLoadInsts 556717785 # Number of load instructions executed
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8610.632689 # average number of cycles each access was blocked system.cpu.iew.iewExecSquashedInsts 28220476 # Number of squashed instructions skipped in execute
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.l2cache.avg_refs 2.658362 # Average number of references to valid blocks. system.cpu.iew.exec_nop 283 # number of nop insts executed
system.cpu.l2cache.blocked::no_mshrs 5690 # number of cycles access was blocked system.cpu.iew.exec_refs 742905406 # number of memory reference insts executed
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.iew.exec_branches 235411550 # Number of branches executed
system.cpu.l2cache.blocked_cycles::no_mshrs 48994500 # number of cycles access was blocked system.cpu.iew.exec_stores 186187621 # Number of stores executed
system.cpu.iew.exec_rate 1.719771 # Inst execution rate
system.cpu.iew.wb_sent 1926889510 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1922135210 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1211916900 # num instructions producing a value
system.cpu.iew.wb_consumers 1896005064 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.697964 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.639195 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1723073902 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 389560093 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 464 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18347567 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1060267574 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.625131 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.338631 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 472290035 44.54% 44.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 255203775 24.07% 68.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110318720 10.40% 79.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55061761 5.19% 84.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28404469 2.68% 86.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27943387 2.64% 89.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 20897685 1.97% 91.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 17855453 1.68% 93.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 72292289 6.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1060267574 # Number of insts commited each cycle
system.cpu.commit.count 1723073902 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773831 # Number of memory references committed
system.cpu.commit.loads 485926778 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462372 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 72292289 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3100608681 # The number of ROB reads
system.cpu.rob.rob_writes 4285815110 # The number of ROB writes
system.cpu.timesIdled 696063 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11335809 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1723073884 # Number of Instructions Simulated
system.cpu.committedInsts_total 1723073884 # Number of Instructions Simulated
system.cpu.cpi 0.656979 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.656979 # CPI: Total CPI of All Threads
system.cpu.ipc 1.522118 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.522118 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9738255749 # number of integer regfile reads
system.cpu.int_regfile_writes 1902471542 # number of integer regfile writes
system.cpu.fp_regfile_reads 36 # number of floating regfile reads
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
system.cpu.misc_regfile_reads 2800450937 # number of misc regfile reads
system.cpu.misc_regfile_writes 140 # number of misc regfile writes
system.cpu.icache.replacements 9 # number of replacements
system.cpu.icache.tagsinuse 573.017722 # Cycle average of tags in use
system.cpu.icache.total_refs 265450383 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 717 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 370223.686192 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 573.017722 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.279794 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 265450383 # number of ReadReq hits
system.cpu.icache.demand_hits 265450383 # number of demand (read+write) hits
system.cpu.icache.overall_hits 265450383 # number of overall hits
system.cpu.icache.ReadReq_misses 914 # number of ReadReq misses
system.cpu.icache.demand_misses 914 # number of demand (read+write) misses
system.cpu.icache.overall_misses 914 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32210500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32210500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32210500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 265451297 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 265451297 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 265451297 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35241.247265 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35241.247265 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35241.247265 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 197 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 197 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 197 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 717 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 717 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 717 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 24697500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 24697500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 24697500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34445.606695 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9552367 # number of replacements
system.cpu.dcache.tagsinuse 4082.984998 # Cycle average of tags in use
system.cpu.dcache.total_refs 675087648 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9556463 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.641999 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6495236000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4082.984998 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.996823 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 507131941 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 167955564 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 69 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 675087505 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 675087505 # number of overall hits
system.cpu.dcache.ReadReq_misses 10254687 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 4630483 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 14885170 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 14885170 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 173914872000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 112892331168 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 286807203168 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 286807203168 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 517386628 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 69 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 689972675 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 689972675 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.019820 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.026830 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.021574 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021574 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16959.549521 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 24380.249570 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 19267.983044 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 19267.983044 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 148361910 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 35813 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4142.683104 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3126452 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2590385 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 2738322 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5328707 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5328707 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7664302 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1892161 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9556463 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9556463 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 89320855000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 42428124877 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 131748979877 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 131748979877 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014813 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.013850 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.013850 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11654.140847 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22423.105051 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2920822 # number of replacements
system.cpu.l2cache.tagsinuse 26404.864855 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7838163 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2948145 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.658676 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 129803245500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15746.128543 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10658.736312 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.480534 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.325279 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5643332 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3126452 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 980638 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6623970 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6623970 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2021685 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 911525 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2933210 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2933210 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 69338469500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 31601923000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 100940392500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 100940392500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7665017 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3126452 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1892163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9557180 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9557180 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.263755 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.481737 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.306912 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.306912 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34297.365564 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34669.288281 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34412.944351 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34412.944351 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 48964500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 5689 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 9557030 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34432.739864 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8606.872913 # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.750375 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 6623658 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 101004035000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.306933 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2933372 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 91725497500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.306932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2933362 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.writebacks 1216359 # number of writebacks
system.cpu.l2cache.occ_blocks::0 15787.476515 # Average occupied blocks per context system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.occ_blocks::1 10639.481396 # Average occupied blocks per context system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.occ_percent::0 0.481796 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.324691 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 9557030 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34432.739864 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.750375 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 6623658 # number of overall hits
system.cpu.l2cache.overall_miss_latency 101004035000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.306933 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2933372 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 91725497500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_misses 2021675 # number of ReadReq MSHR misses
system.cpu.l2cache.overall_mshr_miss_rate 0.306932 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_mshr_misses 911525 # number of ReadExReq MSHR misses
system.cpu.l2cache.overall_mshr_misses 2933362 # number of overall MSHR misses system.cpu.l2cache.demand_mshr_misses 2933200 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_misses 2933200 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2921001 # number of replacements system.cpu.l2cache.ReadReq_mshr_miss_latency 62968532000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.sampled_refs 2948324 # Sample count of references to valid blocks. system.cpu.l2cache.ReadExReq_mshr_miss_latency 28735558500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 91704090500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 91704090500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263753 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481737 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.306911 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.306911 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.713493 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31524.706947 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 26426.957911 # Cycle average of tags in use system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.total_refs 7837713 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 129803259500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1216468 # number of writebacks
system.cpu.memDep0.conflictingLoads 87202635 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 84882545 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 598179019 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 212168948 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 2797025769 # number of misc regfile reads
system.cpu.misc_regfile_writes 132 # number of misc regfile writes
system.cpu.numCycles 1135599452 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 43624609 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 1706319975 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 3032404 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 568994598 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 25723615 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 11682 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 10112299112 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 2191283557 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 2168556618 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 426283235 # Number of cycles rename is running
system.cpu.rename.SquashCycles 60139906 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 31553217 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 462236638 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 1010 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 10112298102 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 14041 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 629 # count of serializing insts renamed
system.cpu.rename.skidInsts 61919422 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 626 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3109347935 # The number of ROB reads
system.cpu.rob.rob_writes 4281671298 # The number of ROB writes
system.cpu.timesIdled 552036 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 46 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 14:48:18 M5 started May 16 2011 16:39:45
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -27,4 +27,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 114589481500 because target called exit() 122 123 124 Exiting @ tick 114583980000 because target called exit()

986
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

10
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -5,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 1 2011 16:48:51 M5 compiled May 17 2011 12:22:59
M5 started May 1 2011 16:48:54 M5 started May 17 2011 12:44:44
M5 executing on u200439-lin.austin.arm.com M5 executing on nadc-0309
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
@ -28,4 +30,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 106659390000 because target called exit() 122 123 124 Exiting @ tick 106734154000 because target called exit()

901
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,474 +1,473 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 88999 # Simulator instruction rate (inst/s) sim_seconds 0.106734 # Number of seconds simulated
host_mem_usage 265284 # Number of bytes of host memory used sim_ticks 106734154000 # Number of ticks simulated
host_seconds 2487.25 # Real time elapsed on the host
host_tick_rate 42882469 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 173636 # Simulator instruction rate (inst/s)
host_tick_rate 83720146 # Simulator tick rate (ticks/s)
host_mem_usage 258788 # Number of bytes of host memory used
host_seconds 1274.89 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated sim_insts 221363017 # Number of instructions simulated
sim_seconds 0.106659 # Number of seconds simulated system.cpu.workload.num_syscalls 400 # Number of system calls
sim_ticks 106659390000 # Number of ticks simulated system.cpu.numCycles 213468309 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 25050494 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 25050494 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3072725 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 22404993 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 19578906 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 19559071 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 22388883 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3071862 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 25034838 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 25034838 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 3071894 # The number of times a branch was mispredicted system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.commit.branches 12326943 # Number of branches committed system.cpu.fetch.icacheStallCycles 27480404 # Number of cycles fetch is stalled on an Icache miss
system.cpu.commit.bw_lim_events 2350531 # number cycles where commit BW limit reached system.cpu.fetch.Insts 261552197 # Number of instructions fetch has processed
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.fetch.Branches 25050494 # Number of branches that fetch encountered
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.fetch.predictedBranches 19578906 # Number of branches that fetch has predicted taken
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.fetch.Cycles 69713468 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.commit.commitSquashedInsts 173965235 # The number of squashed insts skipped by commit system.cpu.fetch.SquashCycles 3100277 # Number of cycles fetch has spent squashing
system.cpu.commit.committed_per_cycle::samples 190108496 # Number of insts commited each cycle system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.commit.committed_per_cycle::mean 1.164404 # Number of insts commited each cycle system.cpu.fetch.CacheLines 27480404 # Number of cache lines fetched
system.cpu.commit.committed_per_cycle::stdev 1.519902 # Number of insts commited each cycle system.cpu.fetch.IcacheSquashes 444252 # Number of outstanding Icache misses that were squashed
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.fetch.rateDist::samples 213378820 # Number of instructions fetched each cycle (Total)
system.cpu.commit.committed_per_cycle::0 74006380 38.93% 38.93% # Number of insts commited each cycle system.cpu.fetch.rateDist::mean 2.014955 # Number of instructions fetched each cycle (Total)
system.cpu.commit.committed_per_cycle::1 71095556 37.40% 76.33% # Number of insts commited each cycle system.cpu.fetch.rateDist::stdev 3.225944 # Number of instructions fetched each cycle (Total)
system.cpu.commit.committed_per_cycle::2 18250817 9.60% 85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12666090 6.66% 92.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5885570 3.10% 95.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2802504 1.47% 97.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1948827 1.03% 98.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1102221 0.58% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2350531 1.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 190108496 # Number of insts commited each cycle
system.cpu.commit.count 221363017 # Number of instructions committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.loads 56649590 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 77165306 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 0.963660 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.963660 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 50560876 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33172.166428 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34228.682171 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 50560179 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 23121000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 697 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 310 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 13246500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 387 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26488.657179 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35473.248408 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 187990000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5527 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 55693000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1570 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 36352.334527 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 71076606 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 27086.348473 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency
system.cpu.dcache.demand_hits 71068812 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 211111000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses
system.cpu.dcache.demand_misses 7794 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5837 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 68939500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 1400.398145 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.341894 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 71076606 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 27086.348473 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 71068812 # number of overall hits
system.cpu.dcache.overall_miss_latency 211111000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses
system.cpu.dcache.overall_misses 7794 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5837 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 68939500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 48 # number of replacements
system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1400.398145 # Cycle average of tags in use
system.cpu.dcache.total_refs 71068814 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 10 # number of writebacks
system.cpu.decode.BlockedCycles 57002752 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 419872535 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 66995296 # Number of cycles decode is idle
system.cpu.decode.RunCycles 60323444 # Number of cycles decode is running
system.cpu.decode.SquashCycles 23120513 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 5787004 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 25034838 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 27511716 # Number of cache lines fetched
system.cpu.fetch.Cycles 69512577 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 449654 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 261443886 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 3099669 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.117359 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 27511716 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 19559071 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.225602 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 213229009 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.015146 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.226933 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 145563800 68.27% 68.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 145514774 68.20% 68.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3763912 1.77% 70.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 3945621 1.85% 70.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3143749 1.47% 71.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 3133148 1.47% 71.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4274487 2.00% 73.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 4337653 2.03% 73.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4655568 2.18% 75.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 4594142 2.15% 75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4407393 2.07% 77.76% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 4407004 2.07% 77.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4998818 2.34% 80.11% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 5010346 2.35% 80.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3209647 1.51% 81.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 3238927 1.52% 81.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39211635 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 39197205 18.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 213229009 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 213378820 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3514377 # number of floating regfile reads system.cpu.fetch.branchRate 0.117350 # Number of branch fetches per cycle
system.cpu.fp_regfile_writes 2187528 # number of floating regfile writes system.cpu.fetch.rate 1.225251 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_accesses 27511716 # number of ReadReq accesses(hits+misses) system.cpu.decode.IdleCycles 66958522 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_miss_latency 25569.940006 # average ReadReq miss latency system.cpu.decode.BlockedCycles 57001085 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.790041 # average ReadReq mshr miss latency system.cpu.decode.RunCycles 60412397 # Number of cycles decode is running
system.cpu.icache.ReadReq_hits 27505382 # number of ReadReq hits system.cpu.decode.UnblockCycles 5858231 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_latency 161960000 # number of ReadReq miss cycles system.cpu.decode.SquashCycles 23148585 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses system.cpu.decode.DecodedInsts 419968775 # Number of instructions handled by decode
system.cpu.icache.ReadReq_misses 6334 # number of ReadReq misses system.cpu.rename.SquashCycles 23148585 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_hits 952 # number of ReadReq MSHR hits system.cpu.rename.IdleCycles 74832356 # Number of cycles rename is idle
system.cpu.icache.ReadReq_mshr_miss_latency 120905500 # number of ReadReq MSHR miss cycles system.cpu.rename.BlockCycles 18068346 # Number of cycles rename is blocking
system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses system.cpu.rename.serializeStallCycles 22426 # count of cycles rename stalled for serializing inst
system.cpu.icache.ReadReq_mshr_misses 5382 # number of ReadReq MSHR misses system.cpu.rename.RunCycles 57435303 # Number of cycles rename is running
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.UnblockCycles 39871804 # Number of cycles rename is unblocking
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.RenamedInsts 409779934 # Number of instructions processed by rename
system.cpu.icache.avg_refs 5112.524535 # Average number of references to valid blocks. system.cpu.rename.IQFullEvents 21501033 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 16352489 # Number of times rename has blocked due to LSQ full
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedOperands 430797249 # Number of destination operands rename has renamed
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.RenameLookups 1054244251 # Number of register rename lookups that rename has made
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.int_rename_lookups 1043122686 # Number of integer rename lookups
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.fp_rename_lookups 11121565 # Number of floating rename lookups
system.cpu.icache.demand_accesses 27511716 # number of demand (read+write) accesses system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.icache.demand_avg_miss_latency 25569.940006 # average overall miss latency system.cpu.rename.UndoneMaps 196433840 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
system.cpu.icache.demand_hits 27505382 # number of demand (read+write) hits system.cpu.rename.tempSerializingInsts 1310 # count of temporary serializing insts renamed
system.cpu.icache.demand_miss_latency 161960000 # number of demand (read+write) miss cycles system.cpu.rename.skidInsts 83098345 # count of insts added to the skid buffer
system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses system.cpu.memDep0.insertedLoads 104980766 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_misses 6334 # number of demand (read+write) misses system.cpu.memDep0.insertedStores 37095594 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_hits 952 # number of demand (read+write) MSHR hits system.cpu.memDep0.conflictingLoads 90430171 # Number of conflicting loads.
system.cpu.icache.demand_mshr_miss_latency 120905500 # number of demand (read+write) MSHR miss cycles system.cpu.memDep0.conflictingStores 30425406 # Number of conflicting stores.
system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses system.cpu.iq.iqInstsAdded 395507958 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.demand_mshr_misses 5382 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 1605.599338 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.783984 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 27511716 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25569.940006 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 27505382 # number of overall hits
system.cpu.icache.overall_miss_latency 161960000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses
system.cpu.icache.overall_misses 6334 # number of overall misses
system.cpu.icache.overall_mshr_hits 952 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120905500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 5382 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 3421 # number of replacements
system.cpu.icache.sampled_refs 5380 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1605.599338 # Cycle average of tags in use
system.cpu.icache.total_refs 27505382 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 89772 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 3285583 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 15876599 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 1.304758 # Inst execution rate
system.cpu.iew.exec_refs 90277406 # number of memory reference insts executed
system.cpu.iew.exec_stores 23169669 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 535171 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 104943598 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 227523 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 37082263 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 395310289 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 67107737 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3518032 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 278329468 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 451527 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 13065 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 23120513 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 520097 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 16336525 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 15761 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 34193 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 46033 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 48294008 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 16566547 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 34193 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 745041 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2540542 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 371832293 # num instructions consuming a value
system.cpu.iew.wb_count 275994943 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.599268 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 222827233 # num instructions producing a value
system.cpu.iew.wb_rate 1.293815 # insts written-back per cycle
system.cpu.iew.wb_sent 277038754 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 516581259 # number of integer regfile reads
system.cpu.int_regfile_writes 284038520 # number of integer regfile writes
system.cpu.ipc 1.037710 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.037710 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 1197054 0.42% 0.42% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187021337 66.36% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1590291 0.56% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 68531630 24.32% 91.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23507188 8.34% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 281847500 # Type of FU issued
system.cpu.iq.fp_alu_accesses 2638444 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 5236518 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2534154 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 5693561 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 2791850 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009906 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 67290 2.41% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2359047 84.50% 86.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 365513 13.09% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 280803852 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 774570053 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 273460789 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 563268520 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 395308865 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 281847500 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 173620640 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqInstsIssued 281831488 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 90712 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 66022 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 173816816 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 357685429 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 357064626 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 213378820 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 213229009 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.320803 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.321807 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.372846 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.374231 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 72462076 33.98% 33.98% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 72508340 33.98% 33.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 65441995 30.69% 64.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 65572290 30.73% 64.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 36667606 17.20% 81.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 36644917 17.17% 81.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20567003 9.65% 91.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20570479 9.64% 91.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 11965683 5.61% 97.13% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 12013956 5.63% 97.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3990809 1.87% 99.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 3959522 1.86% 99.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1502036 0.70% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1478424 0.69% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 514117 0.24% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 513187 0.24% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 117684 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 117705 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 213229009 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 213378820 # Number of insts issued each cycle
system.cpu.iq.rate 1.321250 # Inst issue rate system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses) system.cpu.iq.fu_full::IntAlu 68507 2.43% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.695262 # average ReadExReq miss latency system.cpu.iq.fu_full::IntMult 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.472471 # average ReadExReq mshr miss latency system.cpu.iq.fu_full::IntDiv 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_miss_latency 53963500 # number of ReadExReq miss cycles system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses system.cpu.iq.fu_full::FloatMult 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48971000 # number of ReadExReq MSHR miss cycles system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_accesses 5767 # number of ReadReq accesses(hits+misses) system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.551611 # average ReadReq miss latency system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.326597 # average ReadReq mshr miss latency system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_hits 2105 # number of ReadReq hits system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_miss_latency 125572000 # number of ReadReq miss cycles system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_miss_rate 0.634992 # miss rate for ReadReq accesses system.cpu.iq.fu_full::SimdMult 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_mshr_miss_latency 113677000 # number of ReadReq MSHR miss cycles system.cpu.iq.fu_full::SimdShift 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634992 # mshr miss rate for ReadReq accesses system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2380396 84.55% 86.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 366520 13.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1200241 0.43% 0.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187039498 66.37% 66.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1589434 0.56% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 68498295 24.30% 91.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23504020 8.34% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 281831488 # Type of FU issued
system.cpu.iq.rate 1.320250 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2815423 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009990 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 774688380 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 563666165 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 273461056 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5234861 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 5690969 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2532279 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 280809032 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2637638 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 16340043 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 48331176 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 20419 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34133 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 16579878 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 45973 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 23148585 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 533368 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 548562 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 395509382 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 255580 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 104980766 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37095594 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 479390 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13059 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 34133 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2541200 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 744980 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3286180 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 278314164 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 67081099 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3517324 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 90254153 # number of memory reference insts executed
system.cpu.iew.exec_branches 15873858 # Number of branches executed
system.cpu.iew.exec_stores 23173054 # Number of stores executed
system.cpu.iew.exec_rate 1.303773 # Inst execution rate
system.cpu.iew.wb_sent 277023863 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 275993335 # cumulative count of insts written-back
system.cpu.iew.wb_producers 222941305 # num instructions producing a value
system.cpu.iew.wb_consumers 371922764 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.292901 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.599429 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 174164321 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3072754 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 190230235 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.163658 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.518986 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 74059520 38.93% 38.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 71187215 37.42% 76.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 18215863 9.58% 85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12685132 6.67% 92.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5921003 3.11% 95.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2781558 1.46% 97.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1922219 1.01% 98.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1098236 0.58% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2359489 1.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 190230235 # Number of insts commited each cycle
system.cpu.commit.count 221363017 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165306 # Number of memory references committed
system.cpu.commit.loads 56649590 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 12326943 # Number of branches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 2359489 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 583398084 # The number of ROB reads
system.cpu.rob.rob_writes 814214437 # The number of ROB writes
system.cpu.timesIdled 1914 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 89489 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 0.964336 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.964336 # CPI: Total CPI of All Threads
system.cpu.ipc 1.036983 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.036983 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 516528082 # number of integer regfile reads
system.cpu.int_regfile_writes 284024941 # number of integer regfile writes
system.cpu.fp_regfile_reads 3512884 # number of floating regfile reads
system.cpu.fp_regfile_writes 2186553 # number of floating regfile writes
system.cpu.misc_regfile_reads 145160346 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 3419 # number of replacements
system.cpu.icache.tagsinuse 1603.937064 # Cycle average of tags in use
system.cpu.icache.total_refs 27474068 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 5377 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5109.553282 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1603.937064 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.783172 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 27474068 # number of ReadReq hits
system.cpu.icache.demand_hits 27474068 # number of demand (read+write) hits
system.cpu.icache.overall_hits 27474068 # number of overall hits
system.cpu.icache.ReadReq_misses 6336 # number of ReadReq misses
system.cpu.icache.demand_misses 6336 # number of demand (read+write) misses
system.cpu.icache.overall_misses 6336 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 161881500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 161881500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 161881500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 27480404 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 27480404 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 27480404 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000231 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000231 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000231 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 25549.479167 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 25549.479167 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 25549.479167 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 957 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 957 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 957 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 5379 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 5379 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 5379 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 120710000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 120710000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 120710000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22440.974159 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 48 # number of replacements
system.cpu.dcache.tagsinuse 1400.553684 # Cycle average of tags in use
system.cpu.dcache.total_refs 71038551 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36336.854731 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1400.553684 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.341932 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 50529918 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 20508631 # number of WriteReq hits
system.cpu.dcache.demand_hits 71038549 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 71038549 # number of overall hits
system.cpu.dcache.ReadReq_misses 700 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 7099 # number of WriteReq misses
system.cpu.dcache.demand_misses 7799 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 7799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 23034500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 187834000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 210868500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 210868500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 50530618 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 71046348 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 71046348 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32906.428571 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 26459.219608 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 27037.889473 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 27037.889473 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 10 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 312 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 5530 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5842 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5842 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 13276000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 55641500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 68917500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 68917500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34216.494845 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35463.033779 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2429.026594 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2107 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3661 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.575526 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2428.011682 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014912 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.074097 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2107 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.demand_hits 2113 # number of demand (read+write) hits
system.cpu.l2cache.avg_refs 0.574195 # Average number of references to valid blocks. system.cpu.l2cache.overall_hits 2113 # number of overall hits
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.ReadReq_misses 3657 # number of ReadReq misses
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5219 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5219 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 125400000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 53945500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 179345500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 179345500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 5764 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 7332 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 7332 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.634455 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.711811 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.711811 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.401969 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.171575 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34363.958613 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34363.958613 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34367.438744 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 2111 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 179535500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.712202 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5224 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 162648000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.712202 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5224 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 2429.722700 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014710 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.074149 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34367.438744 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2111 # number of overall hits
system.cpu.l2cache.overall_miss_latency 179535500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.712202 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5224 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 162648000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.712202 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5224 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2430.737411 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2105 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 90595235 # Number of conflicting loads. system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.memDep0.conflictingStores 30370608 # Number of conflicting stores. system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.memDep0.insertedLoads 104943598 # Number of loads inserted to the mem dependence unit. system.cpu.l2cache.ReadReq_mshr_misses 3657 # number of ReadReq MSHR misses
system.cpu.memDep0.insertedStores 37082263 # Number of stores inserted to the mem dependence unit. system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses
system.cpu.misc_regfile_reads 145181965 # number of misc regfile reads system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses
system.cpu.misc_regfile_writes 844 # number of misc regfile writes system.cpu.l2cache.demand_mshr_misses 5219 # number of demand (read+write) MSHR misses
system.cpu.numCycles 213318781 # number of cpu cycles simulated system.cpu.l2cache.overall_mshr_misses 5219 # number of overall MSHR misses
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.l2cache.ReadReq_mshr_miss_latency 113519000 # number of ReadReq MSHR miss cycles
system.cpu.rename.BlockCycles 18031749 # Number of cycles rename is blocking system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed system.cpu.l2cache.ReadExReq_mshr_miss_latency 48964500 # number of ReadExReq MSHR miss cycles
system.cpu.rename.IQFullEvents 21548402 # Number of times rename has blocked due to IQ full system.cpu.l2cache.demand_mshr_miss_latency 162483500 # number of demand (read+write) MSHR miss cycles
system.cpu.rename.IdleCycles 74813235 # Number of cycles rename is idle system.cpu.l2cache.overall_mshr_miss_latency 162483500 # number of overall MSHR miss cycles
system.cpu.rename.LSQFullEvents 16345466 # Number of times rename has blocked due to LSQ full system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634455 # mshr miss rate for ReadReq accesses
system.cpu.rename.RenameLookups 1053910938 # Number of register rename lookups that rename has made system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.rename.RenamedInsts 409668647 # Number of instructions processed by rename system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses
system.cpu.rename.RenamedOperands 430592677 # Number of destination operands rename has renamed system.cpu.l2cache.demand_mshr_miss_rate 0.711811 # mshr miss rate for demand accesses
system.cpu.rename.RunCycles 57355298 # Number of cycles rename is running system.cpu.l2cache.overall_mshr_miss_rate 0.711811 # mshr miss rate for overall accesses
system.cpu.rename.SquashCycles 23120513 # Number of cycles rename is squashing system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.564124 # average ReadReq mshr miss latency
system.cpu.rename.UnblockCycles 39885814 # Number of cycles rename is unblocking system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.rename.UndoneMaps 196229268 # Number of HB maps that are undone due to squashing system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.311140 # average ReadExReq mshr miss latency
system.cpu.rename.fp_rename_lookups 11151271 # Number of floating rename lookups system.cpu.l2cache.demand_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency
system.cpu.rename.int_rename_lookups 1042759667 # Number of integer rename lookups system.cpu.l2cache.overall_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency
system.cpu.rename.serializeStallCycles 22400 # count of cycles rename stalled for serializing inst system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.rename.skidInsts 83004304 # count of insts added to the skid buffer system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.rename.tempSerializingInsts 1309 # count of temporary serializing insts renamed system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.rob.rob_reads 583086217 # The number of ROB reads
system.cpu.rob.rob_writes 813789002 # The number of ROB writes
system.cpu.timesIdled 1930 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
View file

@ -7,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 4 2011 13:56:47 M5 compiled May 16 2011 15:11:25
M5 started May 4 2011 14:21:49 M5 started May 16 2011 15:11:56
M5 executing on nadc-0364 M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Hello world! Hello world!
Exiting @ tick 10782500 because target called exit() Exiting @ tick 10758500 because target called exit()

970
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,514 +1,514 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 97592 # Simulator instruction rate (inst/s)
host_mem_usage 257968 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 182664453 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5739 # Number of instructions simulated
sim_seconds 0.000011 # Number of seconds simulated sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 10782500 # Number of ticks simulated sim_ticks 10758500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. sim_freq 1000000000000 # Frequency of simulated ticks
system.cpu.BPredUnit.BTBHits 725 # Number of BTB hits host_inst_rate 88454 # Simulator instruction rate (inst/s)
system.cpu.BPredUnit.BTBLookups 1851 # Number of BTB lookups host_tick_rate 165780634 # Simulator tick rate (ticks/s)
system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions. host_mem_usage 251164 # Number of bytes of host memory used
system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect host_seconds 0.07 # Real time elapsed on the host
system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted sim_insts 5739 # Number of instructions simulated
system.cpu.BPredUnit.lookups 2185 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 238 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
system.cpu.commit.branches 945 # Number of branches committed
system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 4364 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 10921 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.525501 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.286416 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8444 77.32% 77.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1188 10.88% 88.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 479 4.39% 92.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 318 2.91% 95.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 171 1.57% 97.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 152 1.39% 98.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 62 0.57% 99.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 33 0.30% 99.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 10921 # Number of insts commited each cycle
system.cpu.commit.count 5739 # Number of instructions committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
system.cpu.commit.loads 1201 # Number of loads committed
system.cpu.commit.membars 12 # Number of memory barriers committed
system.cpu.commit.refs 2139 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 5739 # Number of Instructions Simulated
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
system.cpu.cpi 3.757798 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.757798 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 1795 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 32493.670886 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29240.566038 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5134000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.088022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 158 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059053 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 106 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 35800.687285 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35880.952381 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 10418000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1507000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 15.398649 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2708 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 34636.971047 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31125 # average overall mshr miss latency
system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 15552000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.165805 # miss rate for demand accesses
system.cpu.dcache.demand_misses 449 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4606500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.054653 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 89.451060 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.021839 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 2708 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34636.971047 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31125 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 2259 # number of overall hits
system.cpu.dcache.overall_miss_latency 15552000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.165805 # miss rate for overall accesses
system.cpu.dcache.overall_misses 449 # number of overall misses
system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4606500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.054653 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 89.451060 # Cycle average of tags in use
system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.BlockedCycles 1179 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 352 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 12101 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 7437 # Number of cycles decode is idle
system.cpu.decode.RunCycles 2257 # Number of cycles decode is running
system.cpu.decode.SquashCycles 777 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 565 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 2185 # Number of branches that fetch encountered system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.fetch.CacheLines 1628 # Number of cache lines fetched system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.fetch.Cycles 2410 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.fetch.IcacheSquashes 234 # Number of outstanding Icache misses that were squashed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.fetch.Insts 11189 # Number of instructions fetch has processed system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 21518 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2191 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1669 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 732 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 1618 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 11168 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2191 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 974 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2422 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.101317 # Number of branch fetches per cycle system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.icacheStallCycles 1628 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.CacheLines 1618 # Number of cache lines fetched
system.cpu.fetch.predictedBranches 963 # Number of branches that fetch has predicted taken system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rate 0.518826 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 11665 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 11697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.190999 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.186202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.598414 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.597096 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9287 79.40% 79.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 9243 79.24% 79.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 223 1.91% 81.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 226 1.94% 81.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 149 1.27% 82.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 153 1.31% 82.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 211 1.80% 84.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 215 1.84% 84.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 194 1.66% 86.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 195 1.67% 86.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 259 2.21% 88.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 261 2.24% 88.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 122 1.04% 89.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 124 1.06% 89.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 98 0.84% 90.13% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 97 0.83% 90.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1154 9.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1151 9.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 11697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 11665 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fetch.branchRate 0.101822 # Number of branch fetches per cycle
system.cpu.icache.ReadReq_accesses 1628 # number of ReadReq accesses(hits+misses) system.cpu.fetch.rate 0.519007 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_avg_miss_latency 35051.051051 # average ReadReq miss latency system.cpu.decode.IdleCycles 7384 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33594.076655 # average ReadReq mshr miss latency system.cpu.decode.BlockedCycles 1181 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_hits 1295 # number of ReadReq hits system.cpu.decode.RunCycles 2267 # Number of cycles decode is running
system.cpu.icache.ReadReq_miss_latency 11672000 # number of ReadReq miss cycles system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_rate 0.204545 # miss rate for ReadReq accesses system.cpu.decode.SquashCycles 786 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_misses 333 # number of ReadReq misses system.cpu.decode.BranchResolved 350 # Number of times decode resolved a branch
system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction
system.cpu.icache.ReadReq_mshr_miss_latency 9641500 # number of ReadReq MSHR miss cycles system.cpu.decode.DecodedInsts 12143 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_miss_rate 0.176290 # mshr miss rate for ReadReq accesses system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode
system.cpu.icache.ReadReq_mshr_misses 287 # number of ReadReq MSHR misses system.cpu.rename.SquashCycles 786 # Number of cycles rename is squashing
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.IdleCycles 7644 # Number of cycles rename is idle
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking
system.cpu.icache.avg_refs 4.512195 # Average number of references to valid blocks. system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.RunCycles 2054 # Number of cycles rename is running
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.UnblockCycles 189 # Number of cycles rename is unblocking
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.RenamedInsts 11385 # Number of instructions processed by rename
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
system.cpu.icache.demand_accesses 1628 # number of demand (read+write) accesses system.cpu.rename.RenamedOperands 11181 # Number of destination operands rename has renamed
system.cpu.icache.demand_avg_miss_latency 35051.051051 # average overall miss latency system.cpu.rename.RenameLookups 51901 # Number of register rename lookups that rename has made
system.cpu.icache.demand_avg_mshr_miss_latency 33594.076655 # average overall mshr miss latency system.cpu.rename.int_rename_lookups 51381 # Number of integer rename lookups
system.cpu.icache.demand_hits 1295 # number of demand (read+write) hits system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups
system.cpu.icache.demand_miss_latency 11672000 # number of demand (read+write) miss cycles system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
system.cpu.icache.demand_miss_rate 0.204545 # miss rate for demand accesses system.cpu.rename.UndoneMaps 5492 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_misses 333 # number of demand (read+write) misses system.cpu.rename.serializingInsts 15 # count of serializing insts renamed
system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed
system.cpu.icache.demand_mshr_miss_latency 9641500 # number of demand (read+write) MSHR miss cycles system.cpu.rename.skidInsts 493 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_miss_rate 0.176290 # mshr miss rate for demand accesses system.cpu.memDep0.insertedLoads 2353 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_misses 287 # number of demand (read+write) MSHR misses system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqInstsAdded 10217 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.occ_blocks::0 147.191898 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.071871 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 1628 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35051.051051 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 33594.076655 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1295 # number of overall hits
system.cpu.icache.overall_miss_latency 11672000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.204545 # miss rate for overall accesses
system.cpu.icache.overall_misses 333 # number of overall misses
system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 9641500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.176290 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 287 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.sampled_refs 287 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 147.191898 # Cycle average of tags in use
system.cpu.icache.total_refs 1295 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 9869 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 1360 # Number of branches executed
system.cpu.iew.exec_nop 3 # number of nop insts executed
system.cpu.iew.exec_rate 0.377446 # Inst execution rate
system.cpu.iew.exec_refs 3052 # number of memory reference insts executed
system.cpu.iew.exec_stores 1120 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 2335 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 10208 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 8140 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 777 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 1134 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 6995 # num instructions consuming a value
system.cpu.iew.wb_count 7761 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.509078 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 3561 # num instructions producing a value
system.cpu.iew.wb_rate 0.359872 # insts written-back per cycle
system.cpu.iew.wb_sent 7887 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 37201 # number of integer regfile reads
system.cpu.int_regfile_writes 7643 # number of integer regfile writes
system.cpu.ipc 0.266113 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.266113 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5232 61.80% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2072 24.47% 86.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1153 13.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8466 # Type of FU issued
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 182 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.021498 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 11 6.04% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 115 63.19% 69.23% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 56 30.77% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 8628 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 28796 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 7745 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 14142 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 10181 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8466 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3941 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqInstsIssued 8487 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
system.cpu.iq.iqSquashedOperandsExamined 10938 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedInstsExamined 3978 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.issued_per_cycle::samples 11697 # Number of insts issued each cycle system.cpu.iq.iqSquashedOperandsExamined 11076 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::mean 0.723775 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 11665 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.386140 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.727561 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.389080 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8148 69.66% 69.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 8112 69.54% 69.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1408 12.04% 81.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1403 12.03% 81.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 816 6.98% 88.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 820 7.03% 88.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 516 4.41% 93.08% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 520 4.46% 93.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 394 3.37% 96.45% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 393 3.37% 96.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 234 2.00% 98.45% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 236 2.02% 98.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 143 1.22% 99.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 143 1.23% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 11697 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 11665 # Number of insts issued each cycle
system.cpu.iq.rate 0.392562 # Inst issue rate system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.itb.accesses 0 # DTB accesses system.cpu.iq.fu_full::IntAlu 11 6.01% 6.01% # attempts to use FU when none available
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.hits 0 # DTB hits system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.misses 0 # DTB misses system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.write_hits 0 # DTB write hits system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.itb.write_misses 0 # DTB write misses system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_avg_miss_latency 34440.476190 # average ReadExReq miss latency system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_miss_latency 1446500 # number of ReadExReq miss cycles system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 116 63.39% 69.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 56 30.60% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5246 61.81% 61.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2078 24.48% 86.40% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1154 13.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8487 # Type of FU issued
system.cpu.iq.rate 0.394414 # Inst issue rate
system.cpu.iq.fu_busy_cnt 183 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.021562 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 28807 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14215 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7753 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 8650 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 786 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10244 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 136 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2353 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8154 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 3 # number of nop insts executed
system.cpu.iew.exec_refs 3053 # number of memory reference insts executed
system.cpu.iew.exec_branches 1361 # Number of branches executed
system.cpu.iew.exec_stores 1121 # Number of stores executed
system.cpu.iew.exec_rate 0.378939 # Inst execution rate
system.cpu.iew.wb_sent 7896 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7769 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3570 # num instructions producing a value
system.cpu.iew.wb_consumers 7022 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.361047 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.508402 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4400 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 334 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 10880 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.527482 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.289859 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8406 77.26% 77.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1187 10.91% 88.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 477 4.38% 92.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 317 2.91% 95.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 170 1.56% 97.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 153 1.41% 98.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 62 0.57% 99.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 34 0.31% 99.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 10880 # Number of insts commited each cycle
system.cpu.commit.count 5739 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2139 # Number of memory references committed
system.cpu.commit.loads 1201 # Number of loads committed
system.cpu.commit.membars 12 # Number of memory barriers committed
system.cpu.commit.branches 945 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 20788 # The number of ROB reads
system.cpu.rob.rob_writes 21080 # The number of ROB writes
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 9853 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5739 # Number of Instructions Simulated
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
system.cpu.cpi 3.749434 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.749434 # CPI: Total CPI of All Threads
system.cpu.ipc 0.266707 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.266707 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 37248 # number of integer regfile reads
system.cpu.int_regfile_writes 7653 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 13970 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 146.709916 # Cycle average of tags in use
system.cpu.icache.total_refs 1288 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 285 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.519298 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 146.709916 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.071636 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits
system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits
system.cpu.icache.overall_hits 1288 # number of overall hits
system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses
system.cpu.icache.demand_misses 330 # number of demand (read+write) misses
system.cpu.icache.overall_misses 330 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 11562500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 11562500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 11562500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 1618 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 1618 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 1618 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.203956 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.203956 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.203956 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35037.878788 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35037.878788 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35037.878788 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 9568500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 9568500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 9568500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.176143 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.176143 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.176143 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33573.684211 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 89.574063 # Cycle average of tags in use
system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 15.295302 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 89.574063 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.021869 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 2259 # number of overall hits
system.cpu.dcache.ReadReq_misses 159 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 450 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 450 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 10420500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 15553000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 15553000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 1796 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 2709 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 2709 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.088530 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.166113 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.166113 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32279.874214 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35809.278351 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 34562.222222 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 34562.222222 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 107 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 149 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1507500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4607000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4607000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059577 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.055002 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.055002 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28967.289720 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35892.857143 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 185.420659 # Cycle average of tags in use
system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 347 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.112392 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 185.420659 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.005659 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits
system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 39 # number of overall hits
system.cpu.l2cache.ReadReq_misses 353 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_misses 395 # number of demand (read+write) misses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.overall_misses 395 # number of overall misses
system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_miss_latency 12138500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_accesses 393 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_miss_latency 1447000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_avg_miss_latency 34391.549296 # average ReadReq miss latency system.cpu.l2cache.demand_miss_latency 13585500 # number of demand (read+write) miss cycles
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31237.822350 # average ReadReq mshr miss latency system.cpu.l2cache.overall_miss_latency 13585500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_hits 38 # number of ReadReq hits system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_miss_latency 12209000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_miss_rate 0.903308 # miss rate for ReadReq accesses system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses
system.cpu.l2cache.ReadReq_misses 355 # number of ReadReq misses system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_miss_rate 0.900510 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10902000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.888041 # mshr miss rate for ReadReq accesses system.cpu.l2cache.demand_miss_rate 0.910138 # miss rate for demand accesses
system.cpu.l2cache.ReadReq_mshr_misses 349 # number of ReadReq MSHR misses system.cpu.l2cache.overall_miss_rate 0.910138 # miss rate for overall accesses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.ReadReq_avg_miss_latency 34386.685552 # average ReadReq miss latency
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_avg_miss_latency 34452.380952 # average ReadExReq miss latency
system.cpu.l2cache.avg_refs 0.108883 # Average number of references to valid blocks. system.cpu.l2cache.demand_avg_miss_latency 34393.670886 # average overall miss latency
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.overall_avg_miss_latency 34393.670886 # average overall miss latency
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34396.725441 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.524297 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 38 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13655500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.912644 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 397 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12217000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.898851 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 185.920349 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.005674 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34396.725441 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.524297 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 38 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13655500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.912644 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 397 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12217000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.898851 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 349 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 185.920349 # Cycle average of tags in use
system.cpu.l2cache.total_refs 38 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
system.cpu.memDep0.insertedLoads 2335 # Number of loads inserted to the mem dependence unit. system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit. system.cpu.l2cache.ReadReq_mshr_misses 347 # number of ReadReq MSHR misses
system.cpu.misc_regfile_reads 13994 # number of misc regfile reads system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses
system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses
system.cpu.numCycles 21566 # number of cpu cycles simulated system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.l2cache.ReadReq_mshr_miss_latency 10837500 # number of ReadReq MSHR miss cycles
system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed system.cpu.l2cache.demand_mshr_miss_latency 12152500 # number of demand (read+write) MSHR miss cycles
system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full system.cpu.l2cache.overall_mshr_miss_latency 12152500 # number of overall MSHR miss cycles
system.cpu.rename.IdleCycles 7695 # Number of cycles rename is idle system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.rename.LSQFullEvents 122 # Number of times rename has blocked due to LSQ full system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885204 # mshr miss rate for ReadReq accesses
system.cpu.rename.RenameLookups 51738 # Number of register rename lookups that rename has made system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.rename.RenamedInsts 11352 # Number of instructions processed by rename system.cpu.l2cache.demand_mshr_miss_rate 0.896313 # mshr miss rate for demand accesses
system.cpu.rename.RenamedOperands 11162 # Number of destination operands rename has renamed system.cpu.l2cache.overall_mshr_miss_rate 0.896313 # mshr miss rate for overall accesses
system.cpu.rename.RunCycles 2047 # Number of cycles rename is running system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31231.988473 # average ReadReq mshr miss latency
system.cpu.rename.SquashCycles 777 # Number of cycles rename is squashing system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency
system.cpu.rename.UnblockCycles 186 # Number of cycles rename is unblocking system.cpu.l2cache.demand_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency
system.cpu.rename.UndoneMaps 5473 # Number of HB maps that are undone due to squashing system.cpu.l2cache.overall_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency
system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.rename.int_rename_lookups 51218 # Number of integer rename lookups system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.rename.serializingInsts 15 # count of serializing insts renamed system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.rename.skidInsts 482 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 20793 # The number of ROB reads
system.cpu.rob.rob_writes 20998 # The number of ROB writes
system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

10
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simout
Redirecting stderr to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simerr
M5 Simulator System M5 Simulator System
Copyright (c) 2001-2008 Copyright (c) 2001-2008
@ -5,12 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Apr 21 2011 13:30:37 M5 compiled May 17 2011 12:22:59
M5 started Apr 21 2011 14:05:23 M5 started May 17 2011 13:06:27
M5 executing on maize M5 executing on nadc-0309
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Hello world! Hello world!
Exiting @ tick 11371000 because target called exit() Exiting @ tick 11369000 because target called exit()

814
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,303 +1,106 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 99680 # Simulator instruction rate (inst/s)
host_mem_usage 212240 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 115331857 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9809 # Number of instructions simulated
sim_seconds 0.000011 # Number of seconds simulated sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11371000 # Number of ticks simulated sim_ticks 11369000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. sim_freq 1000000000000 # Frequency of simulated ticks
system.cpu.BPredUnit.BTBHits 931 # Number of BTB hits host_inst_rate 133340 # Simulator instruction rate (inst/s)
system.cpu.BPredUnit.BTBLookups 2531 # Number of BTB lookups host_tick_rate 154514196 # Simulator tick rate (ticks/s)
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. host_mem_usage 245132 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 9809 # Number of instructions simulated
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 22739 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2757 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 2757 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 2758 # Number of conditional branches predicted system.cpu.BPredUnit.BTBLookups 2530 # Number of BTB lookups
system.cpu.BPredUnit.lookups 2758 # Number of BP lookups system.cpu.BPredUnit.BTBHits 929 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.commit.branches 1214 # Number of branches committed system.cpu.fetch.icacheStallCycles 1700 # Number of cycles fetch is stalled on an Icache miss
system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached system.cpu.fetch.Insts 12836 # Number of instructions fetch has processed
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.fetch.Branches 2757 # Number of branches that fetch encountered
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards system.cpu.fetch.Cycles 3597 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.commit.commitSquashedInsts 9222 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 11809 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.830638 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.597584 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8189 69.35% 69.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1225 10.37% 79.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 582 4.93% 84.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11809 # Number of insts commited each cycle
system.cpu.commit.count 9809 # Number of instructions committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 9714 # Number of committed integer instructions.
system.cpu.commit.loads 1056 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 1990 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 9809 # Number of Instructions Simulated
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
system.cpu.cpi 2.318585 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.318585 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency
system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses
system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 85.873455 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.020965 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 2039 # number of overall hits
system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses
system.cpu.dcache.overall_misses 426 # number of overall misses
system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 85.873455 # Cycle average of tags in use
system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.BlockedCycles 1369 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 22088 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 7085 # Number of cycles decode is idle
system.cpu.decode.RunCycles 3278 # Number of cycles decode is running
system.cpu.decode.SquashCycles 1477 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 2758 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1703 # Number of cache lines fetched
system.cpu.fetch.Cycles 3590 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 238 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12847 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.121268 # Number of branch fetches per cycle system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.icacheStallCycles 1703 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.CacheLines 1700 # Number of cache lines fetched
system.cpu.fetch.predictedBranches 931 # Number of branches that fetch has predicted taken system.cpu.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rate 0.564877 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 13282 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 13286 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.734377 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.734834 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.109101 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.110520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9786 73.66% 73.66% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 9775 73.60% 73.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 161 1.21% 74.87% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 168 1.26% 74.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 122 0.92% 75.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 126 0.95% 75.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.71% 77.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 226 1.70% 77.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 192 1.45% 78.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 192 1.45% 78.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 168 1.26% 80.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 168 1.26% 80.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 257 1.93% 82.14% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 259 1.95% 82.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 171 1.29% 83.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 168 1.26% 83.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2202 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 2200 16.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13286 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 13282 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.fetch.branchRate 0.121245 # Number of branch fetches per cycle
system.cpu.icache.ReadReq_accesses 1703 # number of ReadReq accesses(hits+misses) system.cpu.fetch.rate 0.564493 # Number of inst fetches per cycle
system.cpu.icache.ReadReq_avg_miss_latency 36577.562327 # average ReadReq miss latency system.cpu.decode.IdleCycles 7076 # Number of cycles decode is idle
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100 # average ReadReq mshr miss latency system.cpu.decode.BlockedCycles 1369 # Number of cycles decode is blocked
system.cpu.icache.ReadReq_hits 1342 # number of ReadReq hits system.cpu.decode.RunCycles 3285 # Number of cycles decode is running
system.cpu.icache.ReadReq_miss_latency 13204500 # number of ReadReq miss cycles system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking
system.cpu.icache.ReadReq_miss_rate 0.211979 # miss rate for ReadReq accesses system.cpu.decode.SquashCycles 1475 # Number of cycles decode is squashing
system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses system.cpu.decode.DecodedInsts 22079 # Number of instructions handled by decode
system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits system.cpu.rename.SquashCycles 1475 # Number of cycles rename is squashing
system.cpu.icache.ReadReq_mshr_miss_latency 10354500 # number of ReadReq MSHR miss cycles system.cpu.rename.IdleCycles 7317 # Number of cycles rename is idle
system.cpu.icache.ReadReq_mshr_miss_rate 0.173224 # mshr miss rate for ReadReq accesses system.cpu.rename.BlockCycles 565 # Number of cycles rename is blocking
system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses system.cpu.rename.serializeStallCycles 440 # count of cycles rename stalled for serializing inst
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.rename.RunCycles 3105 # Number of cycles rename is running
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.rename.UnblockCycles 380 # Number of cycles rename is unblocking
system.cpu.icache.avg_refs 4.549153 # Average number of references to valid blocks. system.cpu.rename.RenamedInsts 21002 # Number of instructions processed by rename
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.rename.LSQFullEvents 248 # Number of times rename has blocked due to LSQ full
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.rename.RenamedOperands 19737 # Number of destination operands rename has renamed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.rename.RenameLookups 44285 # Number of register rename lookups that rename has made
system.cpu.icache.demand_accesses 1703 # number of demand (read+write) accesses system.cpu.rename.int_rename_lookups 44269 # Number of integer rename lookups
system.cpu.icache.demand_avg_miss_latency 36577.562327 # average overall miss latency system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.icache.demand_avg_mshr_miss_latency 35100 # average overall mshr miss latency system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed
system.cpu.icache.demand_hits 1342 # number of demand (read+write) hits system.cpu.rename.UndoneMaps 10369 # Number of HB maps that are undone due to squashing
system.cpu.icache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
system.cpu.icache.demand_miss_rate 0.211979 # miss rate for demand accesses system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.icache.demand_misses 361 # number of demand (read+write) misses system.cpu.rename.skidInsts 1483 # count of insts added to the skid buffer
system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits system.cpu.memDep0.insertedLoads 2081 # Number of loads inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_latency 10354500 # number of demand (read+write) MSHR miss cycles system.cpu.memDep0.insertedStores 1618 # Number of stores inserted to the mem dependence unit.
system.cpu.icache.demand_mshr_miss_rate 0.173224 # mshr miss rate for demand accesses system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.iq.iqInstsAdded 18991 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.iq.iqInstsIssued 16049 # Number of instructions issued
system.cpu.icache.occ_blocks::0 144.881554 # Average occupied blocks per context system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
system.cpu.icache.occ_percent::0 0.070743 # Average percentage of cache occupancy system.cpu.iq.iqSquashedInstsExamined 8597 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.icache.overall_accesses 1703 # number of overall (read+write) accesses system.cpu.iq.iqSquashedOperandsExamined 10847 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.icache.overall_avg_miss_latency 36577.562327 # average overall miss latency system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed
system.cpu.icache.overall_avg_mshr_miss_latency 35100 # average overall mshr miss latency system.cpu.iq.issued_per_cycle::samples 13282 # Number of insts issued each cycle
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.iq.issued_per_cycle::mean 1.208327 # Number of insts issued each cycle
system.cpu.icache.overall_hits 1342 # number of overall hits system.cpu.iq.issued_per_cycle::stdev 1.917321 # Number of insts issued each cycle
system.cpu.icache.overall_miss_latency 13204500 # number of overall miss cycles system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.icache.overall_miss_rate 0.211979 # miss rate for overall accesses system.cpu.iq.issued_per_cycle::0 8198 61.72% 61.72% # Number of insts issued each cycle
system.cpu.icache.overall_misses 361 # number of overall misses system.cpu.iq.issued_per_cycle::1 1295 9.75% 71.47% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits system.cpu.iq.issued_per_cycle::2 980 7.38% 78.85% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_latency 10354500 # number of overall MSHR miss cycles system.cpu.iq.issued_per_cycle::3 727 5.47% 84.32% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_miss_rate 0.173224 # mshr miss rate for overall accesses system.cpu.iq.issued_per_cycle::4 779 5.87% 90.19% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses system.cpu.iq.issued_per_cycle::5 582 4.38% 94.57% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.iq.issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.iq.issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle
system.cpu.icache.replacements 0 # number of replacements system.cpu.iq.issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle
system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.icache.tagsinuse 144.881554 # Cycle average of tags in use system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.icache.total_refs 1342 # Total number of references to valid blocks. system.cpu.iq.issued_per_cycle::total 13282 # Number of insts issued each cycle
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 566 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 1545 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 0.675461 # Inst execution rate
system.cpu.iew.exec_refs 2952 # number of memory reference insts executed
system.cpu.iew.exec_stores 1295 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 2082 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1617 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 19032 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 693 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 15362 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1477 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 1026 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 683 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 497 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 14668 # num instructions consuming a value
system.cpu.iew.wb_count 15056 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.677734 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 9941 # num instructions producing a value
system.cpu.iew.wb_rate 0.662006 # insts written-back per cycle
system.cpu.iew.wb_sent 15179 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 22959 # number of integer regfile reads
system.cpu.int_regfile_writes 13993 # number of integer regfile writes
system.cpu.ipc 0.431298 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.431298 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 12893 80.31% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 16055 # Type of FU issued
system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009156 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available
@ -332,129 +135,326 @@ system.cpu.iq.fu_full::MemRead 27 18.37% 87.07% # at
system.cpu.iq.fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 16193 # Number of integer alu accesses system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
system.cpu.iq.int_inst_queue_reads 45588 # Number of integer instruction queue reads system.cpu.iq.FU_type_0::IntAlu 12887 80.30% 80.32% # Type of FU issued
system.cpu.iq.int_inst_queue_wakeup_accesses 15052 # Number of integer instruction queue wakeup accesses system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.int_inst_queue_writes 27650 # Number of integer instruction queue writes system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqInstsAdded 18999 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqInstsIssued 16055 # Number of instructions issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqSquashedInstsExamined 8610 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.iqSquashedOperandsExamined 10851 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::samples 13286 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::mean 1.208415 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::stdev 1.917020 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::0 8201 61.73% 61.73% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::1 1290 9.71% 71.44% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::2 986 7.42% 78.86% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::3 726 5.46% 84.32% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::4 782 5.89% 90.21% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::5 580 4.37% 94.57% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.issued_per_cycle::total 13286 # Number of insts issued each cycle system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.32% # Type of FU issued
system.cpu.iq.rate 0.705931 # Inst issue rate system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.32% # Type of FU issued
system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.32% # Type of FU issued
system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104 # average ReadExReq miss latency system.cpu.iq.FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency system.cpu.iq.FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_miss_latency 2664500 # number of ReadExReq miss cycles system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses system.cpu.iq.FU_type_0::total 16049 # Type of FU issued
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles system.cpu.iq.rate 0.705792 # Inst issue rate
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses system.cpu.iq.fu_busy_rate 0.009159 # FU busy rate (busy events/executed inst)
system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) system.cpu.iq.int_inst_queue_reads 45572 # Number of integer instruction queue reads
system.cpu.l2cache.ReadReq_avg_miss_latency 34244.444444 # average ReadReq miss latency system.cpu.iq.int_inst_queue_writes 27629 # Number of integer instruction queue writes
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency system.cpu.iq.int_inst_queue_wakeup_accesses 15050 # Number of integer instruction queue wakeup accesses
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads
system.cpu.l2cache.ReadReq_miss_latency 12328000 # number of ReadReq miss cycles system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses system.cpu.iq.int_alu_accesses 16187 # Number of integer alu accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.iew.lsq.thread0.squashedLoads 1025 # Number of loads squashed
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1475 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 19024 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 215 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2081 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1618 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 498 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 15360 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 689 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 2952 # number of memory reference insts executed
system.cpu.iew.exec_branches 1546 # Number of branches executed
system.cpu.iew.exec_stores 1295 # Number of stores executed
system.cpu.iew.exec_rate 0.675491 # Inst execution rate
system.cpu.iew.wb_sent 15177 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 15054 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9950 # num instructions producing a value
system.cpu.iew.wb_consumers 14675 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.662034 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.678024 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 9214 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11807 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.830778 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.597683 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8187 69.34% 69.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1225 10.38% 79.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 582 4.93% 84.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11807 # Number of insts commited each cycle
system.cpu.commit.count 9809 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 1990 # Number of memory references committed
system.cpu.commit.loads 1056 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1214 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9714 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 30689 # The number of ROB reads
system.cpu.rob.rob_writes 39546 # The number of ROB writes
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 9809 # Number of Instructions Simulated
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
system.cpu.cpi 2.318177 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.318177 # CPI: Total CPI of All Threads
system.cpu.ipc 0.431373 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.431373 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 22959 # number of integer regfile reads
system.cpu.int_regfile_writes 13989 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.misc_regfile_reads 6812 # number of misc regfile reads
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 144.881621 # Cycle average of tags in use
system.cpu.icache.total_refs 1339 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.538983 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 144.881621 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.070743 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 1339 # number of ReadReq hits
system.cpu.icache.demand_hits 1339 # number of demand (read+write) hits
system.cpu.icache.overall_hits 1339 # number of overall hits
system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses
system.cpu.icache.demand_misses 361 # number of demand (read+write) misses
system.cpu.icache.overall_misses 361 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 13205500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 13205500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 13205500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 1700 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 1700 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 1700 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.212353 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.212353 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.212353 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36580.332410 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36580.332410 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36580.332410 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 10355500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 10355500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 10355500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.173529 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.173529 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.173529 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35103.389831 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 85.872025 # Cycle average of tags in use
system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 85.872025 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.020965 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 2039 # number of overall hits
system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 426 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 178.189347 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.occ_blocks::0 178.189347 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.005438 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 12329000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2664000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 14993000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 14993000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34247.222222 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34597.402597 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34308.924485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34308.924485 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_avg_miss_latency 34307.780320 # average overall miss latency system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 14992500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.occ_blocks::0 178.188786 # Average occupied blocks per context system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.occ_percent::0 0.005438 # Average percentage of cache occupancy system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses
system.cpu.l2cache.overall_avg_miss_latency 34307.780320 # average overall miss latency system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.overall_miss_latency 14992500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 437 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 178.188786 # Cycle average of tags in use system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2082 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1617 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 6812 # number of misc regfile reads
system.cpu.numCycles 22743 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 565 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 7327 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 248 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 44292 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 21008 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 19746 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 3097 # Number of cycles rename is running
system.cpu.rename.SquashCycles 1477 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 380 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 10378 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 44276 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 440 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
system.cpu.rename.skidInsts 1483 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 30699 # The number of ROB reads
system.cpu.rob.rob_writes 39564 # The number of ROB writes
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------