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Regression: Updates due to changes to Ruby memory controller

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This commit is contained in:
Nilay Vaish 2012-09-10 12:44:03 -05:00
parent c5bf1390aa
commit 5cdf221d8c
26 changed files with 1011 additions and 924 deletions
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75
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -11,6 +11,7 @@ type=LinuxX86System
children=acpi_description_table_pointer cpu0 cpu1 dir_cntrl0 dma_cntrl0 e820_table intel_mp_pointer intel_mp_table intrctrl l1_cntrl0 l1_cntrl1 l2_cntrl0 pc physmem piobus ruby smbios_table sys_port_proxy children=acpi_description_table_pointer cpu0 cpu1 dir_cntrl0 dma_cntrl0 e820_table intel_mp_pointer intel_mp_table intrctrl l1_cntrl0 l1_cntrl1 l2_cntrl0 pc physmem piobus ruby smbios_table sys_port_proxy
acpi_description_table_pointer=system.acpi_description_table_pointer acpi_description_table_pointer=system.acpi_description_table_pointer
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
clock=1
e820_table=system.e820_table e820_table=system.e820_table
init_param=0 init_param=0
intel_mp_pointer=system.intel_mp_pointer intel_mp_pointer=system.intel_mp_pointer
@ -69,7 +70,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -86,14 +86,16 @@ walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker] [system.cpu0.dtb.walker]
type=X86PagetableWalker type=X86PagetableWalker
clock=1
system=system system=system
port=system.l1_cntrl0.sequencer.slave[3] port=system.l1_cntrl0.sequencer.slave[3]
[system.cpu0.interrupts] [system.cpu0.interrupts]
type=X86LocalApic type=X86LocalApic
clock=1
int_latency=1000 int_latency=1000
pio_addr=2305843009213693952 pio_addr=2305843009213693952
pio_latency=1000 pio_latency=100000
system=system system=system
int_master=system.piobus.slave[4] int_master=system.piobus.slave[4]
int_slave=system.piobus.master[19] int_slave=system.piobus.master[19]
@ -107,6 +109,7 @@ walker=system.cpu0.itb.walker
[system.cpu0.itb.walker] [system.cpu0.itb.walker]
type=X86PagetableWalker type=X86PagetableWalker
clock=1
system=system system=system
port=system.l1_cntrl0.sequencer.slave[2] port=system.l1_cntrl0.sequencer.slave[2]
@ -133,7 +136,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -150,14 +152,16 @@ walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker] [system.cpu1.dtb.walker]
type=X86PagetableWalker type=X86PagetableWalker
clock=1
system=system system=system
port=system.l1_cntrl1.sequencer.slave[3] port=system.l1_cntrl1.sequencer.slave[3]
[system.cpu1.interrupts] [system.cpu1.interrupts]
type=X86LocalApic type=X86LocalApic
clock=1
int_latency=1000 int_latency=1000
pio_addr=2305843009213693952 pio_addr=2305843009213693952
pio_latency=1000 pio_latency=100000
system=system system=system
int_master=system.piobus.slave[5] int_master=system.piobus.slave[5]
int_slave=system.piobus.master[21] int_slave=system.piobus.master[21]
@ -171,6 +175,7 @@ walker=system.cpu1.itb.walker
[system.cpu1.itb.walker] [system.cpu1.itb.walker]
type=X86PagetableWalker type=X86PagetableWalker
clock=1
system=system system=system
port=system.l1_cntrl1.sequencer.slave[2] port=system.l1_cntrl1.sequencer.slave[2]
@ -207,9 +212,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=2500
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -218,6 +223,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -237,6 +243,7 @@ version=0
[system.dma_cntrl0.dma_sequencer] [system.dma_cntrl0.dma_sequencer]
type=DMASequencer type=DMASequencer
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true
@ -670,6 +677,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.L1DcacheMemory dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory icache=system.l1_cntrl0.L1IcacheMemory
@ -734,6 +742,7 @@ tagArrayBanks=1
[system.l1_cntrl1.sequencer] [system.l1_cntrl1.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl1.L1DcacheMemory dcache=system.l1_cntrl1.L1DcacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl1.L1IcacheMemory icache=system.l1_cntrl1.L1IcacheMemory
@ -785,9 +794,10 @@ system=system
[system.pc.behind_pci] [system.pc.behind_pci]
type=IsaFake type=IsaFake
clock=1
fake_mem=false fake_mem=false
pio_addr=9223372036854779128 pio_addr=9223372036854779128
pio_latency=1000 pio_latency=100000
pio_size=8 pio_size=8
ret_bad_addr=false ret_bad_addr=false
ret_data16=65535 ret_data16=65535
@ -802,8 +812,9 @@ pio=system.piobus.master[12]
[system.pc.com_1] [system.pc.com_1]
type=Uart8250 type=Uart8250
children=terminal children=terminal
clock=1
pio_addr=9223372036854776824 pio_addr=9223372036854776824
pio_latency=1000 pio_latency=100000
platform=system.pc platform=system.pc
system=system system=system
terminal=system.pc.com_1.terminal terminal=system.pc.com_1.terminal
@ -825,9 +836,10 @@ port=3456
[system.pc.fake_com_2] [system.pc.fake_com_2]
type=IsaFake type=IsaFake
clock=1
fake_mem=false fake_mem=false
pio_addr=9223372036854776568 pio_addr=9223372036854776568
pio_latency=1000 pio_latency=100000
pio_size=8 pio_size=8
ret_bad_addr=false ret_bad_addr=false
ret_data16=65535 ret_data16=65535
@ -841,9 +853,10 @@ pio=system.piobus.master[14]
[system.pc.fake_com_3] [system.pc.fake_com_3]
type=IsaFake type=IsaFake
clock=1
fake_mem=false fake_mem=false
pio_addr=9223372036854776808 pio_addr=9223372036854776808
pio_latency=1000 pio_latency=100000
pio_size=8 pio_size=8
ret_bad_addr=false ret_bad_addr=false
ret_data16=65535 ret_data16=65535
@ -857,9 +870,10 @@ pio=system.piobus.master[15]
[system.pc.fake_com_4] [system.pc.fake_com_4]
type=IsaFake type=IsaFake
clock=1
fake_mem=false fake_mem=false
pio_addr=9223372036854776552 pio_addr=9223372036854776552
pio_latency=1000 pio_latency=100000
pio_size=8 pio_size=8
ret_bad_addr=false ret_bad_addr=false
ret_data16=65535 ret_data16=65535
@ -873,9 +887,10 @@ pio=system.piobus.master[16]
[system.pc.fake_floppy] [system.pc.fake_floppy]
type=IsaFake type=IsaFake
clock=1
fake_mem=false fake_mem=false
pio_addr=9223372036854776818 pio_addr=9223372036854776818
pio_latency=1000 pio_latency=100000
pio_size=2 pio_size=2
ret_bad_addr=false ret_bad_addr=false
ret_data16=65535 ret_data16=65535
@ -889,9 +904,10 @@ pio=system.piobus.master[17]
[system.pc.i_dont_exist] [system.pc.i_dont_exist]
type=IsaFake type=IsaFake
clock=1
fake_mem=false fake_mem=false
pio_addr=9223372036854775936 pio_addr=9223372036854775936
pio_latency=1000 pio_latency=100000
pio_size=1 pio_size=1
ret_bad_addr=false ret_bad_addr=false
ret_data16=65535 ret_data16=65535
@ -906,7 +922,8 @@ pio=system.piobus.master[11]
[system.pc.pciconfig] [system.pc.pciconfig]
type=PciConfigAll type=PciConfigAll
bus=0 bus=0
pio_latency=1 clock=1
pio_latency=30000
platform=system.pc platform=system.pc
size=16777216 size=16777216
system=system system=system
@ -921,7 +938,6 @@ io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1 pic1=system.pc.south_bridge.pic1
pic2=system.pc.south_bridge.pic2 pic2=system.pc.south_bridge.pic2
pio_latency=1000
pit=system.pc.south_bridge.pit pit=system.pc.south_bridge.pit
platform=system.pc platform=system.pc
speaker=system.pc.south_bridge.speaker speaker=system.pc.south_bridge.speaker
@ -929,9 +945,10 @@ speaker=system.pc.south_bridge.speaker
[system.pc.south_bridge.cmos] [system.pc.south_bridge.cmos]
type=Cmos type=Cmos
children=int_pin children=int_pin
clock=1
int_pin=system.pc.south_bridge.cmos.int_pin int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920 pio_addr=9223372036854775920
pio_latency=1000 pio_latency=100000
system=system system=system
time=Sun Jan 1 00:00:00 2012 time=Sun Jan 1 00:00:00 2012
pio=system.piobus.master[1] pio=system.piobus.master[1]
@ -941,8 +958,9 @@ type=X86IntSourcePin
[system.pc.south_bridge.dma1] [system.pc.south_bridge.dma1]
type=I8237 type=I8237
clock=1
pio_addr=9223372036854775808 pio_addr=9223372036854775808
pio_latency=1000 pio_latency=100000
system=system system=system
pio=system.piobus.master[2] pio=system.piobus.master[2]
@ -987,16 +1005,15 @@ SubClassCode=1
SubsystemID=0 SubsystemID=0
SubsystemVendorID=0 SubsystemVendorID=0
VendorID=32902 VendorID=32902
clock=1
config_latency=20000 config_latency=20000
ctrl_offset=0 ctrl_offset=0
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
io_shift=0 io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0 pci_bus=0
pci_dev=4 pci_dev=4
pci_func=0 pci_func=0
pio_latency=1000 pio_latency=30000
platform=system.pc platform=system.pc
system=system system=system
config=system.piobus.master[4] config=system.piobus.master[4]
@ -1123,10 +1140,11 @@ number=12
[system.pc.south_bridge.io_apic] [system.pc.south_bridge.io_apic]
type=I82094AA type=I82094AA
apic_id=2 apic_id=2
clock=1
external_int_pic=system.pc.south_bridge.pic1 external_int_pic=system.pc.south_bridge.pic1
int_latency=1000 int_latency=1000
pio_addr=4273995776 pio_addr=4273995776
pio_latency=1000 pio_latency=100000
system=system system=system
int_master=system.piobus.slave[1] int_master=system.piobus.slave[1]
pio=system.piobus.master[10] pio=system.piobus.master[10]
@ -1134,12 +1152,13 @@ pio=system.piobus.master[10]
[system.pc.south_bridge.keyboard] [system.pc.south_bridge.keyboard]
type=I8042 type=I8042
children=keyboard_int_pin mouse_int_pin children=keyboard_int_pin mouse_int_pin
clock=1
command_port=9223372036854775908 command_port=9223372036854775908
data_port=9223372036854775904 data_port=9223372036854775904
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0 pio_addr=0
pio_latency=1000 pio_latency=100000
system=system system=system
pio=system.piobus.master[5] pio=system.piobus.master[5]
@ -1152,10 +1171,11 @@ type=X86IntSourcePin
[system.pc.south_bridge.pic1] [system.pc.south_bridge.pic1]
type=I8259 type=I8259
children=output children=output
clock=1
mode=I8259Master mode=I8259Master
output=system.pc.south_bridge.pic1.output output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840 pio_addr=9223372036854775840
pio_latency=1000 pio_latency=100000
slave=system.pc.south_bridge.pic2 slave=system.pc.south_bridge.pic2
system=system system=system
pio=system.piobus.master[6] pio=system.piobus.master[6]
@ -1166,10 +1186,11 @@ type=X86IntSourcePin
[system.pc.south_bridge.pic2] [system.pc.south_bridge.pic2]
type=I8259 type=I8259
children=output children=output
clock=1
mode=I8259Slave mode=I8259Slave
output=system.pc.south_bridge.pic2.output output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968 pio_addr=9223372036854775968
pio_latency=1000 pio_latency=100000
slave=Null slave=Null
system=system system=system
pio=system.piobus.master[7] pio=system.piobus.master[7]
@ -1180,9 +1201,10 @@ type=X86IntSourcePin
[system.pc.south_bridge.pit] [system.pc.south_bridge.pit]
type=I8254 type=I8254
children=int_pin children=int_pin
clock=1
int_pin=system.pc.south_bridge.pit.int_pin int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872 pio_addr=9223372036854775872
pio_latency=1000 pio_latency=100000
system=system system=system
pio=system.piobus.master[8] pio=system.piobus.master[8]
@ -1191,14 +1213,16 @@ type=X86IntSourcePin
[system.pc.south_bridge.speaker] [system.pc.south_bridge.speaker]
type=PcSpeaker type=PcSpeaker
clock=1
i8254=system.pc.south_bridge.pit i8254=system.pc.south_bridge.pit
pio_addr=9223372036854775905 pio_addr=9223372036854775905
pio_latency=1000 pio_latency=100000
system=system system=system
pio=system.piobus.master[9] pio=system.piobus.master[9]
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -1402,6 +1426,7 @@ version=
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

533
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
View file

@ -1,26 +1,26 @@
Real time: Jul/22/2012 09:10:52 Real time: Sep/10/2012 12:39:22
Profiler Stats Profiler Stats
-------------- --------------
Elapsed_time_in_seconds: 936 Elapsed_time_in_seconds: 743
Elapsed_time_in_minutes: 15.6 Elapsed_time_in_minutes: 12.3833
Elapsed_time_in_hours: 0.26 Elapsed_time_in_hours: 0.206389
Elapsed_time_in_days: 0.0108333 Elapsed_time_in_days: 0.00859954
Virtual_time_in_seconds: 935.71 Virtual_time_in_seconds: 741.97
Virtual_time_in_minutes: 15.5952 Virtual_time_in_minutes: 12.3662
Virtual_time_in_hours: 0.259919 Virtual_time_in_hours: 0.206103
Virtual_time_in_days: 0.01083 Virtual_time_in_days: 0.00858762
Ruby_current_time: 10611136755 Ruby_current_time: 10410013848
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 10611136755 Ruby_cycles: 10410013848
mbytes_resident: 255.668 mbytes_resident: 256.176
mbytes_total: 506.359 mbytes_total: 493.555
resident_ratio: 0.504922 resident_ratio: 0.51905
ruby_cycles_executed: [ 10611136756 10611136756 ] ruby_cycles_executed: [ 10410013849 10410013849 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-1:0 L1Cache-0:0 L1Cache-1:0
@ -30,18 +30,18 @@ DMA-0:0
Busy Bank Count:0 Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 189629563 average: 1.00009 | standard deviation: 0.00948804 | 0 189612491 17072 ] sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154767604 average: 1.00012 | standard deviation: 0.0109597 | 0 154749012 18592 ]
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 1 max: 171 count: 189629562 average: 3.38837 | standard deviation: 5.2007 | 0 0 0 186971926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 971398 311 266 292 1434090 392 51 54821 354 335 192 16528 110 142 35 32 50 3 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12755 7 7 13 100203 39 33 32 64996 57 6 5 14 47 5 3 0 3 3 ] miss_latency: [binsize: 2 max: 260 count: 154767603 average: 3.45135 | standard deviation: 5.08515 | 0 152082574 0 0 0 0 0 0 0 927069 2071 1452677 1549 98893 1824 27121 347 210 5 45 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3350 5780 7258 9605 51199 184 503 87 104 134 4 25 2 6 9 6 9 4 5 26 3 16 8 6 14 11 476 4256 9975 17446 13241 43185 812 901 2319 281 806 17 14 43 17 28 13 16 52 11 26 12 22 41 16 19 13 17 16 85 151 130 145 254 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 1 max: 168 count: 14911026 average: 5.14403 | standard deviation: 9.30738 | 0 0 0 13525110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 129680 44 39 43 1195959 268 20 19713 183 210 99 4905 71 117 32 25 30 3 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2553 0 1 1 16289 11 3 6 15564 15 4 3 4 14 2 1 ] miss_latency_LD: [binsize: 2 max: 216 count: 15352565 average: 5.0885 | standard deviation: 8.5054 | 0 13921971 0 0 0 0 0 0 0 116199 265 1232702 939 35537 1117 12311 282 166 3 45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 878 731 2459 2787 1965 61 84 35 25 25 1 1 0 0 0 2 2 2 3 2 1 2 5 0 0 3 1 1317 2710 4736 6106 5752 320 286 235 109 111 8 3 7 7 6 6 5 9 3 4 5 8 3 8 2 9 4 4 28 16 49 58 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 1 max: 171 count: 9485677 average: 5.51946 | standard deviation: 17.9241 | 0 0 0 9133789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28572 9 9 4 181841 81 8 14495 87 61 54 1688 25 14 1 4 6 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4608 3 3 4 71166 22 16 18 49004 33 1 2 6 31 3 1 0 3 3 ] miss_latency_ST: [binsize: 2 max: 260 count: 9753198 average: 5.121 | standard deviation: 15.1318 | 0 9401711 0 0 0 0 0 0 0 27244 31 167378 295 28869 386 2208 41 13 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 751 3326 3556 6356 49119 86 391 39 72 108 2 22 2 2 7 3 6 2 2 24 2 12 2 3 12 5 473 950 2938 8535 6752 37031 336 518 1977 161 689 7 10 35 5 18 4 8 39 5 19 5 11 36 6 15 4 10 10 19 100 60 86 234 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 1 max: 168 count: 164061652 average: 3.09372 | standard deviation: 1.91508 | 0 0 0 163246895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 796713 238 201 234 171 20 21 22 23 20 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5320 4 3 8 11707 6 12 7 5 9 1 0 4 1 0 1 ] miss_latency_IFETCH: [binsize: 2 max: 236 count: 128448156 average: 3.11282 | standard deviation: 1.97328 | 0 127660849 0 0 0 0 0 0 0 768151 1710 1618 183 156 44 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1613 1619 801 37 40 20 24 8 1 1 1 2 0 4 2 1 1 0 0 0 0 2 0 3 1 2 2 1977 4254 4118 212 202 150 91 102 7 3 1 1 1 5 4 3 3 4 2 3 2 3 2 2 2 0 3 2 38 35 21 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_RMW_Read: [binsize: 1 max: 166 count: 493615 average: 6.17279 | standard deviation: 10.7803 | 0 0 0 427441 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10781 17 14 10 33213 10 0 12152 28 23 20 8480 5 3 1 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228 0 0 0 868 0 1 1 313 0 0 0 0 1 ] miss_latency_RMW_Read: [binsize: 2 max: 214 count: 526656 average: 6.20613 | standard deviation: 9.47551 | 0 453026 0 0 0 0 0 0 0 10693 56 32914 28 18960 66 9490 7 7 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 86 384 383 52 14 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 48 16 130 167 3 5 3 4 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 338796 average: 5.46747 | standard deviation: 8.06826 | 0 0 0 299895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5652 3 3 1 22906 13 2 8439 33 21 19 1455 9 8 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 0 0 0 173 0 1 0 110 ] miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 343514 average: 5.69306 | standard deviation: 7.99809 | 0 301503 0 0 0 0 0 0 0 4782 9 18065 104 15371 211 3112 17 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 18 58 42 23 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 25 41 41 33 3 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338796 average: 3 | standard deviation: 0 | 0 0 0 338796 ] miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 343514 average: 3 | standard deviation: 0 | 0 0 0 343514 ]
miss_latency_NULL: [binsize: 1 max: 171 count: 189629562 average: 3.38837 | standard deviation: 5.2007 | 0 0 0 186971926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 971398 311 266 292 1434090 392 51 54821 354 335 192 16528 110 142 35 32 50 3 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12755 7 7 13 100203 39 33 32 64996 57 6 5 14 47 5 3 0 3 3 ] miss_latency_NULL: [binsize: 2 max: 260 count: 154767603 average: 3.45135 | standard deviation: 5.08515 | 0 152082574 0 0 0 0 0 0 0 927069 2071 1452677 1549 98893 1824 27121 347 210 5 45 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3350 5780 7258 9605 51199 184 503 87 104 134 4 25 2 6 9 6 9 4 5 26 3 16 8 6 14 11 476 4256 9975 17446 13241 43185 812 901 2319 281 806 17 14 43 17 28 13 16 52 11 26 12 22 41 16 19 13 17 16 85 151 130 145 254 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -52,12 +52,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0 imcomplete_dir_Times: 0
miss_latency_LD_NULL: [binsize: 1 max: 168 count: 14911026 average: 5.14403 | standard deviation: 9.30738 | 0 0 0 13525110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 129680 44 39 43 1195959 268 20 19713 183 210 99 4905 71 117 32 25 30 3 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2553 0 1 1 16289 11 3 6 15564 15 4 3 4 14 2 1 ] miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15352565 average: 5.0885 | standard deviation: 8.5054 | 0 13921971 0 0 0 0 0 0 0 116199 265 1232702 939 35537 1117 12311 282 166 3 45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 878 731 2459 2787 1965 61 84 35 25 25 1 1 0 0 0 2 2 2 3 2 1 2 5 0 0 3 1 1317 2710 4736 6106 5752 320 286 235 109 111 8 3 7 7 6 6 5 9 3 4 5 8 3 8 2 9 4 4 28 16 49 58 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_NULL: [binsize: 1 max: 171 count: 9485677 average: 5.51946 | standard deviation: 17.9241 | 0 0 0 9133789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28572 9 9 4 181841 81 8 14495 87 61 54 1688 25 14 1 4 6 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4608 3 3 4 71166 22 16 18 49004 33 1 2 6 31 3 1 0 3 3 ] miss_latency_ST_NULL: [binsize: 2 max: 260 count: 9753198 average: 5.121 | standard deviation: 15.1318 | 0 9401711 0 0 0 0 0 0 0 27244 31 167378 295 28869 386 2208 41 13 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 751 3326 3556 6356 49119 86 391 39 72 108 2 22 2 2 7 3 6 2 2 24 2 12 2 3 12 5 473 950 2938 8535 6752 37031 336 518 1977 161 689 7 10 35 5 18 4 8 39 5 19 5 11 36 6 15 4 10 10 19 100 60 86 234 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_NULL: [binsize: 1 max: 168 count: 164061652 average: 3.09372 | standard deviation: 1.91508 | 0 0 0 163246895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 796713 238 201 234 171 20 21 22 23 20 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5320 4 3 8 11707 6 12 7 5 9 1 0 4 1 0 1 ] miss_latency_IFETCH_NULL: [binsize: 2 max: 236 count: 128448156 average: 3.11282 | standard deviation: 1.97328 | 0 127660849 0 0 0 0 0 0 0 768151 1710 1618 183 156 44 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1613 1619 801 37 40 20 24 8 1 1 1 2 0 4 2 1 1 0 0 0 0 2 0 3 1 2 2 1977 4254 4118 212 202 150 91 102 7 3 1 1 1 5 4 3 3 4 2 3 2 3 2 2 2 0 3 2 38 35 21 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_RMW_Read_NULL: [binsize: 1 max: 166 count: 493615 average: 6.17279 | standard deviation: 10.7803 | 0 0 0 427441 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10781 17 14 10 33213 10 0 12152 28 23 20 8480 5 3 1 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228 0 0 0 868 0 1 1 313 0 0 0 0 1 ] miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 526656 average: 6.20613 | standard deviation: 9.47551 | 0 453026 0 0 0 0 0 0 0 10693 56 32914 28 18960 66 9490 7 7 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 86 384 383 52 14 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 48 16 130 167 3 5 3 4 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 338796 average: 5.46747 | standard deviation: 8.06826 | 0 0 0 299895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5652 3 3 1 22906 13 2 8439 33 21 19 1455 9 8 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 0 0 0 173 0 1 0 110 ] miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 343514 average: 5.69306 | standard deviation: 7.99809 | 0 301503 0 0 0 0 0 0 0 4782 9 18065 104 15371 211 3112 17 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 18 58 42 23 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 25 41 41 33 3 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338796 average: 3 | standard deviation: 0 | 0 0 0 338796 ] miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 343514 average: 3 | standard deviation: 0 | 0 0 0 343514 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -71,11 +71,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
Message Delayed Cycles Message Delayed Cycles
---------------------- ----------------------
Total_delay_cycles: [binsize: 1 max: 13 count: 10872044 average: 0.594087 | standard deviation: 1.42322 | 9257017 966 601 871 1611047 867 138 98 114 242 5 7 16 55 ] Total_delay_cycles: [binsize: 1 max: 37 count: 11103363 average: 0.602841 | standard deviation: 1.43362 | 9429040 3332 1976 3111 1660414 3191 363 280 324 1123 43 53 45 64 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4773322 average: 0.0220343 | standard deviation: 0.294682 | 4746360 488 366 641 25333 123 1 2 5 3 ] Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899404 average: 0.0429665 | standard deviation: 0.408913 | 4844305 1818 1325 2404 49185 275 22 10 27 33 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098722 average: 1.04182 | standard deviation: 1.75681 | 4510657 478 235 230 1585714 744 137 96 109 239 5 7 16 55 ] virtual_network_0_delay_cycles: [binsize: 1 max: 37 count: 6203959 average: 1.04499 | standard deviation: 1.76161 | 4584735 1514 651 707 1611229 2916 341 270 297 1090 43 53 45 64 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 4690840 average: 0.0221975 | standard deviation: 0.295989 | 4664268 387 299 538 25234 106 1 2 5 ] virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4764540 average: 0.0435379 | standard deviation: 0.412109 | 4710621 1470 1106 2169 48864 222 21 10 26 31 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 82482 average: 0.0127543 | standard deviation: 0.207023 | 82092 101 67 103 99 17 0 0 0 3 ] virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 134864 average: 0.0227785 | standard deviation: 0.272208 | 133684 348 219 235 321 53 1 0 1 2 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -87,82 +87,82 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4773322 average: 0.0220343 |
Resource Usage Resource Usage
-------------- --------------
page_size: 4096 page_size: 4096
user_time: 935 user_time: 741
system_time: 0 system_time: 0
page_reclaims: 66867 page_reclaims: 56598
page_faults: 113 page_faults: 18
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 28712
block_outputs: 0 block_outputs: 496
Network Stats Network Stats
------------- -------------
total_msg_count_Control: 8507592 68060736 total_msg_count_Control: 8574735 68597880
total_msg_count_Request_Control: 245557 1964456 total_msg_count_Request_Control: 402718 3221744
total_msg_count_Response_Data: 8804181 633901032 total_msg_count_Response_Data: 8871975 638782200
total_msg_count_Response_Control: 10879239 87033912 total_msg_count_Response_Control: 11214822 89718576
total_msg_count_Writeback_Data: 4760235 342736920 total_msg_count_Writeback_Data: 4845309 348862248
total_msg_count_Writeback_Control: 290208 2321664 total_msg_count_Writeback_Control: 241377 1931016
total_msgs: 33487012 total_bytes: 1136018720 total_msgs: 34150936 total_bytes: 1151113664
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.0329182 links_utilized_percent_switch_0: 0.0911552
links_utilized_percent_switch_0_link_0: 0.0389055 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 0.0987912 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.0269309 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.0835191 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 42316 338528 [ 42316 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Request_Control: 70786 566288 [ 70786 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 857284 61724448 [ 0 857284 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 2105042 151563024 [ 0 2105042 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Control: 498762 3990096 [ 0 498762 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Control: 1552199 12417592 [ 0 1552199 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 869376 6955008 [ 869376 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Control: 2125660 17005280 [ 2125660 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Response_Data: 39863 2870136 [ 0 39863 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Response_Data: 64978 4678416 [ 0 64978 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Response_Control: 527853 4222824 [ 0 16344 511509 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Response_Control: 1603790 12830320 [ 0 30250 1573540 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 435670 31368240 [ 435613 57 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Data: 1445650 104086800 [ 1445590 60 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 38325 306600 [ 38325 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Control: 63591 508728 [ 63591 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.0731522 links_utilized_percent_switch_1: 0.0193582
links_utilized_percent_switch_1_link_0: 0.0814063 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 0.024614 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.064898 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.0141024 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 40166 321328 [ 40166 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 64078 512624 [ 64078 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 1778465 128049480 [ 0 1778465 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Response_Data: 536393 38620296 [ 0 536393 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Control: 1229916 9839328 [ 0 1229916 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Response_Control: 233034 1864272 [ 0 233034 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Control: 1788260 14306080 [ 1788260 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Control: 559369 4474952 [ 559369 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 33641 2422152 [ 0 33641 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Data: 62193 4477896 [ 0 62193 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Control: 1263724 10109792 [ 0 17462 1246262 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Control: 275069 2200552 [ 0 24994 250075 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Data: 1151075 82877400 [ 1150966 109 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Data: 169453 12200616 [ 169266 187 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 58411 467288 [ 58411 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 16868 134944 [ 16868 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.110433 links_utilized_percent_switch_2: 0.113355
links_utilized_percent_switch_2_link_0: 0.0977505 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 0.101973 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.123116 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.124737 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Control: 2657636 21261088 [ 2657636 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Control: 2685029 21480232 [ 2685029 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 203222 14631984 [ 0 203222 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 221014 15913008 [ 0 221014 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Control: 1880796 15046368 [ 0 123025 1757771 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Control: 1940226 15521808 [ 0 116611 1823615 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Data: 1586745 114245640 [ 1586579 166 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Data: 1615103 116287416 [ 1614856 247 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 96736 773888 [ 96736 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 80459 643672 [ 80459 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 178228 1425824 [ 178228 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Control: 173216 1385728 [ 173216 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Request_Control: 80593 644744 [ 80593 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Request_Control: 132990 1063920 [ 132990 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Data: 2682995 193175640 [ 0 2682995 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Response_Data: 2656938 191299536 [ 0 2656938 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Control: 1722141 13777128 [ 0 1722141 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Response_Control: 1751724 14013792 [ 0 1751724 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 2 switch_3_inlinks: 2
switch_3_outlinks: 2 switch_3_outlinks: 2
links_utilized_percent_switch_3: 0.00653492 links_utilized_percent_switch_3: 0.00649987
links_utilized_percent_switch_3_link_0: 0.00498048 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_0: 0.00499478 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0.00808936 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_1: 0.00800496 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Control: 178228 1425824 [ 178228 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Control: 173216 1385728 [ 173216 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 95756 6894432 [ 0 95756 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 94876 6831072 [ 0 94876 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Control: 16939 135512 [ 0 16939 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Control: 12815 102520 [ 0 12815 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Data: 178228 12832416 [ 0 178228 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Response_Data: 173216 12471552 [ 0 173216 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Control: 112695 901560 [ 0 112695 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Response_Control: 107691 861528 [ 0 107691 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_4_inlinks: 2 switch_4_inlinks: 2
switch_4_outlinks: 2 switch_4_outlinks: 2
@ -173,104 +173,104 @@ links_utilized_percent_switch_4: 0
switch_5_inlinks: 5 switch_5_inlinks: 5
switch_5_outlinks: 5 switch_5_outlinks: 5
links_utilized_percent_switch_5: 0.0446086 links_utilized_percent_switch_5: 0.0460746
links_utilized_percent_switch_5_link_0: 0.0389055 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_0: 0.0987912 bw: 16000 base_latency: 1
links_utilized_percent_switch_5_link_1: 0.0814063 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_1: 0.024614 bw: 16000 base_latency: 1
links_utilized_percent_switch_5_link_2: 0.0977505 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_2: 0.101973 bw: 16000 base_latency: 1
links_utilized_percent_switch_5_link_3: 0.00498048 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_3: 0.00499478 bw: 16000 base_latency: 1
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
outgoing_messages_switch_5_link_0_Request_Control: 42316 338528 [ 42316 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_0_Request_Control: 70786 566288 [ 70786 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_0_Response_Data: 857284 61724448 [ 0 857284 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_0_Response_Data: 2105042 151563024 [ 0 2105042 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_0_Response_Control: 498762 3990096 [ 0 498762 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_0_Response_Control: 1552199 12417592 [ 0 1552199 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_1_Request_Control: 40166 321328 [ 40166 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_1_Request_Control: 64078 512624 [ 64078 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_1_Response_Data: 1778465 128049480 [ 0 1778465 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_1_Response_Data: 536393 38620296 [ 0 536393 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_1_Response_Control: 1229916 9839328 [ 0 1229916 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_1_Response_Control: 233034 1864272 [ 0 233034 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_2_Control: 2657636 21261088 [ 2657636 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_2_Control: 2685029 21480232 [ 2685029 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_2_Response_Data: 203222 14631984 [ 0 203222 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_2_Response_Data: 221014 15913008 [ 0 221014 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_2_Response_Control: 1880796 15046368 [ 0 123025 1757771 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_2_Response_Control: 1940226 15521808 [ 0 116611 1823615 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_2_Writeback_Data: 1586745 114245640 [ 1586579 166 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_2_Writeback_Data: 1615103 116287416 [ 1614856 247 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_2_Writeback_Control: 96736 773888 [ 96736 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_2_Writeback_Control: 80459 643672 [ 80459 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_3_Control: 178228 1425824 [ 178228 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_3_Control: 173216 1385728 [ 173216 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_3_Response_Data: 95756 6894432 [ 0 95756 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_3_Response_Data: 94876 6831072 [ 0 94876 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_5_link_3_Response_Control: 16939 135512 [ 0 16939 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_3_Response_Control: 12815 102520 [ 0 12815 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 331052 system.l1_cntrl0.L1IcacheMemory_total_misses: 500519
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 331052 system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 500519
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 331052 100% system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 500519 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 538324 system.l1_cntrl0.L1DcacheMemory_total_misses: 1625141
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 538324 system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1625141
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.6959% system.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.0225%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.3041% system.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.9775%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 538324 100% system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1625141 100%
--- L1Cache --- --- L1Cache ---
- Event Counts - - Event Counts -
Load [6302183 8608843 ] 14911026 Load [11656116 3696449 ] 15352565
Ifetch [105452422 58609236 ] 164061658 Ifetch [108814365 19633797 ] 128448162
Store [5316807 5340077 ] 10656884 Store [7712319 3254563 ] 10966882
Inv [16401 17571 ] 33972 Inv [30310 25181 ] 55491
L1_Replacement [842231 1761215 ] 2603446 L1_Replacement [2079410 509274 ] 2588684
Fwd_GETX [11967 11549 ] 23516 Fwd_GETX [15974 15601 ] 31575
Fwd_GETS [13944 11046 ] 24990 Fwd_GETS [24497 23296 ] 47793
Fwd_GET_INSTR [4 0 ] 4 Fwd_GET_INSTR [5 0 ] 5
Data [640 949 ] 1589 Data [1782 948 ] 2730
Data_Exclusive [256580 1019234 ] 1275814 Data_Exclusive [1225582 83107 ] 1308689
DataS_fromL1 [11046 13948 ] 24994 DataS_fromL1 [23296 24502 ] 47798
Data_all_Acks [589018 744334 ] 1333352 Data_all_Acks [854382 427836 ] 1282218
Ack [12092 9795 ] 21887 Ack [20618 22976 ] 43594
Ack_all [12732 10744 ] 23476 Ack_all [22400 23924 ] 46324
WB_Ack [473938 1209377 ] 1683315 WB_Ack [1509181 186134 ] 1695315
- Transitions - - Transitions -
NP Load [286086 1081309 ] 1367395 NP Load [1283915 113877 ] 1397792
NP Ifetch [330926 483173 ] 814099 NP Ifetch [500136 286396 ] 786532
NP Store [226242 197757 ] 423999 NP Store [296383 110025 ] 406408
NP Inv [5584 4068 ] 9652 NP Inv [6709 2651 ] 9360
NP L1_Replacement [0 0 ] 0 NP L1_Replacement [0 0 ] 0
I Load [8355 10166 ] 18521 I Load [16564 16238 ] 32802
I Ifetch [126 532 ] 658 I Ifetch [383 392 ] 775
I Store [5549 5528 ] 11077 I Store [7661 9464 ] 17125
I Inv [0 0 ] 0 I Inv [0 0 ] 0
I L1_Replacement [8754 8728 ] 17482 I L1_Replacement [14967 11936 ] 26903
S Load [576650 500308 ] 1076958 S Load [793810 479655 ] 1273465
S Ifetch [105121368 58125527 ] 163246895 S Ifetch [108313841 19347008 ] 127660849
S Store [12092 9795 ] 21887 S Store [20618 22977 ] 43595
S Inv [10695 13362 ] 24057 S Inv [23499 22176 ] 45675
S L1_Replacement [359539 543110 ] 902649 S L1_Replacement [555262 311204 ] 866466
E Load [1186542 2631089 ] 3817631 E Load [3115905 532300 ] 3648205
E Ifetch [0 0 ] 0 E Ifetch [0 0 ] 0
E Store [82337 84568 ] 166905 E Store [118471 30355 ] 148826
E Inv [65 32 ] 97 E Inv [42 166 ] 208
E L1_Replacement [172847 933185 ] 1106032 E L1_Replacement [1105295 51372 ] 1156667
E Fwd_GETX [241 150 ] 391 E Fwd_GETX [96 110 ] 206
E Fwd_GETS [923 1251 ] 2174 E Fwd_GETS [1518 1045 ] 2563
E Fwd_GET_INSTR [0 0 ] 0 E Fwd_GET_INSTR [1 0 ] 1
M Load [4244550 4385971 ] 8630521 M Load [6445922 2554379 ] 9000301
M Ifetch [0 0 ] 0 M Ifetch [0 0 ] 0
M Store [4990587 5042429 ] 10033016 M Store [7269186 3081742 ] 10350928
M Inv [57 109 ] 166 M Inv [60 187 ] 247
M L1_Replacement [301091 276192 ] 577283 M L1_Replacement [403886 134762 ] 538648
M Fwd_GETX [11726 11399 ] 23125 M Fwd_GETX [15878 15491 ] 31369
M Fwd_GETS [13021 9795 ] 22816 M Fwd_GETS [22979 22251 ] 45230
M Fwd_GET_INSTR [4 0 ] 4 M Fwd_GET_INSTR [4 0 ] 4
IS Load [0 0 ] 0 IS Load [0 0 ] 0
@ -278,26 +278,26 @@ IS Ifetch [0 0 ] 0
IS Store [0 0 ] 0 IS Store [0 0 ] 0
IS Inv [0 0 ] 0 IS Inv [0 0 ] 0
IS L1_Replacement [0 0 ] 0 IS L1_Replacement [0 0 ] 0
IS Data_Exclusive [256580 1019234 ] 1275814 IS Data_Exclusive [1225582 83107 ] 1308689
IS DataS_fromL1 [11046 13948 ] 24994 IS DataS_fromL1 [23296 24502 ] 47798
IS Data_all_Acks [357867 541998 ] 899865 IS Data_all_Acks [552120 309294 ] 861414
IM Load [0 0 ] 0 IM Load [0 0 ] 0
IM Ifetch [0 0 ] 0 IM Ifetch [0 0 ] 0
IM Store [0 0 ] 0 IM Store [0 0 ] 0
IM Inv [0 0 ] 0 IM Inv [0 0 ] 0
IM L1_Replacement [0 0 ] 0 IM L1_Replacement [0 0 ] 0
IM Data [640 949 ] 1589 IM Data [1782 948 ] 2730
IM Data_all_Acks [231151 202336 ] 433487 IM Data_all_Acks [302262 118542 ] 420804
IM Ack [0 0 ] 0 IM Ack [0 0 ] 0
SM Load [0 0 ] 0 SM Load [0 0 ] 0
SM Ifetch [0 0 ] 0 SM Ifetch [0 0 ] 0
SM Store [0 0 ] 0 SM Store [0 0 ] 0
SM Inv [0 0 ] 0 SM Inv [0 1 ] 1
SM L1_Replacement [0 0 ] 0 SM L1_Replacement [0 0 ] 0
SM Ack [12092 9795 ] 21887 SM Ack [20618 22976 ] 43594
SM Ack_all [12732 10744 ] 23476 SM Ack_all [22400 23924 ] 46324
IS_I Load [0 0 ] 0 IS_I Load [0 0 ] 0
IS_I Ifetch [0 0 ] 0 IS_I Ifetch [0 0 ] 0
@ -309,14 +309,14 @@ IS_I DataS_fromL1 [0 0 ] 0
IS_I Data_all_Acks [0 0 ] 0 IS_I Data_all_Acks [0 0 ] 0
M_I Load [0 0 ] 0 M_I Load [0 0 ] 0
M_I Ifetch [2 4 ] 6 M_I Ifetch [5 1 ] 6
M_I Store [0 0 ] 0 M_I Store [0 0 ] 0
M_I Inv [0 0 ] 0 M_I Inv [0 0 ] 0
M_I L1_Replacement [0 0 ] 0 M_I L1_Replacement [0 0 ] 0
M_I Fwd_GETX [0 0 ] 0 M_I Fwd_GETX [0 0 ] 0
M_I Fwd_GETS [0 0 ] 0 M_I Fwd_GETS [0 0 ] 0
M_I Fwd_GET_INSTR [0 0 ] 0 M_I Fwd_GET_INSTR [0 0 ] 0
M_I WB_Ack [473938 1209377 ] 1683315 M_I WB_Ack [1509181 186134 ] 1695315
SINK_WB_ACK Load [0 0 ] 0 SINK_WB_ACK Load [0 0 ] 0
SINK_WB_ACK Ifetch [0 0 ] 0 SINK_WB_ACK Ifetch [0 0 ] 0
@ -326,107 +326,108 @@ SINK_WB_ACK L1_Replacement [0 0 ] 0
SINK_WB_ACK WB_Ack [0 0 ] 0 SINK_WB_ACK WB_Ack [0 0 ] 0
Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1IcacheMemory
system.l1_cntrl1.L1IcacheMemory_total_misses: 483705 system.l1_cntrl1.L1IcacheMemory_total_misses: 286788
system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 483705 system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 286788
system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100% system.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 483705 100% system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 286788 100%
Cache Stats: system.l1_cntrl1.L1DcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory
system.l1_cntrl1.L1DcacheMemory_total_misses: 1304555 system.l1_cntrl1.L1DcacheMemory_total_misses: 272581
system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1304555 system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 272581
system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.6665% system.l1_cntrl1.L1DcacheMemory_request_type_LD: 47.7344%
system.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.3335% system.l1_cntrl1.L1DcacheMemory_request_type_ST: 52.2656%
system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1304555 100% system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 272581 100%
Cache Stats: system.l2_cntrl0.L2cacheMemory Cache Stats: system.l2_cntrl0.L2cacheMemory
system.l2_cntrl0.L2cacheMemory_total_misses: 226738 system.l2_cntrl0.L2cacheMemory_total_misses: 252589
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 226738 system.l2_cntrl0.L2cacheMemory_total_demand_misses: 252589
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 26.2245% system.l2_cntrl0.L2cacheMemory_request_type_GETS: 31.2052%
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.53822% system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.11428%
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.2372% system.l2_cntrl0.L2cacheMemory_request_type_GETX: 62.6801%
system.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.0003959%
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 226738 100% system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 252589 100%
--- L2Cache --- --- L2Cache ---
- Event Counts - - Event Counts -
L1_GET_INSTR [814757 ] 814757 L1_GET_INSTR [787308 ] 787308
L1_GETS [1386175 ] 1386175 L1_GETS [1430831 ] 1430831
L1_GETX [435076 ] 435076 L1_GETX [423538 ] 423538
L1_UPGRADE [21887 ] 21887 L1_UPGRADE [43595 ] 43595
L1_PUTX [1683315 ] 1683315 L1_PUTX [1695315 ] 1695315
L1_PUTX_old [0 ] 0 L1_PUTX_old [0 ] 0
Fwd_L1_GETX [0 ] 0 Fwd_L1_GETX [0 ] 0
Fwd_L1_GETS [0 ] 0 Fwd_L1_GETS [0 ] 0
Fwd_L1_GET_INSTR [0 ] 0 Fwd_L1_GET_INSTR [0 ] 0
L2_Replacement [95713 ] 95713 L2_Replacement [94722 ] 94722
L2_Replacement_clean [16982 ] 16982 L2_Replacement_clean [12969 ] 12969
Mem_Data [178228 ] 178228 Mem_Data [173216 ] 173216
Mem_Ack [112695 ] 112695 Mem_Ack [107691 ] 107691
WB_Data [24497 ] 24497 WB_Data [47467 ] 47467
WB_Data_clean [663 ] 663 WB_Data_clean [578 ] 578
Ack [1889 ] 1889 Ack [1874 ] 1874
Ack_all [8441 ] 8441 Ack_all [7046 ] 7046
Unblock [24994 ] 24994 Unblock [47798 ] 47798
Unblock_Cancel [0 ] 0 Unblock_Cancel [0 ] 0
Exclusive_Unblock [1732777 ] 1732777 Exclusive_Unblock [1775817 ] 1775817
MEM_Inv [0 ] 0 MEM_Inv [0 ] 0
- Transitions - - Transitions -
NP L1_GET_INSTR [17088 ] 17088 NP L1_GET_INSTR [15439 ] 15439
NP L1_GETS [34471 ] 34471 NP L1_GETS [31028 ] 31028
NP L1_GETX [126669 ] 126669 NP L1_GETX [126749 ] 126749
NP L1_PUTX [0 ] 0 NP L1_PUTX [0 ] 0
NP L1_PUTX_old [0 ] 0 NP L1_PUTX_old [0 ] 0
SS L1_GET_INSTR [797476 ] 797476 SS L1_GET_INSTR [771650 ] 771650
SS L1_GETS [85112 ] 85112 SS L1_GETS [74112 ] 74112
SS L1_GETX [1790 ] 1790 SS L1_GETX [2985 ] 2985
SS L1_UPGRADE [21887 ] 21887 SS L1_UPGRADE [43594 ] 43594
SS L1_PUTX [0 ] 0 SS L1_PUTX [0 ] 0
SS L1_PUTX_old [0 ] 0 SS L1_PUTX_old [0 ] 0
SS L2_Replacement [269 ] 269 SS L2_Replacement [236 ] 236
SS L2_Replacement_clean [8075 ] 8075 SS L2_Replacement_clean [6602 ] 6602
SS MEM_Inv [0 ] 0 SS MEM_Inv [0 ] 0
M L1_GET_INSTR [189 ] 189 M L1_GET_INSTR [213 ] 213
M L1_GETS [1241343 ] 1241343 M L1_GETS [1277661 ] 1277661
M L1_GETX [283101 ] 283101 M L1_GETX [262225 ] 262225
M L1_PUTX [0 ] 0 M L1_PUTX [0 ] 0
M L1_PUTX_old [0 ] 0 M L1_PUTX_old [0 ] 0
M L2_Replacement [95264 ] 95264 M L2_Replacement [94356 ] 94356
M L2_Replacement_clean [8824 ] 8824 M L2_Replacement_clean [6042 ] 6042
M MEM_Inv [0 ] 0 M MEM_Inv [0 ] 0
MT L1_GET_INSTR [4 ] 4 MT L1_GET_INSTR [5 ] 5
MT L1_GETS [24990 ] 24990 MT L1_GETS [47793 ] 47793
MT L1_GETX [23516 ] 23516 MT L1_GETX [31575 ] 31575
MT L1_PUTX [1683315 ] 1683315 MT L1_PUTX [1695315 ] 1695315
MT L1_PUTX_old [0 ] 0 MT L1_PUTX_old [0 ] 0
MT L2_Replacement [180 ] 180 MT L2_Replacement [130 ] 130
MT L2_Replacement_clean [83 ] 83 MT L2_Replacement_clean [325 ] 325
MT MEM_Inv [0 ] 0 MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0 M_I L1_GET_INSTR [1 ] 1
M_I L1_GETS [0 ] 0 M_I L1_GETS [0 ] 0
M_I L1_GETX [0 ] 0 M_I L1_GETX [2 ] 2
M_I L1_UPGRADE [0 ] 0 M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0 M_I L1_PUTX [0 ] 0
M_I L1_PUTX_old [0 ] 0 M_I L1_PUTX_old [0 ] 0
M_I Mem_Ack [112695 ] 112695 M_I Mem_Ack [107691 ] 107691
M_I MEM_Inv [0 ] 0 M_I MEM_Inv [0 ] 0
MT_I L1_GET_INSTR [0 ] 0 MT_I L1_GET_INSTR [0 ] 0
@ -435,9 +436,9 @@ MT_I L1_GETX [0 ] 0
MT_I L1_UPGRADE [0 ] 0 MT_I L1_UPGRADE [0 ] 0
MT_I L1_PUTX [0 ] 0 MT_I L1_PUTX [0 ] 0
MT_I L1_PUTX_old [0 ] 0 MT_I L1_PUTX_old [0 ] 0
MT_I WB_Data [123 ] 123 MT_I WB_Data [93 ] 93
MT_I WB_Data_clean [0 ] 0 MT_I WB_Data_clean [0 ] 0
MT_I Ack_all [57 ] 57 MT_I Ack_all [37 ] 37
MT_I MEM_Inv [0 ] 0 MT_I MEM_Inv [0 ] 0
MCT_I L1_GET_INSTR [0 ] 0 MCT_I L1_GET_INSTR [0 ] 0
@ -446,9 +447,9 @@ MCT_I L1_GETX [0 ] 0
MCT_I L1_UPGRADE [0 ] 0 MCT_I L1_UPGRADE [0 ] 0
MCT_I L1_PUTX [0 ] 0 MCT_I L1_PUTX [0 ] 0
MCT_I L1_PUTX_old [0 ] 0 MCT_I L1_PUTX_old [0 ] 0
MCT_I WB_Data [43 ] 43 MCT_I WB_Data [154 ] 154
MCT_I WB_Data_clean [0 ] 0 MCT_I WB_Data_clean [0 ] 0
MCT_I Ack_all [40 ] 40 MCT_I Ack_all [171 ] 171
I_I L1_GET_INSTR [0 ] 0 I_I L1_GET_INSTR [0 ] 0
I_I L1_GETS [0 ] 0 I_I L1_GETS [0 ] 0
@ -456,8 +457,8 @@ I_I L1_GETX [0 ] 0
I_I L1_UPGRADE [0 ] 0 I_I L1_UPGRADE [0 ] 0
I_I L1_PUTX [0 ] 0 I_I L1_PUTX [0 ] 0
I_I L1_PUTX_old [0 ] 0 I_I L1_PUTX_old [0 ] 0
I_I Ack [1633 ] 1633 I_I Ack [1645 ] 1645
I_I Ack_all [8075 ] 8075 I_I Ack_all [6602 ] 6602
S_I L1_GET_INSTR [0 ] 0 S_I L1_GET_INSTR [0 ] 0
S_I L1_GETS [0 ] 0 S_I L1_GETS [0 ] 0
@ -465,8 +466,8 @@ S_I L1_GETX [0 ] 0
S_I L1_UPGRADE [0 ] 0 S_I L1_UPGRADE [0 ] 0
S_I L1_PUTX [0 ] 0 S_I L1_PUTX [0 ] 0
S_I L1_PUTX_old [0 ] 0 S_I L1_PUTX_old [0 ] 0
S_I Ack [256 ] 256 S_I Ack [229 ] 229
S_I Ack_all [269 ] 269 S_I Ack_all [236 ] 236
S_I MEM_Inv [0 ] 0 S_I MEM_Inv [0 ] 0
ISS L1_GET_INSTR [0 ] 0 ISS L1_GET_INSTR [0 ] 0
@ -476,7 +477,7 @@ ISS L1_PUTX [0 ] 0
ISS L1_PUTX_old [0 ] 0 ISS L1_PUTX_old [0 ] 0
ISS L2_Replacement [0 ] 0 ISS L2_Replacement [0 ] 0
ISS L2_Replacement_clean [0 ] 0 ISS L2_Replacement_clean [0 ] 0
ISS Mem_Data [34471 ] 34471 ISS Mem_Data [31028 ] 31028
ISS MEM_Inv [0 ] 0 ISS MEM_Inv [0 ] 0
IS L1_GET_INSTR [0 ] 0 IS L1_GET_INSTR [0 ] 0
@ -486,7 +487,7 @@ IS L1_PUTX [0 ] 0
IS L1_PUTX_old [0 ] 0 IS L1_PUTX_old [0 ] 0
IS L2_Replacement [0 ] 0 IS L2_Replacement [0 ] 0
IS L2_Replacement_clean [0 ] 0 IS L2_Replacement_clean [0 ] 0
IS Mem_Data [17088 ] 17088 IS Mem_Data [15439 ] 15439
IS MEM_Inv [0 ] 0 IS MEM_Inv [0 ] 0
IM L1_GET_INSTR [0 ] 0 IM L1_GET_INSTR [0 ] 0
@ -496,31 +497,31 @@ IM L1_PUTX [0 ] 0
IM L1_PUTX_old [0 ] 0 IM L1_PUTX_old [0 ] 0
IM L2_Replacement [0 ] 0 IM L2_Replacement [0 ] 0
IM L2_Replacement_clean [0 ] 0 IM L2_Replacement_clean [0 ] 0
IM Mem_Data [126669 ] 126669 IM Mem_Data [126749 ] 126749
IM MEM_Inv [0 ] 0 IM MEM_Inv [0 ] 0
SS_MB L1_GET_INSTR [0 ] 0 SS_MB L1_GET_INSTR [0 ] 0
SS_MB L1_GETS [197 ] 197 SS_MB L1_GETS [185 ] 185
SS_MB L1_GETX [0 ] 0 SS_MB L1_GETX [0 ] 0
SS_MB L1_UPGRADE [0 ] 0 SS_MB L1_UPGRADE [1 ] 1
SS_MB L1_PUTX [0 ] 0 SS_MB L1_PUTX [0 ] 0
SS_MB L1_PUTX_old [0 ] 0 SS_MB L1_PUTX_old [0 ] 0
SS_MB L2_Replacement [0 ] 0 SS_MB L2_Replacement [0 ] 0
SS_MB L2_Replacement_clean [0 ] 0 SS_MB L2_Replacement_clean [0 ] 0
SS_MB Unblock_Cancel [0 ] 0 SS_MB Unblock_Cancel [0 ] 0
SS_MB Exclusive_Unblock [23677 ] 23677 SS_MB Exclusive_Unblock [46579 ] 46579
SS_MB MEM_Inv [0 ] 0 SS_MB MEM_Inv [0 ] 0
MT_MB L1_GET_INSTR [0 ] 0 MT_MB L1_GET_INSTR [0 ] 0
MT_MB L1_GETS [62 ] 62 MT_MB L1_GETS [52 ] 52
MT_MB L1_GETX [0 ] 0 MT_MB L1_GETX [2 ] 2
MT_MB L1_UPGRADE [0 ] 0 MT_MB L1_UPGRADE [0 ] 0
MT_MB L1_PUTX [0 ] 0 MT_MB L1_PUTX [0 ] 0
MT_MB L1_PUTX_old [0 ] 0 MT_MB L1_PUTX_old [0 ] 0
MT_MB L2_Replacement [0 ] 0 MT_MB L2_Replacement [0 ] 0
MT_MB L2_Replacement_clean [0 ] 0 MT_MB L2_Replacement_clean [0 ] 0
MT_MB Unblock_Cancel [0 ] 0 MT_MB Unblock_Cancel [0 ] 0
MT_MB Exclusive_Unblock [1709100 ] 1709100 MT_MB Exclusive_Unblock [1729238 ] 1729238
MT_MB MEM_Inv [0 ] 0 MT_MB MEM_Inv [0 ] 0
M_MB L1_GET_INSTR [0 ] 0 M_MB L1_GET_INSTR [0 ] 0
@ -542,9 +543,9 @@ MT_IIB L1_PUTX [0 ] 0
MT_IIB L1_PUTX_old [0 ] 0 MT_IIB L1_PUTX_old [0 ] 0
MT_IIB L2_Replacement [0 ] 0 MT_IIB L2_Replacement [0 ] 0
MT_IIB L2_Replacement_clean [0 ] 0 MT_IIB L2_Replacement_clean [0 ] 0
MT_IIB WB_Data [24325 ] 24325 MT_IIB WB_Data [47153 ] 47153
MT_IIB WB_Data_clean [663 ] 663 MT_IIB WB_Data_clean [578 ] 578
MT_IIB Unblock [6 ] 6 MT_IIB Unblock [67 ] 67
MT_IIB MEM_Inv [0 ] 0 MT_IIB MEM_Inv [0 ] 0
MT_IB L1_GET_INSTR [0 ] 0 MT_IB L1_GET_INSTR [0 ] 0
@ -555,7 +556,7 @@ MT_IB L1_PUTX [0 ] 0
MT_IB L1_PUTX_old [0 ] 0 MT_IB L1_PUTX_old [0 ] 0
MT_IB L2_Replacement [0 ] 0 MT_IB L2_Replacement [0 ] 0
MT_IB L2_Replacement_clean [0 ] 0 MT_IB L2_Replacement_clean [0 ] 0
MT_IB WB_Data [6 ] 6 MT_IB WB_Data [67 ] 67
MT_IB WB_Data_clean [0 ] 0 MT_IB WB_Data_clean [0 ] 0
MT_IB Unblock_Cancel [0 ] 0 MT_IB Unblock_Cancel [0 ] 0
MT_IB MEM_Inv [0 ] 0 MT_IB MEM_Inv [0 ] 0
@ -568,41 +569,41 @@ MT_SB L1_PUTX [0 ] 0
MT_SB L1_PUTX_old [0 ] 0 MT_SB L1_PUTX_old [0 ] 0
MT_SB L2_Replacement [0 ] 0 MT_SB L2_Replacement [0 ] 0
MT_SB L2_Replacement_clean [0 ] 0 MT_SB L2_Replacement_clean [0 ] 0
MT_SB Unblock [24988 ] 24988 MT_SB Unblock [47731 ] 47731
MT_SB MEM_Inv [0 ] 0 MT_SB MEM_Inv [0 ] 0
Memory controller: system.dir_cntrl0.memBuffer: Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 273984 memory_total_requests: 268092
memory_reads: 178228 memory_reads: 173216
memory_writes: 95756 memory_writes: 94876
memory_refreshes: 4121604 memory_refreshes: 540124
memory_total_request_delays: 24710 memory_total_request_delays: 1022021
memory_delays_per_request: 0.0901877 memory_delays_per_request: 3.8122
memory_delays_in_input_queue: 14 memory_delays_in_input_queue: 40636
memory_delays_behind_head_of_bank_queue: 0 memory_delays_behind_head_of_bank_queue: 7592
memory_delays_stalled_at_head_of_bank_queue: 24696 memory_delays_stalled_at_head_of_bank_queue: 973793
memory_stalls_for_bank_busy: 10948 memory_stalls_for_bank_busy: 964375
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 2078 memory_stalls_for_arbitration: 2145
memory_stalls_for_bus: 11665 memory_stalls_for_bus: 7230
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 0 memory_stalls_for_read_write_turnaround: 35
memory_stalls_for_read_read_turnaround: 5 memory_stalls_for_read_read_turnaround: 8
accesses_per_bank: 8772 9164 8720 8601 8832 8296 9047 8408 8557 8367 8357 9453 8328 8124 8143 7165 8279 8292 8242 8119 8483 8396 8265 8262 8529 8487 8608 9184 9135 8956 10142 8271 accesses_per_bank: 8668 7929 8035 8011 8299 8319 8160 8260 8419 8215 8203 8373 8266 8099 8222 7212 8411 8364 8278 8158 8504 8396 9002 8309 8651 8405 8646 9172 9084 8992 8830 8200
--- Directory --- --- Directory ---
- Event Counts - - Event Counts -
Fetch [178228 ] 178228 Fetch [173216 ] 173216
Data [95756 ] 95756 Data [94876 ] 94876
Memory_Data [178228 ] 178228 Memory_Data [173216 ] 173216
Memory_Ack [95756 ] 95756 Memory_Ack [94876 ] 94876
DMA_READ [0 ] 0 DMA_READ [0 ] 0
DMA_WRITE [0 ] 0 DMA_WRITE [0 ] 0
CleanReplacement [16939 ] 16939 CleanReplacement [12815 ] 12815
- Transitions - - Transitions -
I Fetch [178228 ] 178228 I Fetch [173216 ] 173216
I DMA_READ [0 ] 0 I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0 I DMA_WRITE [0 ] 0
@ -618,20 +619,20 @@ ID_W Memory_Ack [0 ] 0
ID_W DMA_READ [0 ] 0 ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0 ID_W DMA_WRITE [0 ] 0
M Data [95756 ] 95756 M Data [94876 ] 94876
M DMA_READ [0 ] 0 M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0 M DMA_WRITE [0 ] 0
M CleanReplacement [16939 ] 16939 M CleanReplacement [12815 ] 12815
IM Fetch [0 ] 0 IM Fetch [0 ] 0
IM Data [0 ] 0 IM Data [0 ] 0
IM Memory_Data [178228 ] 178228 IM Memory_Data [173216 ] 173216
IM DMA_READ [0 ] 0 IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0 IM DMA_WRITE [0 ] 0
MI Fetch [0 ] 0 MI Fetch [0 ] 0
MI Data [0 ] 0 MI Data [0 ] 0
MI Memory_Ack [95756 ] 95756 MI Memory_Ack [94876 ] 94876
MI DMA_READ [0 ] 0 MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0 MI DMA_WRITE [0 ] 0

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 22 2012 08:55:10 gem5 compiled Sep 10 2012 12:26:53
gem5 started Jul 22 2012 08:55:16 gem5 started Sep 10 2012 12:26:58
gem5 executing on ribera.cs.wisc.edu gem5 executing on ribera.cs.wisc.edu
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
warning: add_child('terminal'): child 'terminal' already has parent warning: add_child('terminal'): child 'terminal' already has parent
@ -12,4 +12,4 @@ Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5305568377500 because m5_exit instruction encountered Exiting @ tick 5205006924000 because m5_exit instruction encountered

192
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -1,77 +1,77 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 5.309130 # Number of seconds simulated sim_seconds 5.205007 # Number of seconds simulated
sim_ticks 5309130431000 # Number of ticks simulated sim_ticks 5205006924000 # Number of ticks simulated
final_tick 5309130431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 252383 # Simulator instruction rate (inst/s) host_inst_rate 145510 # Simulator instruction rate (inst/s)
host_op_rate 484244 # Simulator op (including micro ops) rate (op/s) host_op_rate 279202 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12393223655 # Simulator tick rate (ticks/s) host_tick_rate 7001191594 # Simulator tick rate (ticks/s)
host_mem_usage 461792 # Number of bytes of host memory used host_mem_usage 505404 # Number of bytes of host memory used
host_seconds 428.39 # Real time elapsed on the host host_seconds 743.45 # Real time elapsed on the host
sim_insts 108118332 # Number of instructions simulated sim_insts 108178578 # Number of instructions simulated
sim_ops 207445228 # Number of ops (including micro ops) simulated sim_ops 207571464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 107024 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 173936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 51696 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 833139344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 870514880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 64776128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 69689841 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 119080 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 49504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 55640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 193794504 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 157070368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 32074945 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 27207776 # Number of bytes read from this memory
system.physmem.bytes_read::total 1124153521 # Number of bytes read from this memory system.physmem.bytes_read::total 1124848049 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 833139344 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 870514880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 193794504 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 157070368 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1026933848 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1027585248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 44442078 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 48549302 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 25482673 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 21364054 # Number of bytes written to this memory
system.physmem.bytes_written::total 72915871 # Number of bytes written to this memory system.physmem.bytes_written::total 72904476 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 13378 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 21742 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 6462 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 104142418 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 108814360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 11379014 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 12175547 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 14885 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 6188 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 6955 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 24224313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 19633796 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 4791752 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 4005942 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144579988 # Number of read requests responded to by this memory system.physmem.num_reads::total 144671709 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 6585171 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 7160367 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 3512759 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2936343 # Number of write requests responded to by this memory
system.physmem.num_writes::total 10144668 # Number of write requests responded to by this memory system.physmem.num_writes::total 10143448 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6623 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 20158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 33417 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 9737 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 156925763 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 167245672 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12200892 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 13389001 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 22429 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 9511 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 10480 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 36502118 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 30176784 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 6041469 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 5227231 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 211739669 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 216108848 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 156925763 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 167245672 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 36502118 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 30176784 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 193427881 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 197422456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 563389 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 8370877 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 9327423 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 4799783 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 4104520 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13734052 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 14006605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 570011 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 20158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 33417 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 9740 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 156925763 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 167245672 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 20571769 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 22716424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 22429 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 9511 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 10480 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 36502118 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 30176784 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 10841251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 9331751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 225473721 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 230115453 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -114,52 +114,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.numCycles 10617406972 # number of cpu cycles simulated system.cpu0.numCycles 10410013848 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 89456821 # Number of instructions committed system.cpu0.committedInsts 93129090 # Number of instructions committed
system.cpu0.committedOps 172956710 # Number of ops (including micro ops) committed system.cpu0.committedOps 179514856 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 163049245 # Number of integer alu accesses system.cpu0.num_int_alu_accesses 169447650 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured system.cpu0.num_func_calls 0 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 15979073 # number of instructions that are conditional controls system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls
system.cpu0.num_int_insts 163049245 # number of integer instructions system.cpu0.num_int_insts 169447650 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 506406726 # number of times the integer registers were read system.cpu0.num_int_register_reads 526613811 # number of times the integer registers were read
system.cpu0.num_int_register_writes 269974282 # number of times the integer registers were written system.cpu0.num_int_register_writes 279904453 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 18821806 # number of memory refs system.cpu0.num_mem_refs 20197632 # number of memory refs
system.cpu0.num_load_insts 12224477 # Number of load instructions system.cpu0.num_load_insts 13022518 # Number of load instructions
system.cpu0.num_store_insts 6597329 # Number of store instructions system.cpu0.num_store_insts 7175114 # Number of store instructions
system.cpu0.num_idle_cycles 9900769036.140667 # Number of idle cycles system.cpu0.num_idle_cycles 9667682114.054142 # Number of idle cycles
system.cpu0.num_busy_cycles 716637935.859333 # Number of busy cycles system.cpu0.num_busy_cycles 742331733.945857 # Number of busy cycles
system.cpu0.not_idle_fraction 0.067497 # Percentage of non-idle cycles system.cpu0.not_idle_fraction 0.071309 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.932503 # Percentage of idle cycles system.cpu0.idle_fraction 0.928691 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.numCycles 10618260862 # number of cpu cycles simulated system.cpu1.numCycles 10407072224 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 18661511 # Number of instructions committed system.cpu1.committedInsts 15049488 # Number of instructions committed
system.cpu1.committedOps 34488518 # Number of ops (including micro ops) committed system.cpu1.committedOps 28056608 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 33823915 # Number of integer alu accesses system.cpu1.num_int_alu_accesses 27537877 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured system.cpu1.num_func_calls 0 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2426468 # number of instructions that are conditional controls system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls
system.cpu1.num_int_insts 33823915 # number of integer instructions system.cpu1.num_int_insts 27537877 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 103356389 # number of times the integer registers were read system.cpu1.num_int_register_reads 83543948 # number of times the integer registers were read
system.cpu1.num_int_register_writes 49288010 # number of times the integer registers were written system.cpu1.num_int_register_writes 39599816 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 8339462 # number of memory refs system.cpu1.num_mem_refs 6975131 # number of memory refs
system.cpu1.num_load_insts 4801557 # Number of load instructions system.cpu1.num_load_insts 4014934 # Number of load instructions
system.cpu1.num_store_insts 3537905 # Number of store instructions system.cpu1.num_store_insts 2960197 # Number of store instructions
system.cpu1.num_idle_cycles 10461852949.262030 # Number of idle cycles system.cpu1.num_idle_cycles 10279839396.425842 # Number of idle cycles
system.cpu1.num_busy_cycles 156407912.737971 # Number of busy cycles system.cpu1.num_busy_cycles 127232827.574158 # Number of busy cycles
system.cpu1.not_idle_fraction 0.014730 # Percentage of non-idle cycles system.cpu1.not_idle_fraction 0.012226 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.985270 # Percentage of idle cycles system.cpu1.idle_fraction 0.987774 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
View file

@ -26,7 +26,7 @@ Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0 Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes) PID hash table entries: 512 (order: 9, 4096 bytes)
Marking TSC unstable due to TSCs unsynchronized Marking TSC unstable due to TSCs unsynchronized
time.c: Detected 1999.999 MHz processor. time.c: Detected 2000.001 MHz processor.
Console: colour dummy device 80x25 Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0] console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes) Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@ -39,7 +39,7 @@ CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line)
Freeing SMP alternatives: 34k freed Freeing SMP alternatives: 34k freed
Using local APIC timer interrupts. Using local APIC timer interrupts.
result 7812491 result 7812503
Detected 7.812 MHz APIC timer. Detected 7.812 MHz APIC timer.
Booting processor 1/2 APIC 0x1 Booting processor 1/2 APIC 0x1
Initializing CPU#1 Initializing CPU#1
@ -125,9 +125,9 @@ oprofile: using timer interrupt.
TCP cubic registered TCP cubic registered
NET: Registered protocol family 1 NET: Registered protocol family 1
NET: Registered protocol family 10 NET: Registered protocol family 10
input: PS/2 Generic Mouse as /class/input/input1
IPv6 over IPv4 tunneling driver IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17 NET: Registered protocol family 17
input: PS/2 Generic Mouse as /class/input/input1
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
VFS: Mounted root (ext2 filesystem). VFS: Mounted root (ext2 filesystem).
Freeing unused kernel memory: 248k freed Freeing unused kernel memory: 248k freed

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -78,7 +78,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -121,9 +121,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -132,6 +132,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -189,6 +190,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.L1DcacheMemory dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory icache=system.l1_cntrl0.L1IcacheMemory
@ -234,6 +236,7 @@ tagArrayBanks=1
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -358,6 +361,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

169
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
View file

@ -1,4 +1,4 @@
Real time: Jul/10/2012 17:45:14 Real time: Sep/09/2012 13:38:15
Profiler Stats Profiler Stats
-------------- --------------
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0 Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.54 Virtual_time_in_seconds: 0.59
Virtual_time_in_minutes: 0.009 Virtual_time_in_minutes: 0.00983333
Virtual_time_in_hours: 0.00015 Virtual_time_in_hours: 0.000163889
Virtual_time_in_days: 6.25e-06 Virtual_time_in_days: 6.8287e-06
Ruby_current_time: 231701 Ruby_current_time: 113627
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 231701 Ruby_cycles: 113627
mbytes_resident: 46.2734 mbytes_resident: 52.8594
mbytes_total: 228.938 mbytes_total: 266.098
resident_ratio: 0.20214 resident_ratio: 0.198661
ruby_cycles_executed: [ 231702 ] ruby_cycles_executed: [ 113628 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -30,17 +30,17 @@ Directory-0:0
Busy Bank Count:0 Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 2 max: 326 count: 8464 average: 26.3749 | standard deviation: 59.7716 | 0 7082 0 0 0 0 0 0 0 0 21 3 180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 7 156 141 316 165 138 16 4 6 35 30 41 24 40 3 1 2 4 3 0 2 2 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 3 0 0 0 0 0 0 0 1 0 0 1 20 0 3 2 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency: [binsize: 1 max: 122 count: 8448 average: 12.4502 | standard deviation: 24.781 | 0 0 7066 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 1 1 2 181 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 3 1 776 93 43 166 13 3 9 0 0 2 1 0 1 0 0 1 0 1 1 1 0 0 0 0 3 0 0 1 0 0 5 0 0 0 1 0 0 0 0 1 0 0 25 0 0 2 0 0 1 0 0 1 ]
miss_latency_LD: [binsize: 2 max: 326 count: 1185 average: 65.011 | standard deviation: 81.2899 | 0 660 0 0 0 0 0 0 0 0 3 2 95 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 55 33 124 68 56 0 2 3 11 11 7 12 19 3 1 1 3 2 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 ] miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 29.3643 | standard deviation: 33.3419 | 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 1 95 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 298 27 9 57 5 0 4 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 3 0 0 0 0 0 3 0 0 0 1 0 0 0 0 1 0 0 6 ]
miss_latency_ST: [binsize: 2 max: 321 count: 865 average: 39.3988 | standard deviation: 76.4664 | 0 654 0 0 0 0 0 0 0 0 17 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 17 11 29 14 36 1 0 1 1 6 23 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 18 0 2 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 1 max: 122 count: 865 average: 17.7642 | standard deviation: 30.4859 | 0 0 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 93 8 1 36 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 0 2 0 0 1 0 0 1 ]
miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.4804 | standard deviation: 48.2606 | 0 5768 0 0 0 0 0 0 0 0 1 1 59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 84 97 163 83 46 15 2 2 23 13 11 12 20 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH: [binsize: 1 max: 101 count: 6400 average: 8.60547 | standard deviation: 20.2068 | 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 3 1 385 58 33 73 8 3 3 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 2 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7082 average: 2 | standard deviation: 0 | 0 0 7082 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 7066 average: 2 | standard deviation: 0 | 0 0 7066 ]
miss_latency_L2Cache: [binsize: 1 max: 25 count: 204 average: 24.5441 | standard deviation: 1.24963 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 2 1 1 179 ] miss_latency_L2Cache: [binsize: 1 max: 25 count: 204 average: 24.5931 | standard deviation: 1.18696 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 1 1 2 181 ]
miss_latency_Directory: [binsize: 2 max: 326 count: 1178 average: 173.231 | standard deviation: 22.9712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 7 156 141 316 165 138 16 4 6 35 30 41 24 40 3 1 2 4 3 0 2 2 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 3 0 0 0 0 0 0 0 1 0 0 1 20 0 3 2 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_Directory: [binsize: 1 max: 122 count: 1178 average: 73.0306 | standard deviation: 7.25919 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 3 1 776 93 43 166 13 3 9 0 0 2 1 0 1 0 0 1 0 1 1 1 0 0 0 0 3 0 0 1 0 0 5 0 0 0 1 0 0 0 0 1 0 0 25 0 0 2 0 0 1 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -49,17 +49,17 @@ imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 70 count: 1 average: 70 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1177 imcomplete_dir_Times: 1177
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 658 average: 2 | standard deviation: 0 | 0 0 658 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 25 count: 100 average: 24.83 | standard deviation: 0.771984 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 95 ] miss_latency_LD_L2Cache: [binsize: 1 max: 25 count: 100 average: 24.86 | standard deviation: 0.6742 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 1 95 ]
miss_latency_LD_Directory: [binsize: 2 max: 326 count: 425 average: 172.318 | standard deviation: 18.6969 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 55 33 124 68 56 0 2 3 11 11 7 12 19 3 1 1 3 2 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 ] miss_latency_LD_Directory: [binsize: 1 max: 113 count: 425 average: 72.7906 | standard deviation: 6.46854 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 298 27 9 57 5 0 4 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 3 0 0 0 0 0 3 0 0 0 1 0 0 0 0 1 0 0 6 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 654 average: 2 | standard deviation: 0 | 0 0 654 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 654 average: 2 | standard deviation: 0 | 0 0 654 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 25 count: 43 average: 23.4186 | standard deviation: 1.98206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 26 ] miss_latency_ST_L2Cache: [binsize: 1 max: 25 count: 43 average: 23.4186 | standard deviation: 1.98206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 26 ]
miss_latency_ST_Directory: [binsize: 2 max: 321 count: 168 average: 189.077 | standard deviation: 46.5714 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 17 11 29 14 36 1 0 1 1 6 23 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 18 0 2 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_Directory: [binsize: 1 max: 122 count: 168 average: 77.6845 | standard deviation: 14.6277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 93 8 1 36 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 0 2 0 0 1 0 0 1 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5754 average: 2 | standard deviation: 0 | 0 0 5754 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 25 count: 61 average: 24.8689 | standard deviation: 0.645497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 58 ] miss_latency_IFETCH_L2Cache: [binsize: 1 max: 25 count: 61 average: 24.9836 | standard deviation: 0.129099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 60 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 276 count: 585 average: 169.344 | standard deviation: 10.0739 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 84 97 163 83 46 15 2 2 23 13 11 12 20 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH_Directory: [binsize: 1 max: 101 count: 585 average: 71.8684 | standard deviation: 2.64866 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 3 1 385 58 33 73 8 3 3 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 2 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -91,11 +91,11 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 12976 page_reclaims: 10608
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
block_outputs: 0 block_outputs: 112
Network Stats Network Stats
------------- -------------
@ -106,32 +106,28 @@ total_msg_count_ResponseL2hit_Data: 612 44064
total_msg_count_Response_Control: 3 24 total_msg_count_Response_Control: 3 24
total_msg_count_Writeback_Data: 4749 341928 total_msg_count_Writeback_Data: 4749 341928
total_msg_count_Writeback_Control: 2901 23208 total_msg_count_Writeback_Control: 2901 23208
total_msg_count_Persistent_Control: 240 1920 total_msgs: 19530 total_bytes: 725520
total_msgs: 19770 total_bytes: 727440
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.81473 links_utilized_percent_switch_0: 5.72201
links_utilized_percent_switch_0_link_0: 2.69291 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 5.47361 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.93654 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 5.97041 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.12213 links_utilized_percent_switch_1: 4.31852
links_utilized_percent_switch_1_link_0: 2.93654 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 5.97041 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 1.30772 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 2.66662 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
@ -140,33 +136,30 @@ links_utilized_percent_switch_1: 2.12213
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 1.6039 links_utilized_percent_switch_2: 3.26177
links_utilized_percent_switch_2_link_0: 0.919936 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 1.85827 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.28786 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 4.66526 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3 switch_3_inlinks: 3
switch_3_outlinks: 3 switch_3_outlinks: 3
links_utilized_percent_switch_3: 2.18025 links_utilized_percent_switch_3: 4.4341
links_utilized_percent_switch_3_link_0: 2.68428 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_0: 5.47361 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_1: 2.93654 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_1: 5.97041 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0.919936 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_2: 1.85827 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 646 system.l1_cntrl0.L1IcacheMemory_total_misses: 646
@ -193,8 +186,8 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
--- L1Cache --- --- L1Cache ---
- Event Counts - - Event Counts -
Load [1185 ] 1185 Load [1183 ] 1183
Ifetch [6414 ] 6414 Ifetch [6400 ] 6400
Store [865 ] 865 Store [865 ] 865
Atomic [0 ] 0 Atomic [0 ] 0
L1_Replacement [1364 ] 1364 L1_Replacement [1364 ] 1364
@ -212,8 +205,8 @@ Transient_Local_GETS_Last_Token [0 ] 0
Persistent_GETX [0 ] 0 Persistent_GETX [0 ] 0
Persistent_GETS [0 ] 0 Persistent_GETS [0 ] 0
Persistent_GETS_Last_Token [0 ] 0 Persistent_GETS_Last_Token [0 ] 0
Own_Lock_or_Unlock [40 ] 40 Own_Lock_or_Unlock [0 ] 0
Request_Timeout [20 ] 20 Request_Timeout [0 ] 0
Use_TimeoutStarverX [0 ] 0 Use_TimeoutStarverX [0 ] 0
Use_TimeoutStarverS [0 ] 0 Use_TimeoutStarverS [0 ] 0
Use_TimeoutNoStarvers [1220 ] 1220 Use_TimeoutNoStarvers [1220 ] 1220
@ -297,8 +290,8 @@ O Persistent_GETS [0 ] 0
O Persistent_GETS_Last_Token [0 ] 0 O Persistent_GETS_Last_Token [0 ] 0
O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock [0 ] 0
M Load [186 ] 186 M Load [184 ] 184
M Ifetch [3322 ] 3322 M Ifetch [3308 ] 3308
M Store [33 ] 33 M Store [33 ] 33
M Atomic [0 ] 0 M Atomic [0 ] 0
M L1_Replacement [945 ] 945 M L1_Replacement [945 ] 945
@ -308,7 +301,7 @@ M Transient_GETS [0 ] 0
M Transient_Local_GETS [0 ] 0 M Transient_Local_GETS [0 ] 0
M Persistent_GETX [0 ] 0 M Persistent_GETX [0 ] 0
M Persistent_GETS [0 ] 0 M Persistent_GETS [0 ] 0
M Own_Lock_or_Unlock [3 ] 3 M Own_Lock_or_Unlock [0 ] 0
MM Load [220 ] 220 MM Load [220 ] 220
MM Ifetch [0 ] 0 MM Ifetch [0 ] 0
@ -321,7 +314,7 @@ MM Transient_GETS [0 ] 0
MM Transient_Local_GETS [0 ] 0 MM Transient_Local_GETS [0 ] 0
MM Persistent_GETX [0 ] 0 MM Persistent_GETX [0 ] 0
MM Persistent_GETS [0 ] 0 MM Persistent_GETS [0 ] 0
MM Own_Lock_or_Unlock [17 ] 17 MM Own_Lock_or_Unlock [0 ] 0
M_W Load [80 ] 80 M_W Load [80 ] 80
M_W Ifetch [2115 ] 2115 M_W Ifetch [2115 ] 2115
@ -375,8 +368,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0
IM Persistent_GETX [0 ] 0 IM Persistent_GETX [0 ] 0
IM Persistent_GETS [0 ] 0 IM Persistent_GETS [0 ] 0
IM Persistent_GETS_Last_Token [0 ] 0 IM Persistent_GETS_Last_Token [0 ] 0
IM Own_Lock_or_Unlock [17 ] 17 IM Own_Lock_or_Unlock [0 ] 0
IM Request_Timeout [17 ] 17 IM Request_Timeout [0 ] 0
SM Load [0 ] 0 SM Load [0 ] 0
SM Ifetch [0 ] 0 SM Ifetch [0 ] 0
@ -438,8 +431,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0
IS Persistent_GETX [0 ] 0 IS Persistent_GETX [0 ] 0
IS Persistent_GETS [0 ] 0 IS Persistent_GETS [0 ] 0
IS Persistent_GETS_Last_Token [0 ] 0 IS Persistent_GETS_Last_Token [0 ] 0
IS Own_Lock_or_Unlock [3 ] 3 IS Own_Lock_or_Unlock [0 ] 0
IS Request_Timeout [3 ] 3 IS Request_Timeout [0 ] 0
I_L Load [0 ] 0 I_L Load [0 ] 0
I_L Ifetch [0 ] 0 I_L Ifetch [0 ] 0
@ -573,10 +566,10 @@ Data_Owner [0 ] 0
Data_All_Tokens [0 ] 0 Data_All_Tokens [0 ] 0
Ack [0 ] 0 Ack [0 ] 0
Ack_All_Tokens [0 ] 0 Ack_All_Tokens [0 ] 0
Persistent_GETX [17 ] 17 Persistent_GETX [0 ] 0
Persistent_GETS [3 ] 3 Persistent_GETS [0 ] 0
Persistent_GETS_Last_Token [0 ] 0 Persistent_GETS_Last_Token [0 ] 0
Own_Lock_or_Unlock [20 ] 20 Own_Lock_or_Unlock [0 ] 0
- Transitions - - Transitions -
NP L1_GETS [1010 ] 1010 NP L1_GETS [1010 ] 1010
@ -595,7 +588,7 @@ NP Ack [0 ] 0
NP Persistent_GETX [0 ] 0 NP Persistent_GETX [0 ] 0
NP Persistent_GETS [0 ] 0 NP Persistent_GETS [0 ] 0
NP Persistent_GETS_Last_Token [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0
NP Own_Lock_or_Unlock [20 ] 20 NP Own_Lock_or_Unlock [0 ] 0
I L1_GETS [0 ] 0 I L1_GETS [0 ] 0
I L1_GETS_Last_Token [0 ] 0 I L1_GETS_Last_Token [0 ] 0
@ -684,8 +677,8 @@ I_L Data_Shared [0 ] 0
I_L Data_Owner [0 ] 0 I_L Data_Owner [0 ] 0
I_L Data_All_Tokens [0 ] 0 I_L Data_All_Tokens [0 ] 0
I_L Ack [0 ] 0 I_L Ack [0 ] 0
I_L Persistent_GETX [17 ] 17 I_L Persistent_GETX [0 ] 0
I_L Persistent_GETS [3 ] 3 I_L Persistent_GETS [0 ] 0
I_L Own_Lock_or_Unlock [0 ] 0 I_L Own_Lock_or_Unlock [0 ] 0
S_L L1_GETS [0 ] 0 S_L L1_GETS [0 ] 0
@ -713,28 +706,28 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1407 memory_total_requests: 1407
memory_reads: 1178 memory_reads: 1178
memory_writes: 229 memory_writes: 229
memory_refreshes: 483 memory_refreshes: 789
memory_total_request_delays: 396 memory_total_request_delays: 323
memory_delays_per_request: 0.28145 memory_delays_per_request: 0.229566
memory_delays_in_input_queue: 112 memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 0 memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 284 memory_delays_stalled_at_head_of_bank_queue: 323
memory_stalls_for_bank_busy: 58 memory_stalls_for_bank_busy: 81
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 16 memory_stalls_for_arbitration: 19
memory_stalls_for_bus: 208 memory_stalls_for_bus: 213
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 2 memory_stalls_for_read_write_turnaround: 10
memory_stalls_for_read_read_turnaround: 0 memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 41 54 102 33 16 20 22 32 34 53 50 40 31 40 21 21 21 28 38 89 22 31 23 32 72 95 141 15 53 accesses_per_bank: 75 17 45 41 54 102 33 16 20 22 32 34 53 50 40 31 40 21 21 21 28 38 89 22 31 23 32 72 95 141 15 53
--- Directory --- --- Directory ---
- Event Counts - - Event Counts -
GETX [488 ] 488 GETX [278 ] 278
GETS [1093 ] 1093 GETS [1034 ] 1034
Lockdown [20 ] 20 Lockdown [0 ] 0
Unlockdown [20 ] 20 Unlockdown [0 ] 0
Own_Lock_or_Unlock [0 ] 0 Own_Lock_or_Unlock [0 ] 0
Own_Lock_or_Unlock_Tokens [0 ] 0 Own_Lock_or_Unlock_Tokens [0 ] 0
Data_Owner [9 ] 9 Data_Owner [9 ] 9
@ -767,7 +760,7 @@ O DMA_WRITE_All_Tokens [0 ] 0
NO GETX [17 ] 17 NO GETX [17 ] 17
NO GETS [0 ] 0 NO GETS [0 ] 0
NO Lockdown [6 ] 6 NO Lockdown [0 ] 0
NO Unlockdown [0 ] 0 NO Unlockdown [0 ] 0
NO Own_Lock_or_Unlock [0 ] 0 NO Own_Lock_or_Unlock [0 ] 0
NO Own_Lock_or_Unlock_Tokens [0 ] 0 NO Own_Lock_or_Unlock_Tokens [0 ] 0
@ -782,7 +775,7 @@ NO DMA_WRITE [0 ] 0
L GETX [0 ] 0 L GETX [0 ] 0
L GETS [0 ] 0 L GETS [0 ] 0
L Lockdown [0 ] 0 L Lockdown [0 ] 0
L Unlockdown [20 ] 20 L Unlockdown [0 ] 0
L Own_Lock_or_Unlock [0 ] 0 L Own_Lock_or_Unlock [0 ] 0
L Own_Lock_or_Unlock_Tokens [0 ] 0 L Own_Lock_or_Unlock_Tokens [0 ] 0
L Data_Owner [0 ] 0 L Data_Owner [0 ] 0
@ -794,8 +787,8 @@ L DMA_READ [0 ] 0
L DMA_WRITE [0 ] 0 L DMA_WRITE [0 ] 0
L DMA_WRITE_All_Tokens [0 ] 0 L DMA_WRITE_All_Tokens [0 ] 0
O_W GETX [303 ] 303 O_W GETX [93 ] 93
O_W GETS [83 ] 83 O_W GETS [24 ] 24
O_W Lockdown [0 ] 0 O_W Lockdown [0 ] 0
O_W Unlockdown [0 ] 0 O_W Unlockdown [0 ] 0
O_W Own_Lock_or_Unlock [0 ] 0 O_W Own_Lock_or_Unlock [0 ] 0
@ -839,7 +832,7 @@ L_NO_W Data_All_Tokens [0 ] 0
L_NO_W Ack_Owner [0 ] 0 L_NO_W Ack_Owner [0 ] 0
L_NO_W Tokens [0 ] 0 L_NO_W Tokens [0 ] 0
L_NO_W Ack_All_Tokens [0 ] 0 L_NO_W Ack_All_Tokens [0 ] 0
L_NO_W Memory_Data [14 ] 14 L_NO_W Memory_Data [0 ] 0
L_NO_W DMA_READ [0 ] 0 L_NO_W DMA_READ [0 ] 0
L_NO_W DMA_WRITE [0 ] 0 L_NO_W DMA_WRITE [0 ] 0
L_NO_W DMA_WRITE_All_Tokens [0 ] 0 L_NO_W DMA_WRITE_All_Tokens [0 ] 0
@ -880,7 +873,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0
NO_W GETX [0 ] 0 NO_W GETX [0 ] 0
NO_W GETS [0 ] 0 NO_W GETS [0 ] 0
NO_W Lockdown [14 ] 14 NO_W Lockdown [0 ] 0
NO_W Unlockdown [0 ] 0 NO_W Unlockdown [0 ] 0
NO_W Own_Lock_or_Unlock [0 ] 0 NO_W Own_Lock_or_Unlock [0 ] 0
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
@ -889,7 +882,7 @@ NO_W Data_All_Tokens [0 ] 0
NO_W Ack_Owner [0 ] 0 NO_W Ack_Owner [0 ] 0
NO_W Tokens [0 ] 0 NO_W Tokens [0 ] 0
NO_W Ack_All_Tokens [0 ] 0 NO_W Ack_All_Tokens [0 ] 0
NO_W Memory_Data [1164 ] 1164 NO_W Memory_Data [1178 ] 1178
NO_W DMA_READ [0 ] 0 NO_W DMA_READ [0 ] 0
NO_W DMA_WRITE [0 ] 0 NO_W DMA_WRITE [0 ] 0
NO_W DMA_WRITE_All_Tokens [0 ] 0 NO_W DMA_WRITE_All_Tokens [0 ] 0

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 16:58:46 gem5 compiled Sep 9 2012 13:38:07
gem5 started Aug 13 2012 18:10:55 gem5 started Sep 9 2012 13:38:15
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Hello world! Hello world!
Exiting @ tick 231701 because target called exit() Exiting @ tick 113627 because target called exit()

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -78,7 +78,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -121,9 +121,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -132,6 +132,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -189,6 +190,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.L1DcacheMemory dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory icache=system.l1_cntrl0.L1IcacheMemory
@ -234,6 +236,7 @@ tagArrayBanks=1
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -358,6 +361,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

96
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
View file

@ -1,4 +1,4 @@
Real time: Jul/10/2012 17:45:47 Real time: Sep/09/2012 13:38:15
Profiler Stats Profiler Stats
-------------- --------------
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0 Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.42 Virtual_time_in_seconds: 0.43
Virtual_time_in_minutes: 0.007 Virtual_time_in_minutes: 0.00716667
Virtual_time_in_hours: 0.000116667 Virtual_time_in_hours: 0.000119444
Virtual_time_in_days: 4.86111e-06 Virtual_time_in_days: 4.97685e-06
Ruby_current_time: 87899 Ruby_current_time: 43073
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 87899 Ruby_cycles: 43073
mbytes_resident: 44.4727 mbytes_resident: 51.0586
mbytes_total: 227.578 mbytes_total: 264.82
resident_ratio: 0.195434 resident_ratio: 0.192819
ruby_cycles_executed: [ 87900 ] ruby_cycles_executed: [ 43074 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -34,13 +34,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 2 max: 307 count: 3294 average: 25.6846 | standard deviation: 58.8214 | 0 2776 0 0 0 0 0 0 0 0 6 2 62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 58 48 98 72 79 0 1 2 13 9 10 7 26 0 1 0 0 1 1 0 1 1 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency: [binsize: 1 max: 113 count: 3294 average: 12.0762 | standard deviation: 24.317 | 0 0 2776 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2 0 62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 2 1 300 33 9 62 5 0 7 3 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 2 0 0 0 0 0 6 ]
miss_latency_LD: [binsize: 2 max: 307 count: 415 average: 65.2795 | standard deviation: 81.9739 | 0 233 0 0 0 0 0 0 0 0 0 1 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 16 14 37 32 18 0 0 0 9 2 2 2 8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 1 max: 113 count: 415 average: 29.3398 | standard deviation: 33.6061 | 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 99 14 1 18 2 0 4 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 3 ]
miss_latency_ST: [binsize: 2 max: 307 count: 294 average: 34.5782 | standard deviation: 69.4748 | 0 228 0 0 0 0 0 0 0 0 6 1 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 15 8 5 0 0 0 0 1 1 0 5 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 1 max: 113 count: 294 average: 15.6905 | standard deviation: 27.6304 | 0 0 228 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 1 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 0 32 2 0 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 ]
miss_latency_IFETCH: [binsize: 2 max: 277 count: 2585 average: 18.3164 | standard deviation: 49.7019 | 0 2315 0 0 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 36 29 46 32 56 0 1 2 4 6 7 5 13 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH: [binsize: 1 max: 101 count: 2585 average: 8.89362 | standard deviation: 20.6535 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 1 169 17 8 36 3 0 2 2 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2776 average: 2 | standard deviation: 0 | 0 0 2776 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 2776 average: 2 | standard deviation: 0 | 0 0 2776 ]
miss_latency_L2Cache: [binsize: 1 max: 25 count: 70 average: 24.6 | standard deviation: 1.16096 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2 0 62 ] miss_latency_L2Cache: [binsize: 1 max: 25 count: 70 average: 24.6 | standard deviation: 1.16096 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2 0 62 ]
miss_latency_Directory: [binsize: 2 max: 307 count: 448 average: 172.614 | standard deviation: 19.1957 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 58 48 98 72 79 0 1 2 13 9 10 7 26 0 1 0 0 1 1 0 1 1 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 2 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_Directory: [binsize: 1 max: 113 count: 448 average: 72.5558 | standard deviation: 5.90738 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 2 1 300 33 9 62 5 0 7 3 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 2 0 0 0 0 0 6 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -49,17 +49,17 @@ imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 70 count: 1 average: 70 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 447 imcomplete_dir_Times: 447
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 25 count: 33 average: 24.9394 | standard deviation: 0.353553 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 32 ] miss_latency_LD_L2Cache: [binsize: 1 max: 25 count: 33 average: 24.9394 | standard deviation: 0.353553 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 32 ]
miss_latency_LD_Directory: [binsize: 2 max: 307 count: 149 average: 173.168 | standard deviation: 20.2876 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 16 14 37 32 18 0 0 0 9 2 2 2 8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_Directory: [binsize: 1 max: 113 count: 149 average: 73.0671 | standard deviation: 7.2866 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 99 14 1 18 2 0 4 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 3 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 228 average: 2 | standard deviation: 0 | 0 0 228 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 228 average: 2 | standard deviation: 0 | 0 0 228 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 25 count: 14 average: 23.1429 | standard deviation: 2 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 1 0 7 ] miss_latency_ST_L2Cache: [binsize: 1 max: 25 count: 14 average: 23.1429 | standard deviation: 2 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 1 0 7 ]
miss_latency_ST_Directory: [binsize: 2 max: 307 count: 52 average: 180.5 | standard deviation: 35.1816 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 15 8 5 0 0 0 0 1 1 0 5 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_Directory: [binsize: 1 max: 113 count: 52 average: 73.7115 | standard deviation: 9.96956 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 0 32 2 0 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 25 count: 23 average: 25 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ] miss_latency_IFETCH_L2Cache: [binsize: 1 max: 25 count: 23 average: 25 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 277 count: 247 average: 170.619 | standard deviation: 12.1654 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 36 29 46 32 56 0 1 2 4 6 7 5 13 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH_Directory: [binsize: 1 max: 101 count: 247 average: 72.004 | standard deviation: 3.18086 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 1 169 17 8 36 3 0 2 2 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -91,11 +91,11 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 12519 page_reclaims: 10155
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
block_outputs: 0 block_outputs: 80
Network Stats Network Stats
------------- -------------
@ -110,9 +110,9 @@ total_msgs: 7326 total_bytes: 270576
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.75856 links_utilized_percent_switch_0: 5.6294
links_utilized_percent_switch_0_link_0: 2.65248 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 5.4129 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.86465 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 5.84589 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1
@ -122,9 +122,9 @@ links_utilized_percent_switch_0: 2.75856
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.05975 links_utilized_percent_switch_1: 4.20333
links_utilized_percent_switch_1_link_0: 2.86465 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 5.84589 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 1.25485 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 2.56077 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 518 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 518 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
@ -136,9 +136,9 @@ links_utilized_percent_switch_1: 2.05975
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 1.59473 links_utilized_percent_switch_2: 3.25436
links_utilized_percent_switch_2_link_0: 0.895915 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 1.82829 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.29354 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 4.68043 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Request_Control: 454 3632 [ 0 0 454 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Request_Control: 454 3632 [ 0 0 454 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1
@ -147,10 +147,10 @@ links_utilized_percent_switch_2: 1.59473
switch_3_inlinks: 3 switch_3_inlinks: 3
switch_3_outlinks: 3 switch_3_outlinks: 3
links_utilized_percent_switch_3: 2.13768 links_utilized_percent_switch_3: 4.36236
links_utilized_percent_switch_3_link_0: 2.65248 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_0: 5.4129 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_1: 2.86465 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_1: 5.84589 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0.895915 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_2: 1.82829 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 448 32256 [ 0 0 0 0 448 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 70 5040 [ 0 0 0 0 70 0 0 0 0 0 ] base_latency: 1
@ -706,26 +706,26 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 532 memory_total_requests: 532
memory_reads: 448 memory_reads: 448
memory_writes: 84 memory_writes: 84
memory_refreshes: 184 memory_refreshes: 299
memory_total_request_delays: 169 memory_total_request_delays: 150
memory_delays_per_request: 0.317669 memory_delays_per_request: 0.281955
memory_delays_in_input_queue: 45 memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 0 memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 124 memory_delays_stalled_at_head_of_bank_queue: 150
memory_stalls_for_bank_busy: 31 memory_stalls_for_bank_busy: 38
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 10 memory_stalls_for_arbitration: 16
memory_stalls_for_bus: 81 memory_stalls_for_bus: 90
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 2 memory_stalls_for_read_write_turnaround: 6
memory_stalls_for_read_read_turnaround: 0 memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 19 10 0 39 20 19 31 22 5 3 6 4 22 41 22 3 4 6 7 13 10 18 14 42 16 5 5 12 13 18 14 69 accesses_per_bank: 19 10 0 39 20 19 31 22 5 3 6 4 22 41 22 3 4 6 7 13 10 18 14 42 16 5 5 12 13 18 14 69
--- Directory --- --- Directory ---
- Event Counts - - Event Counts -
GETX [107 ] 107 GETX [70 ] 70
GETS [441 ] 441 GETS [405 ] 405
Lockdown [0 ] 0 Lockdown [0 ] 0
Unlockdown [0 ] 0 Unlockdown [0 ] 0
Own_Lock_or_Unlock [0 ] 0 Own_Lock_or_Unlock [0 ] 0
@ -787,8 +787,8 @@ L DMA_READ [0 ] 0
L DMA_WRITE [0 ] 0 L DMA_WRITE [0 ] 0
L DMA_WRITE_All_Tokens [0 ] 0 L DMA_WRITE_All_Tokens [0 ] 0
O_W GETX [49 ] 49 O_W GETX [12 ] 12
O_W GETS [45 ] 45 O_W GETS [9 ] 9
O_W Lockdown [0 ] 0 O_W Lockdown [0 ] 0
O_W Unlockdown [0 ] 0 O_W Unlockdown [0 ] 0
O_W Own_Lock_or_Unlock [0 ] 0 O_W Own_Lock_or_Unlock [0 ] 0

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 28 2012 11:35:39 gem5 compiled Sep 9 2012 13:38:07
gem5 started Jul 28 2012 11:36:00 gem5 started Sep 9 2012 13:38:15
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Hello world! Hello world!
Exiting @ tick 87899 because target called exit() Exiting @ tick 43073 because target called exit()

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -78,7 +78,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -118,9 +118,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -129,6 +129,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -165,6 +166,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.cacheMemory dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory icache=system.l1_cntrl0.cacheMemory
@ -180,6 +182,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -281,6 +284,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

82
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
View file

@ -1,4 +1,4 @@
Real time: Jul/10/2012 17:25:18 Real time: Sep/09/2012 13:26:05
Profiler Stats Profiler Stats
-------------- --------------
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0 Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.41 Virtual_time_in_seconds: 0.39
Virtual_time_in_minutes: 0.00683333 Virtual_time_in_minutes: 0.0065
Virtual_time_in_hours: 0.000113889 Virtual_time_in_hours: 0.000108333
Virtual_time_in_days: 4.74537e-06 Virtual_time_in_days: 4.51389e-06
Ruby_current_time: 123378 Ruby_current_time: 52498
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 123378 Ruby_cycles: 52498
mbytes_resident: 44.5195 mbytes_resident: 53.1406
mbytes_total: 227.34 mbytes_total: 264.43
resident_ratio: 0.195845 resident_ratio: 0.200978
ruby_cycles_executed: [ 123379 ] ruby_cycles_executed: [ 52499 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -33,12 +33,12 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] miss_latency: [binsize: 1 max: 94 count: 3294 average: 14.9375 | standard deviation: 24.8042 | 0 0 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 4 7 128 221 203 1 2 1 2 7 11 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 4 18 11 0 1 ]
miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 1 max: 92 count: 415 average: 40.3325 | standard deviation: 31.5967 | 0 0 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 44 94 74 0 2 0 1 2 5 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 9 6 ]
miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 1 max: 92 count: 294 average: 20.9456 | standard deviation: 28.6341 | 0 0 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 16 31 29 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ]
miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_IFETCH: [binsize: 1 max: 94 count: 2585 average: 10.1772 | standard deviation: 20.0197 | 0 0 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 68 96 100 1 0 0 1 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 6 4 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ]
miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] miss_latency_Directory: [binsize: 1 max: 94 count: 626 average: 65.8147 | standard deviation: 6.37759 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 4 7 128 221 203 1 2 1 2 7 11 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 4 18 11 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -47,14 +47,14 @@ imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 625 imcomplete_dir_Times: 625
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ] miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ]
miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_Directory: [binsize: 1 max: 92 count: 245 average: 66.2367 | standard deviation: 7.0079 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 44 94 74 0 2 0 1 2 5 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 9 6 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ]
miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_Directory: [binsize: 1 max: 92 count: 84 average: 65.8095 | standard deviation: 6.52244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 16 31 29 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_IFETCH_Directory: [binsize: 1 max: 94 count: 297 average: 65.468 | standard deviation: 5.76218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 68 96 100 1 0 0 1 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 6 4 0 1 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -86,11 +86,11 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 12524 page_reclaims: 10146
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
block_outputs: 0 block_outputs: 80
Network Stats Network Stats
------------- -------------
@ -103,9 +103,9 @@ total_msgs: 7488 total_bytes: 299520
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.52881 links_utilized_percent_switch_0: 5.94308
links_utilized_percent_switch_0_link_0: 2.5353 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 5.95832 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.52233 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 5.92784 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
@ -114,9 +114,9 @@ links_utilized_percent_switch_0: 2.52881
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.52881 links_utilized_percent_switch_1: 5.94308
links_utilized_percent_switch_1_link_0: 2.52233 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 5.92784 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.5353 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 5.95832 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
@ -125,9 +125,9 @@ links_utilized_percent_switch_1: 2.52881
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.52881 links_utilized_percent_switch_2: 5.94308
links_utilized_percent_switch_2_link_0: 2.5353 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 5.95832 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.52233 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 5.92784 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
@ -190,19 +190,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1248 memory_total_requests: 1248
memory_reads: 626 memory_reads: 626
memory_writes: 622 memory_writes: 622
memory_refreshes: 258 memory_refreshes: 365
memory_total_request_delays: 1502 memory_total_request_delays: 915
memory_delays_per_request: 1.20353 memory_delays_per_request: 0.733173
memory_delays_in_input_queue: 414 memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 3 memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 1085 memory_delays_stalled_at_head_of_bank_queue: 915
memory_stalls_for_bank_busy: 404 memory_stalls_for_bank_busy: 352
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 39 memory_stalls_for_arbitration: 40
memory_stalls_for_bus: 620 memory_stalls_for_bus: 497
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 22 memory_stalls_for_read_write_turnaround: 26
memory_stalls_for_read_read_turnaround: 0 memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138 accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 16:32:12 gem5 compiled Sep 9 2012 13:25:55
gem5 started Jul 10 2012 17:25:18 gem5 started Sep 9 2012 13:26:05
gem5 executing on sc2b0605 gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Hello world! Hello world!
Exiting @ tick 123378 because target called exit() Exiting @ tick 52498 because target called exit()

10
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -78,7 +78,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -118,9 +118,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -129,6 +129,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -165,6 +166,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.cacheMemory dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory icache=system.l1_cntrl0.cacheMemory
@ -180,6 +182,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -281,6 +284,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

10
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:00:38 gem5 compiled Sep 9 2012 13:41:09
gem5 started Aug 13 2012 18:12:12 gem5 started Sep 9 2012 13:41:16
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Hello World! Hello World!
Exiting @ tick 292960 because target called exit() Exiting @ tick 125334 because target called exit()

10
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -78,7 +78,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -118,9 +118,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -129,6 +129,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -165,6 +166,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.cacheMemory dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory icache=system.l1_cntrl0.cacheMemory
@ -180,6 +182,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -281,6 +284,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

98
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
View file

@ -1,4 +1,4 @@
Real time: Jul/10/2012 17:57:35 Real time: Sep/09/2012 13:47:33
Profiler Stats Profiler Stats
-------------- --------------
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0 Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.48 Virtual_time_in_seconds: 0.42
Virtual_time_in_minutes: 0.008 Virtual_time_in_minutes: 0.007
Virtual_time_in_hours: 0.000133333 Virtual_time_in_hours: 0.000116667
Virtual_time_in_days: 5.55556e-06 Virtual_time_in_days: 4.86111e-06
Ruby_current_time: 253364 Ruby_current_time: 107952
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 253364 Ruby_cycles: 107952
mbytes_resident: 47.7148 mbytes_resident: 54.2266
mbytes_total: 237.852 mbytes_total: 273.301
resident_ratio: 0.200624 resident_ratio: 0.198428
ruby_cycles_executed: [ 253365 ] ruby_cycles_executed: [ 107953 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -29,16 +29,16 @@ Directory-0:0
Busy Bank Count:0 Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | standard deviation: 0 | 0 6773 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6759 average: 1 | standard deviation: 0 | 0 6759 ]
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency: [binsize: 1 max: 125 count: 6758 average: 14.974 | standard deviation: 24.8304 | 0 0 0 5469 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 9 10 284 430 440 7 1 3 10 10 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 5 23 35 1 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 1 max: 93 count: 715 average: 37.3343 | standard deviation: 31.1717 | 0 0 0 320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 6 4 94 137 128 1 0 0 4 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 9 1 ]
miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_ST: [binsize: 1 max: 125 count: 673 average: 20.0223 | standard deviation: 28.6826 | 0 0 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 43 50 63 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 4 8 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH: [binsize: 1 max: 98 count: 5370 average: 11.3641 | standard deviation: 21.4696 | 0 0 0 4655 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 2 5 147 243 249 5 1 2 5 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 16 18 0 0 1 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average: 3 | standard deviation: 0 | 0 0 0 5483 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 5469 average: 3 | standard deviation: 0 | 0 0 0 5469 ]
miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_Directory: [binsize: 1 max: 125 count: 1289 average: 65.7773 | standard deviation: 6.53621 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 9 10 284 430 440 7 1 3 10 10 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 5 23 35 1 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -47,14 +47,14 @@ imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1288 imcomplete_dir_Times: 1288
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average: 3 | standard deviation: 0 | 0 0 0 321 ] miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 320 average: 3 | standard deviation: 0 | 0 0 0 320 ]
miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_Directory: [binsize: 1 max: 93 count: 395 average: 65.1494 | standard deviation: 5.26963 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 6 4 94 137 128 1 0 0 4 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 9 1 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ]
miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_ST_Directory: [binsize: 1 max: 125 count: 179 average: 67 | standard deviation: 9.07893 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 43 50 63 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 4 8 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average: 3 | standard deviation: 0 | 0 0 0 4668 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4655 average: 3 | standard deviation: 0 | 0 0 0 4655 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH_Directory: [binsize: 1 max: 98 count: 715 average: 65.8182 | standard deviation: 6.37188 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 2 5 147 243 249 5 1 2 5 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 16 18 0 0 1 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -86,11 +86,11 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 13315 page_reclaims: 10992
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
block_outputs: 0 block_outputs: 80
Network Stats Network Stats
------------- -------------
@ -103,9 +103,9 @@ total_msgs: 15444 total_bytes: 617760
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.53982 links_utilized_percent_switch_0: 5.96098
links_utilized_percent_switch_0_link_0: 2.54298 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 5.96839 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.53667 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 5.95357 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
@ -114,9 +114,9 @@ links_utilized_percent_switch_0: 2.53982
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.53982 links_utilized_percent_switch_1: 5.96098
links_utilized_percent_switch_1_link_0: 2.53667 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 5.95357 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.54298 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 5.96839 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
@ -125,9 +125,9 @@ links_utilized_percent_switch_1: 2.53982
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.53982 links_utilized_percent_switch_2: 5.96098
links_utilized_percent_switch_2_link_0: 2.54298 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 5.96839 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.53667 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 5.95357 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
@ -149,8 +149,8 @@ Cache Stats: system.l1_cntrl0.cacheMemory
--- L1Cache --- --- L1Cache ---
- Event Counts - - Event Counts -
Load [716 ] 716 Load [715 ] 715
Ifetch [5383 ] 5383 Ifetch [5370 ] 5370
Store [673 ] 673 Store [673 ] 673
Data [1289 ] 1289 Data [1289 ] 1289
Fwd_GETX [0 ] 0 Fwd_GETX [0 ] 0
@ -168,8 +168,8 @@ I Replacement [0 ] 0
II Writeback_Nack [0 ] 0 II Writeback_Nack [0 ] 0
M Load [321 ] 321 M Load [320 ] 320
M Ifetch [4668 ] 4668 M Ifetch [4655 ] 4655
M Store [494 ] 494 M Store [494 ] 494
M Fwd_GETX [0 ] 0 M Fwd_GETX [0 ] 0
M Inv [0 ] 0 M Inv [0 ] 0
@ -190,19 +190,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 2574 memory_total_requests: 2574
memory_reads: 1289 memory_reads: 1289
memory_writes: 1285 memory_writes: 1285
memory_refreshes: 528 memory_refreshes: 750
memory_total_request_delays: 2936 memory_total_request_delays: 1873
memory_delays_per_request: 1.14064 memory_delays_per_request: 0.727661
memory_delays_in_input_queue: 668 memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 3 memory_delays_behind_head_of_bank_queue: 2
memory_delays_stalled_at_head_of_bank_queue: 2265 memory_delays_stalled_at_head_of_bank_queue: 1871
memory_stalls_for_bank_busy: 847 memory_stalls_for_bank_busy: 758
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 88 memory_stalls_for_arbitration: 69
memory_stalls_for_bus: 1292 memory_stalls_for_bus: 992
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 38 memory_stalls_for_read_write_turnaround: 52
memory_stalls_for_read_read_turnaround: 0 memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66 accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66

10
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
View file

@ -1,10 +1,12 @@
Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:04:37 gem5 compiled Sep 9 2012 13:47:14
gem5 started Aug 13 2012 18:13:09 gem5 started Sep 9 2012 13:47:33
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 253364 because target called exit() Hello World!Exiting @ tick 107952 because target called exit()

13
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
system=system system=system
@ -64,11 +64,13 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker] [system.cpu.dtb.walker]
type=X86PagetableWalker type=X86PagetableWalker
clock=1
system=system system=system
port=system.l1_cntrl0.sequencer.slave[3] port=system.l1_cntrl0.sequencer.slave[3]
[system.cpu.interrupts] [system.cpu.interrupts]
type=X86LocalApic type=X86LocalApic
clock=1
int_latency=1 int_latency=1
pio_addr=2305843009213693952 pio_addr=2305843009213693952
pio_latency=1 pio_latency=1
@ -85,6 +87,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker] [system.cpu.itb.walker]
type=X86PagetableWalker type=X86PagetableWalker
clock=1
system=system system=system
port=system.l1_cntrl0.sequencer.slave[2] port=system.l1_cntrl0.sequencer.slave[2]
@ -99,7 +102,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -139,9 +142,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -150,6 +153,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -186,6 +190,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=true access_phys_mem=true
clock=1
dcache=system.l1_cntrl0.cacheMemory dcache=system.l1_cntrl0.cacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.cacheMemory icache=system.l1_cntrl0.cacheMemory
@ -202,6 +207,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port s
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -303,6 +309,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

102
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
View file

@ -1,4 +1,4 @@
Real time: Jul/10/2012 17:59:21 Real time: Sep/09/2012 13:51:25
Profiler Stats Profiler Stats
-------------- --------------
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0 Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.54 Virtual_time_in_seconds: 0.53
Virtual_time_in_minutes: 0.009 Virtual_time_in_minutes: 0.00883333
Virtual_time_in_hours: 0.00015 Virtual_time_in_hours: 0.000147222
Virtual_time_in_days: 6.25e-06 Virtual_time_in_days: 6.13426e-06
Ruby_current_time: 276484 Ruby_current_time: 121759
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 276484 Ruby_cycles: 121759
mbytes_resident: 51.5117 mbytes_resident: 59.5742
mbytes_total: 239.223 mbytes_total: 275.16
resident_ratio: 0.215346 resident_ratio: 0.216522
ruby_cycles_executed: [ 276485 ] ruby_cycles_executed: [ 121760 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -29,17 +29,17 @@ Directory-0:0
Busy Bank Count:0 Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8901 average: 1 | standard deviation: 0 | 0 8901 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8851 average: 1 | standard deviation: 0 | 0 8851 ]
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency: [binsize: 1 max: 125 count: 8850 average: 12.7581 | standard deviation: 22.8706 | 0 0 0 7473 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_ST: [binsize: 1 max: 92 count: 934 average: 20.1188 | standard deviation: 28.2308 | 0 0 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ]
miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66288 | standard deviation: 18.0056 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average: 3 | standard deviation: 0 | 0 0 0 7523 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 7473 average: 3 | standard deviation: 0 | 0 0 0 7473 ]
miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7153 | standard deviation: 6.33839 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -48,16 +48,16 @@ imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1376 imcomplete_dir_Times: 1376
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average: 3 | standard deviation: 0 | 0 0 0 549 ] miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average: 3 | standard deviation: 0 | 0 0 0 545 ]
miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ]
miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9488 | standard deviation: 6.5357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average: 3 | standard deviation: 0 | 0 0 0 6287 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.3917 | standard deviation: 5.66183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -89,11 +89,11 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 14592 page_reclaims: 11362
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
block_outputs: 0 block_outputs: 80
Network Stats Network Stats
------------- -------------
@ -106,9 +106,9 @@ total_msgs: 16500 total_bytes: 660000
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 2.48658 links_utilized_percent_switch_0: 5.6464
links_utilized_percent_switch_0_link_0: 2.48947 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 5.65297 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 2.48369 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 5.63983 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
@ -117,9 +117,9 @@ links_utilized_percent_switch_0: 2.48658
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 2.48658 links_utilized_percent_switch_1: 5.6464
links_utilized_percent_switch_1_link_0: 2.48369 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 5.63983 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 2.48947 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 5.65297 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
@ -128,9 +128,9 @@ links_utilized_percent_switch_1: 2.48658
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 2.48658 links_utilized_percent_switch_2: 5.6464
links_utilized_percent_switch_2_link_0: 2.48947 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 5.65297 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 2.48369 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 5.63983 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
@ -152,8 +152,8 @@ Cache Stats: system.l1_cntrl0.cacheMemory
--- L1Cache --- --- L1Cache ---
- Event Counts - - Event Counts -
Load [1048 ] 1048 Load [1044 ] 1044
Ifetch [6910 ] 6910 Ifetch [6864 ] 6864
Store [942 ] 942 Store [942 ] 942
Data [1377 ] 1377 Data [1377 ] 1377
Fwd_GETX [0 ] 0 Fwd_GETX [0 ] 0
@ -171,8 +171,8 @@ I Replacement [0 ] 0
II Writeback_Nack [0 ] 0 II Writeback_Nack [0 ] 0
M Load [549 ] 549 M Load [545 ] 545
M Ifetch [6287 ] 6287 M Ifetch [6241 ] 6241
M Store [687 ] 687 M Store [687 ] 687
M Fwd_GETX [0 ] 0 M Fwd_GETX [0 ] 0
M Inv [0 ] 0 M Inv [0 ] 0
@ -193,19 +193,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 2750 memory_total_requests: 2750
memory_reads: 1377 memory_reads: 1377
memory_writes: 1373 memory_writes: 1373
memory_refreshes: 576 memory_refreshes: 846
memory_total_request_delays: 3035 memory_total_request_delays: 1965
memory_delays_per_request: 1.10364 memory_delays_per_request: 0.714545
memory_delays_in_input_queue: 743 memory_delays_in_input_queue: 0
memory_delays_behind_head_of_bank_queue: 6 memory_delays_behind_head_of_bank_queue: 3
memory_delays_stalled_at_head_of_bank_queue: 2286 memory_delays_stalled_at_head_of_bank_queue: 1962
memory_stalls_for_bank_busy: 791 memory_stalls_for_bank_busy: 830
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 78 memory_stalls_for_arbitration: 62
memory_stalls_for_bus: 1373 memory_stalls_for_bus: 1039
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 44 memory_stalls_for_read_write_turnaround: 31
memory_stalls_for_read_read_turnaround: 0 memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54 accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54

10
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
View file

@ -1,11 +1,13 @@
Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout
Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:08:22 gem5 compiled Sep 9 2012 13:51:17
gem5 started Aug 13 2012 18:23:02 gem5 started Sep 9 2012 13:51:25
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Hello world! Hello world!
Exiting @ tick 276484 because target called exit() Exiting @ tick 121759 because target called exit()

23
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcbus funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcbus funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -30,6 +31,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu0] [system.cpu0]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -48,6 +50,7 @@ test=system.l1_cntrl0.sequencer.slave[0]
[system.cpu1] [system.cpu1]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -66,6 +69,7 @@ test=system.l1_cntrl1.sequencer.slave[0]
[system.cpu2] [system.cpu2]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -84,6 +88,7 @@ test=system.l1_cntrl2.sequencer.slave[0]
[system.cpu3] [system.cpu3]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -102,6 +107,7 @@ test=system.l1_cntrl3.sequencer.slave[0]
[system.cpu4] [system.cpu4]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -120,6 +126,7 @@ test=system.l1_cntrl4.sequencer.slave[0]
[system.cpu5] [system.cpu5]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -138,6 +145,7 @@ test=system.l1_cntrl5.sequencer.slave[0]
[system.cpu6] [system.cpu6]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -156,6 +164,7 @@ test=system.l1_cntrl6.sequencer.slave[0]
[system.cpu7] [system.cpu7]
type=MemTest type=MemTest
atomic=false atomic=false
clock=1
issue_dmas=false issue_dmas=false
max_loads=100000 max_loads=100000
memory_size=65536 memory_size=65536
@ -203,9 +212,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -214,6 +223,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -229,6 +239,7 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
[system.funcmem] [system.funcmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=false in_addr_map=false
@ -293,6 +304,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl0.L1DcacheMemory dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl0.L1IcacheMemory icache=system.l1_cntrl0.L1IcacheMemory
@ -360,6 +372,7 @@ tagArrayBanks=1
[system.l1_cntrl1.sequencer] [system.l1_cntrl1.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl1.L1DcacheMemory dcache=system.l1_cntrl1.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl1.L1IcacheMemory icache=system.l1_cntrl1.L1IcacheMemory
@ -427,6 +440,7 @@ tagArrayBanks=1
[system.l1_cntrl2.sequencer] [system.l1_cntrl2.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl2.L1DcacheMemory dcache=system.l1_cntrl2.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl2.L1IcacheMemory icache=system.l1_cntrl2.L1IcacheMemory
@ -494,6 +508,7 @@ tagArrayBanks=1
[system.l1_cntrl3.sequencer] [system.l1_cntrl3.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl3.L1DcacheMemory dcache=system.l1_cntrl3.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl3.L1IcacheMemory icache=system.l1_cntrl3.L1IcacheMemory
@ -561,6 +576,7 @@ tagArrayBanks=1
[system.l1_cntrl4.sequencer] [system.l1_cntrl4.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl4.L1DcacheMemory dcache=system.l1_cntrl4.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl4.L1IcacheMemory icache=system.l1_cntrl4.L1IcacheMemory
@ -628,6 +644,7 @@ tagArrayBanks=1
[system.l1_cntrl5.sequencer] [system.l1_cntrl5.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl5.L1DcacheMemory dcache=system.l1_cntrl5.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl5.L1IcacheMemory icache=system.l1_cntrl5.L1IcacheMemory
@ -695,6 +712,7 @@ tagArrayBanks=1
[system.l1_cntrl6.sequencer] [system.l1_cntrl6.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl6.L1DcacheMemory dcache=system.l1_cntrl6.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl6.L1IcacheMemory icache=system.l1_cntrl6.L1IcacheMemory
@ -762,6 +780,7 @@ tagArrayBanks=1
[system.l1_cntrl7.sequencer] [system.l1_cntrl7.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl7.L1DcacheMemory dcache=system.l1_cntrl7.L1DcacheMemory
deadlock_threshold=1000000 deadlock_threshold=1000000
icache=system.l1_cntrl7.L1IcacheMemory icache=system.l1_cntrl7.L1IcacheMemory
@ -807,6 +826,7 @@ tagArrayBanks=1
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -1092,6 +1112,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true

8
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
View file

@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
type=System type=System
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
boot_osflags=a boot_osflags=a
clock=1
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
@ -59,9 +60,9 @@ bank_busy_time=11
bank_queue_size=12 bank_queue_size=12
banks_per_rank=8 banks_per_rank=8
basic_bus_busy_time=2 basic_bus_busy_time=2
clock=3
dimm_bit_0=12 dimm_bit_0=12
dimms_per_channel=2 dimms_per_channel=2
mem_bus_cycle_multiplier=10
mem_ctl_latency=12 mem_ctl_latency=12
mem_fixed_delay=0 mem_fixed_delay=0
mem_random_arbitrate=0 mem_random_arbitrate=0
@ -70,6 +71,7 @@ rank_rank_delay=1
ranks_per_dimm=2 ranks_per_dimm=2
read_write_delay=2 read_write_delay=2
refresh_period=1560 refresh_period=1560
ruby_system=system.ruby
tFaw=0 tFaw=0
version=0 version=0
@ -127,6 +129,7 @@ tagArrayBanks=1
[system.l1_cntrl0.sequencer] [system.l1_cntrl0.sequencer]
type=RubySequencer type=RubySequencer
access_phys_mem=false access_phys_mem=false
clock=1
dcache=system.l1_cntrl0.L1DcacheMemory dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000 deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory icache=system.l1_cntrl0.L1IcacheMemory
@ -172,6 +175,7 @@ tagArrayBanks=1
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
clock=1
conf_table_reported=false conf_table_reported=false
file= file=
in_addr_map=true in_addr_map=true
@ -296,6 +300,7 @@ ruby_system=system.ruby
[system.sys_port_proxy] [system.sys_port_proxy]
type=RubyPortProxy type=RubyPortProxy
access_phys_mem=true access_phys_mem=true
clock=1
ruby_system=system.ruby ruby_system=system.ruby
support_data_reqs=true support_data_reqs=true
support_inst_reqs=true support_inst_reqs=true
@ -309,6 +314,7 @@ slave=system.system_port
type=RubyTester type=RubyTester
check_flush=false check_flush=false
checks_to_complete=100 checks_to_complete=100
clock=1
deadlock_threshold=50000 deadlock_threshold=50000
num_cpus=1 num_cpus=1
system=system system=system

412
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
View file

@ -1,4 +1,4 @@
Real time: Jul/10/2012 17:49:52 Real time: Sep/09/2012 13:38:15
Profiler Stats Profiler Stats
-------------- --------------
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0 Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0 Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.53 Virtual_time_in_seconds: 0.52
Virtual_time_in_minutes: 0.00883333 Virtual_time_in_minutes: 0.00866667
Virtual_time_in_hours: 0.000147222 Virtual_time_in_hours: 0.000144444
Virtual_time_in_days: 6.13426e-06 Virtual_time_in_days: 6.01852e-06
Ruby_current_time: 259241 Ruby_current_time: 225141
Ruby_start_time: 0 Ruby_start_time: 0
Ruby_cycles: 259241 Ruby_cycles: 225141
mbytes_resident: 41.8477 mbytes_resident: 48.582
mbytes_total: 225.406 mbytes_total: 262.523
resident_ratio: 0.185689 resident_ratio: 0.185073
ruby_cycles_executed: [ 259242 ] ruby_cycles_executed: [ 225142 ]
Busy Controller Counts: Busy Controller Counts:
L1Cache-0:0 L1Cache-0:0
@ -30,17 +30,17 @@ Directory-0:0
Busy Bank Count:0 Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 998 average: 15.8297 | standard deviation: 1.12508 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 51 933 ] sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1007 average: 15.8213 | standard deviation: 1.12269 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 61 932 ]
All Non-Zero Cycle Demand Cache Accesses All Non-Zero Cycle Demand Cache Accesses
---------------------------------------- ----------------------------------------
miss_latency: [binsize: 64 max: 6727 count: 983 average: 4161.1 | standard deviation: 1947.91 | 87 10 3 3 7 4 15 8 10 8 2 11 4 4 5 1 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 3 0 5 4 2 2 11 11 6 16 17 20 23 28 30 31 31 35 36 41 23 36 40 40 30 35 40 27 26 16 14 15 25 13 8 11 10 8 5 4 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency: [binsize: 32 max: 5937 count: 992 average: 3579.07 | standard deviation: 1577.29 | 70 0 0 14 0 3 10 4 1 4 3 5 2 7 3 2 4 3 7 4 2 4 3 0 2 1 2 0 3 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 2 0 0 2 0 4 4 4 4 6 4 4 2 5 1 5 7 7 7 10 2 8 11 12 10 10 12 13 17 18 11 16 16 18 23 27 22 23 26 29 23 20 17 22 18 19 25 19 20 13 12 11 7 19 13 10 15 11 12 7 11 3 4 7 9 8 7 8 6 4 6 2 3 3 2 3 3 1 1 3 1 0 2 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 32 max: 6030 count: 42 average: 4225.5 | standard deviation: 2062.87 | 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 2 1 1 0 3 0 1 0 0 1 2 0 1 0 1 1 0 1 1 1 0 1 2 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 1 ] miss_latency_LD: [binsize: 32 max: 5568 count: 53 average: 3847.98 | standard deviation: 1453.91 | 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 2 1 0 0 1 0 0 1 0 2 1 1 0 2 1 0 2 2 1 1 1 0 1 2 2 1 0 0 2 0 0 3 2 1 0 0 0 0 1 0 0 1 0 2 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 ]
miss_latency_ST: [binsize: 64 max: 6727 count: 883 average: 4395.44 | standard deviation: 1763.39 | 79 9 2 1 2 4 5 5 1 0 0 4 0 1 2 1 1 1 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 3 0 4 4 2 2 11 11 6 16 17 20 22 27 29 29 31 32 35 38 22 35 38 39 28 34 38 26 23 16 13 14 24 12 6 11 9 8 5 4 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 32 max: 5937 count: 892 average: 3728.14 | standard deviation: 1448.25 | 66 0 0 11 0 3 1 3 0 0 2 5 0 0 3 2 0 1 3 3 1 2 0 0 0 0 1 0 3 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 2 0 0 2 0 4 4 4 4 5 4 4 2 5 1 4 6 7 7 10 2 7 9 11 10 10 11 13 17 17 11 14 15 17 23 25 21 23 24 27 22 19 16 22 17 17 23 18 20 13 10 11 7 16 11 9 15 11 12 7 10 3 4 6 9 6 7 8 6 3 5 2 2 3 1 3 3 1 1 3 1 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 8 max: 937 count: 58 average: 546.845 | standard deviation: 215.598 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 3 0 0 0 0 0 0 0 0 0 0 0 1 2 4 0 2 1 0 0 0 1 0 0 1 1 0 1 3 1 0 2 1 1 0 0 0 2 0 2 1 1 2 1 0 1 0 0 0 0 0 0 1 1 2 0 1 1 1 0 0 0 0 0 1 0 3 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH: [binsize: 8 max: 859 count: 47 average: 446.83 | standard deviation: 206.946 | 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 4 5 0 0 0 0 1 0 1 0 0 1 0 1 2 1 0 0 0 0 0 0 0 0 0 1 1 1 3 1 2 0 0 0 0 0 0 0 0 1 1 2 0 2 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 2 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 116 count: 96 average: 13.6875 | standard deviation: 33.4703 | 0 30 16 20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 2 1 0 0 3 ] miss_latency_L1Cache: [binsize: 1 max: 116 count: 82 average: 18.2561 | standard deviation: 38.3325 | 0 17 18 18 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 3 1 0 0 1 0 1 2 1 1 ]
miss_latency_L2Cache: [binsize: 32 max: 6221 count: 46 average: 2573.46 | standard deviation: 2204.04 | 0 1 0 0 0 2 0 0 2 1 0 3 2 2 0 1 0 2 0 0 0 0 1 0 0 1 1 1 2 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 3 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] miss_latency_L2Cache: [binsize: 32 max: 5349 count: 44 average: 2796.32 | standard deviation: 1876.08 | 0 0 0 0 0 3 0 0 0 0 1 2 0 1 0 2 0 0 1 1 2 1 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 1 1 0 1 2 0 0 1 2 1 0 3 0 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 ]
miss_latency_Directory: [binsize: 64 max: 6727 count: 841 average: 4721.37 | standard deviation: 1325.63 | 0 0 1 3 4 1 11 7 8 8 2 10 3 2 3 0 1 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 2 0 5 4 2 2 10 9 5 15 17 20 21 28 29 28 31 32 36 41 23 35 40 40 28 33 40 27 26 16 14 15 25 13 7 11 10 8 5 3 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_Directory: [binsize: 32 max: 5937 count: 866 average: 3956.01 | standard deviation: 1140.06 | 0 0 0 2 0 0 10 4 1 4 2 3 2 6 3 0 4 3 6 3 0 3 3 0 2 1 0 0 2 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 2 0 0 2 0 4 4 4 4 6 4 4 2 5 1 5 7 5 7 9 2 8 11 12 10 9 11 13 16 16 11 16 15 16 22 27 19 23 26 28 23 20 17 21 17 18 24 18 20 12 12 11 7 19 13 10 15 11 11 7 11 3 4 6 9 8 6 8 5 4 6 2 3 3 2 2 3 1 1 3 1 0 2 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -50,15 +50,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 841 imcomplete_dir_Times: 866
miss_latency_LD_L1Cache: [binsize: 1 max: 116 count: 7 average: 17.7143 | standard deviation: 43.3436 | 0 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_LD_L1Cache: [binsize: 1 max: 107 count: 5 average: 22.8 | standard deviation: 47.0771 | 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD_Directory: [binsize: 32 max: 6030 count: 35 average: 5067.06 | standard deviation: 870.007 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 2 1 1 0 3 0 1 0 0 1 2 0 1 0 1 1 0 1 1 1 0 1 2 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 1 ] miss_latency_LD_L2Cache: [binsize: 32 max: 4964 count: 2 average: 4682.5 | standard deviation: 398.102 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 88 average: 13.4886 | standard deviation: 33.0312 | 0 26 14 19 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 2 1 0 0 2 ] miss_latency_LD_Directory: [binsize: 32 max: 5568 count: 46 average: 4227.48 | standard deviation: 796.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 2 1 0 0 1 0 0 1 0 2 1 1 0 2 1 0 2 2 1 1 1 0 1 1 2 1 0 0 2 0 0 3 2 1 0 0 0 0 1 0 0 0 0 2 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 ]
miss_latency_ST_L2Cache: [binsize: 32 max: 6221 count: 38 average: 2985.71 | standard deviation: 2210.09 | 0 0 0 0 0 2 0 0 1 1 0 3 2 2 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 1 0 1 0 0 0 0 2 0 0 0 1 0 3 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 77 average: 17.961 | standard deviation: 38.0521 | 0 15 17 17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 0 1 0 1 2 1 1 ]
miss_latency_ST_Directory: [binsize: 64 max: 6727 count: 757 average: 4975.6 | standard deviation: 846.532 | 0 0 0 1 0 1 1 4 1 0 0 3 0 0 2 0 1 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 2 0 0 2 2 0 4 4 2 2 10 9 5 15 17 20 20 27 28 26 31 29 35 38 22 34 38 39 26 32 38 26 23 16 13 14 24 12 5 11 9 8 5 3 3 2 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L2Cache: [binsize: 32 max: 5349 count: 37 average: 2985.32 | standard deviation: 1821.77 | 0 0 0 0 0 3 0 0 0 0 1 2 0 0 0 2 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 1 1 0 1 2 0 0 1 2 1 0 3 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 1 average: 3 | standard deviation: 0 | 0 0 0 1 ] miss_latency_ST_Directory: [binsize: 32 max: 5937 count: 778 average: 4130.67 | standard deviation: 835.814 | 0 0 0 0 0 0 1 3 0 0 1 3 0 0 3 0 0 1 3 2 0 2 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 2 0 0 2 0 4 4 4 4 5 4 4 2 5 1 4 6 5 7 9 2 7 9 11 10 9 10 13 16 15 11 14 14 15 22 25 18 23 24 26 22 19 16 21 16 17 22 17 20 12 10 11 7 16 11 9 15 11 11 7 10 3 4 6 9 6 6 8 5 3 5 2 2 3 1 2 3 1 1 3 1 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_L2Cache: [binsize: 8 max: 910 count: 8 average: 615.25 | standard deviation: 325.21 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH_L2Cache: [binsize: 8 max: 859 count: 5 average: 643.2 | standard deviation: 152.682 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH_Directory: [binsize: 8 max: 937 count: 49 average: 546.776 | standard deviation: 181.198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 0 0 0 0 1 2 4 0 2 1 0 0 0 1 0 0 1 1 0 1 3 1 0 1 0 1 0 0 0 2 0 2 1 1 2 1 0 1 0 0 0 0 0 0 1 1 2 0 1 1 1 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH_Directory: [binsize: 8 max: 823 count: 42 average: 423.452 | standard deviation: 201.278 | 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 4 5 0 0 0 0 1 0 1 0 0 1 0 1 2 1 0 0 0 0 0 0 0 0 0 1 1 1 3 1 1 0 0 0 0 0 0 0 0 1 1 2 0 2 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests All Non-Zero Cycle SW Prefetch Requests
------------------------------------ ------------------------------------
@ -90,123 +90,123 @@ Resource Usage
page_size: 4096 page_size: 4096
user_time: 0 user_time: 0
system_time: 0 system_time: 0
page_reclaims: 11869 page_reclaims: 9521
page_faults: 0 page_faults: 0
swaps: 0 swaps: 0
block_inputs: 0 block_inputs: 0
block_outputs: 0 block_outputs: 88
Network Stats Network Stats
------------- -------------
total_msg_count_Request_Control: 5214 41712 total_msg_count_Request_Control: 5349 42792
total_msg_count_Response_Data: 2676 192672 total_msg_count_Response_Data: 2775 199800
total_msg_count_ResponseL2hit_Data: 123 8856 total_msg_count_ResponseL2hit_Data: 120 8640
total_msg_count_Response_Control: 3 24 total_msg_count_Response_Control: 3 24
total_msg_count_Writeback_Data: 5019 361368 total_msg_count_Writeback_Data: 5214 375408
total_msg_count_Writeback_Control: 222 1776 total_msg_count_Writeback_Control: 216 1728
total_msg_count_Persistent_Control: 2172 17376 total_msg_count_Persistent_Control: 2238 17904
total_msgs: 15429 total_bytes: 623784 total_msgs: 15915 total_bytes: 646296
switch_0_inlinks: 2 switch_0_inlinks: 2
switch_0_outlinks: 2 switch_0_outlinks: 2
links_utilized_percent_switch_0: 1.81771 links_utilized_percent_switch_0: 2.17386
links_utilized_percent_switch_0_link_0: 1.73468 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_0: 2.07781 bw: 16000 base_latency: 1
links_utilized_percent_switch_0_link_1: 1.90074 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 2.26991 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 898 64656 [ 0 0 0 0 898 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Data: 49 3528 [ 0 0 0 0 49 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Data: 60 4320 [ 0 0 0 0 60 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 889 7112 [ 0 889 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Request_Control: 911 7288 [ 0 911 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Response_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 933 67176 [ 0 0 0 0 933 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Data: 966 69552 [ 0 0 0 0 966 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2 switch_1_inlinks: 2
switch_1_outlinks: 2 switch_1_outlinks: 2
links_utilized_percent_switch_1: 1.67826 links_utilized_percent_switch_1: 1.98342
links_utilized_percent_switch_1_link_0: 1.77576 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_0: 2.09602 bw: 16000 base_latency: 1
links_utilized_percent_switch_1_link_1: 1.58077 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 1.87083 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 889 7112 [ 0 889 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 911 7288 [ 0 911 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 884 63648 [ 0 0 0 0 884 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 906 65232 [ 0 0 0 0 906 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Request_Control: 849 6792 [ 0 0 849 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Request_Control: 872 6976 [ 0 0 872 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 28 2016 [ 0 0 0 0 28 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Data: 28 2016 [ 0 0 0 0 28 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Data: 739 53208 [ 0 0 0 0 739 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Data: 763 54936 [ 0 0 0 0 763 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 74 592 [ 0 0 0 0 74 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 72 576 [ 0 0 0 0 72 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2 switch_2_inlinks: 2
switch_2_outlinks: 2 switch_2_outlinks: 2
links_utilized_percent_switch_2: 1.51693 links_utilized_percent_switch_2: 1.82319
links_utilized_percent_switch_2_link_0: 1.57228 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_0: 1.88948 bw: 16000 base_latency: 1
links_utilized_percent_switch_2_link_1: 1.46157 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 1.7569 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Request_Control: 849 6792 [ 0 0 849 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Request_Control: 872 6976 [ 0 0 872 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Data: 740 53280 [ 0 0 0 0 740 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Data: 772 55584 [ 0 0 0 0 772 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 74 592 [ 0 0 0 0 74 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 72 576 [ 0 0 0 0 72 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Data: 841 60552 [ 0 0 0 0 841 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Response_Data: 870 62640 [ 0 0 0 0 870 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Writeback_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3 switch_3_inlinks: 3
switch_3_outlinks: 3 switch_3_outlinks: 3
links_utilized_percent_switch_3: 1.67097 links_utilized_percent_switch_3: 1.99349
links_utilized_percent_switch_3_link_0: 1.66486 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_0: 1.99497 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_1: 1.77576 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_1: 2.09602 bw: 16000 base_latency: 1
links_utilized_percent_switch_3_link_2: 1.57228 bw: 16000 base_latency: 1 links_utilized_percent_switch_3_link_2: 1.88948 bw: 16000 base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 898 64656 [ 0 0 0 0 898 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 41 2952 [ 0 0 0 0 41 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Writeback_Data: 49 3528 [ 0 0 0 0 49 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Writeback_Data: 60 4320 [ 0 0 0 0 60 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Request_Control: 889 7112 [ 0 889 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Request_Control: 911 7288 [ 0 911 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Data: 884 63648 [ 0 0 0 0 884 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Writeback_Data: 906 65232 [ 0 0 0 0 906 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Request_Control: 849 6792 [ 0 0 849 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Request_Control: 872 6976 [ 0 0 872 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Data: 740 53280 [ 0 0 0 0 740 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Data: 772 55584 [ 0 0 0 0 772 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 74 592 [ 0 0 0 0 74 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 72 576 [ 0 0 0 0 72 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Persistent_Control: 362 2896 [ 0 0 0 362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Persistent_Control: 373 2984 [ 0 0 0 373 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 57 system.l1_cntrl0.L1IcacheMemory_total_misses: 47
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 57 system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 47
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 57 100% system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 47 100%
Cache Stats: system.l1_cntrl0.L1DcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 832 system.l1_cntrl0.L1DcacheMemory_total_misses: 864
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 832 system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 864
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.20673% system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.55556%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.7933% system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4444%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 832 100% system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 864 100%
--- L1Cache --- --- L1Cache ---
- Event Counts - - Event Counts -
Load [42 ] 42 Load [53 ] 53
Ifetch [58 ] 58 Ifetch [47 ] 47
Store [885 ] 885 Store [893 ] 893
Atomic [0 ] 0 Atomic [0 ] 0
L1_Replacement [19139 ] 19139 L1_Replacement [19950 ] 19950
Data_Shared [4 ] 4 Data_Shared [3 ] 3
Data_Owner [1 ] 1 Data_Owner [1 ] 1
Data_All_Tokens [954 ] 954 Data_All_Tokens [993 ] 993
Ack [0 ] 0 Ack [0 ] 0
Ack_All_Tokens [1 ] 1 Ack_All_Tokens [1 ] 1
Transient_GETX [0 ] 0 Transient_GETX [0 ] 0
@ -218,21 +218,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
Persistent_GETX [0 ] 0 Persistent_GETX [0 ] 0
Persistent_GETS [0 ] 0 Persistent_GETS [0 ] 0
Persistent_GETS_Last_Token [0 ] 0 Persistent_GETS_Last_Token [0 ] 0
Own_Lock_or_Unlock [362 ] 362 Own_Lock_or_Unlock [373 ] 373
Request_Timeout [556 ] 556 Request_Timeout [509 ] 509
Use_TimeoutStarverX [0 ] 0 Use_TimeoutStarverX [0 ] 0
Use_TimeoutStarverS [0 ] 0 Use_TimeoutStarverS [0 ] 0
Use_TimeoutNoStarvers [882 ] 882 Use_TimeoutNoStarvers [906 ] 906
Use_TimeoutNoStarvers_NoMig [0 ] 0 Use_TimeoutNoStarvers_NoMig [0 ] 0
- Transitions - - Transitions -
NP Load [35 ] 35 NP Load [48 ] 48
NP Ifetch [57 ] 57 NP Ifetch [47 ] 47
NP Store [797 ] 797 NP Store [816 ] 816
NP Atomic [0 ] 0 NP Atomic [0 ] 0
NP Data_Shared [0 ] 0 NP Data_Shared [0 ] 0
NP Data_Owner [0 ] 0 NP Data_Owner [0 ] 0
NP Data_All_Tokens [72 ] 72 NP Data_All_Tokens [87 ] 87
NP Ack [0 ] 0 NP Ack [0 ] 0
NP Transient_GETX [0 ] 0 NP Transient_GETX [0 ] 0
NP Transient_Local_GETX [0 ] 0 NP Transient_Local_GETX [0 ] 0
@ -241,7 +241,7 @@ NP Transient_Local_GETS [0 ] 0
NP Persistent_GETX [0 ] 0 NP Persistent_GETX [0 ] 0
NP Persistent_GETS [0 ] 0 NP Persistent_GETS [0 ] 0
NP Persistent_GETS_Last_Token [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0
NP Own_Lock_or_Unlock [178 ] 178 NP Own_Lock_or_Unlock [180 ] 180
I Load [0 ] 0 I Load [0 ] 0
I Ifetch [0 ] 0 I Ifetch [0 ] 0
@ -267,7 +267,7 @@ S Load [0 ] 0
S Ifetch [0 ] 0 S Ifetch [0 ] 0
S Store [0 ] 0 S Store [0 ] 0
S Atomic [0 ] 0 S Atomic [0 ] 0
S L1_Replacement [4 ] 4 S L1_Replacement [3 ] 3
S Data_Shared [0 ] 0 S Data_Shared [0 ] 0
S Data_Owner [0 ] 0 S Data_Owner [0 ] 0
S Data_All_Tokens [0 ] 0 S Data_All_Tokens [0 ] 0
@ -304,73 +304,73 @@ O Persistent_GETS_Last_Token [0 ] 0
O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock [0 ] 0
M Load [0 ] 0 M Load [0 ] 0
M Ifetch [1 ] 1 M Ifetch [0 ] 0
M Store [0 ] 0 M Store [0 ] 0
M Atomic [0 ] 0 M Atomic [0 ] 0
M L1_Replacement [86 ] 86 M L1_Replacement [89 ] 89
M Transient_GETX [0 ] 0 M Transient_GETX [0 ] 0
M Transient_Local_GETX [0 ] 0 M Transient_Local_GETX [0 ] 0
M Transient_GETS [0 ] 0 M Transient_GETS [0 ] 0
M Transient_Local_GETS [0 ] 0 M Transient_Local_GETS [0 ] 0
M Persistent_GETX [0 ] 0 M Persistent_GETX [0 ] 0
M Persistent_GETS [0 ] 0 M Persistent_GETS [0 ] 0
M Own_Lock_or_Unlock [14 ] 14 M Own_Lock_or_Unlock [18 ] 18
MM Load [7 ] 7 MM Load [5 ] 5
MM Ifetch [0 ] 0 MM Ifetch [0 ] 0
MM Store [76 ] 76 MM Store [66 ] 66
MM Atomic [0 ] 0 MM Atomic [0 ] 0
MM L1_Replacement [794 ] 794 MM L1_Replacement [814 ] 814
MM Transient_GETX [0 ] 0 MM Transient_GETX [0 ] 0
MM Transient_Local_GETX [0 ] 0 MM Transient_Local_GETX [0 ] 0
MM Transient_GETS [0 ] 0 MM Transient_GETS [0 ] 0
MM Transient_Local_GETS [0 ] 0 MM Transient_Local_GETS [0 ] 0
MM Persistent_GETX [0 ] 0 MM Persistent_GETX [0 ] 0
MM Persistent_GETS [0 ] 0 MM Persistent_GETS [0 ] 0
MM Own_Lock_or_Unlock [14 ] 14 MM Own_Lock_or_Unlock [15 ] 15
M_W Load [0 ] 0 M_W Load [0 ] 0
M_W Ifetch [0 ] 0 M_W Ifetch [0 ] 0
M_W Store [0 ] 0 M_W Store [0 ] 0
M_W Atomic [0 ] 0 M_W Atomic [0 ] 0
M_W L1_Replacement [262 ] 262 M_W L1_Replacement [468 ] 468
M_W Transient_GETX [0 ] 0 M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0 M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0 M_W Transient_GETS [0 ] 0
M_W Transient_Local_GETS [0 ] 0 M_W Transient_Local_GETS [0 ] 0
M_W Persistent_GETX [0 ] 0 M_W Persistent_GETX [0 ] 0
M_W Persistent_GETS [0 ] 0 M_W Persistent_GETS [0 ] 0
M_W Own_Lock_or_Unlock [3 ] 3 M_W Own_Lock_or_Unlock [1 ] 1
M_W Use_TimeoutStarverX [0 ] 0 M_W Use_TimeoutStarverX [0 ] 0
M_W Use_TimeoutStarverS [0 ] 0 M_W Use_TimeoutStarverS [0 ] 0
M_W Use_TimeoutNoStarvers [87 ] 87 M_W Use_TimeoutNoStarvers [91 ] 91
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
MM_W Load [0 ] 0 MM_W Load [0 ] 0
MM_W Ifetch [0 ] 0 MM_W Ifetch [0 ] 0
MM_W Store [12 ] 12 MM_W Store [11 ] 11
MM_W Atomic [0 ] 0 MM_W Atomic [0 ] 0
MM_W L1_Replacement [7507 ] 7507 MM_W L1_Replacement [7711 ] 7711
MM_W Transient_GETX [0 ] 0 MM_W Transient_GETX [0 ] 0
MM_W Transient_Local_GETX [0 ] 0 MM_W Transient_Local_GETX [0 ] 0
MM_W Transient_GETS [0 ] 0 MM_W Transient_GETS [0 ] 0
MM_W Transient_Local_GETS [0 ] 0 MM_W Transient_Local_GETS [0 ] 0
MM_W Persistent_GETX [0 ] 0 MM_W Persistent_GETX [0 ] 0
MM_W Persistent_GETS [0 ] 0 MM_W Persistent_GETS [0 ] 0
MM_W Own_Lock_or_Unlock [18 ] 18 MM_W Own_Lock_or_Unlock [25 ] 25
MM_W Use_TimeoutStarverX [0 ] 0 MM_W Use_TimeoutStarverX [0 ] 0
MM_W Use_TimeoutStarverS [0 ] 0 MM_W Use_TimeoutStarverS [0 ] 0
MM_W Use_TimeoutNoStarvers [795 ] 795 MM_W Use_TimeoutNoStarvers [815 ] 815
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
IM Load [0 ] 0 IM Load [0 ] 0
IM Ifetch [0 ] 0 IM Ifetch [0 ] 0
IM Store [0 ] 0 IM Store [0 ] 0
IM Atomic [0 ] 0 IM Atomic [0 ] 0
IM L1_Replacement [10013 ] 10013 IM L1_Replacement [10210 ] 10210
IM Data_Shared [0 ] 0 IM Data_Shared [0 ] 0
IM Data_Owner [1 ] 1 IM Data_Owner [1 ] 1
IM Data_All_Tokens [794 ] 794 IM Data_All_Tokens [814 ] 814
IM Ack [0 ] 0 IM Ack [0 ] 0
IM Transient_GETX [0 ] 0 IM Transient_GETX [0 ] 0
IM Transient_Local_GETX [0 ] 0 IM Transient_Local_GETX [0 ] 0
@ -381,8 +381,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0
IM Persistent_GETX [0 ] 0 IM Persistent_GETX [0 ] 0
IM Persistent_GETS [0 ] 0 IM Persistent_GETS [0 ] 0
IM Persistent_GETS_Last_Token [0 ] 0 IM Persistent_GETS_Last_Token [0 ] 0
IM Own_Lock_or_Unlock [120 ] 120 IM Own_Lock_or_Unlock [114 ] 114
IM Request_Timeout [493 ] 493 IM Request_Timeout [443 ] 443
SM Load [0 ] 0 SM Load [0 ] 0
SM Ifetch [0 ] 0 SM Ifetch [0 ] 0
@ -424,16 +424,16 @@ OM Persistent_GETX [0 ] 0
OM Persistent_GETS [0 ] 0 OM Persistent_GETS [0 ] 0
OM Persistent_GETS_Last_Token [0 ] 0 OM Persistent_GETS_Last_Token [0 ] 0
OM Own_Lock_or_Unlock [1 ] 1 OM Own_Lock_or_Unlock [1 ] 1
OM Request_Timeout [1 ] 1 OM Request_Timeout [6 ] 6
IS Load [0 ] 0 IS Load [0 ] 0
IS Ifetch [0 ] 0 IS Ifetch [0 ] 0
IS Store [0 ] 0 IS Store [0 ] 0
IS Atomic [0 ] 0 IS Atomic [0 ] 0
IS L1_Replacement [473 ] 473 IS L1_Replacement [655 ] 655
IS Data_Shared [4 ] 4 IS Data_Shared [3 ] 3
IS Data_Owner [0 ] 0 IS Data_Owner [0 ] 0
IS Data_All_Tokens [88 ] 88 IS Data_All_Tokens [92 ] 92
IS Ack [0 ] 0 IS Ack [0 ] 0
IS Transient_GETX [0 ] 0 IS Transient_GETX [0 ] 0
IS Transient_Local_GETX [0 ] 0 IS Transient_Local_GETX [0 ] 0
@ -444,8 +444,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0
IS Persistent_GETX [0 ] 0 IS Persistent_GETX [0 ] 0
IS Persistent_GETS [0 ] 0 IS Persistent_GETS [0 ] 0
IS Persistent_GETS_Last_Token [0 ] 0 IS Persistent_GETS_Last_Token [0 ] 0
IS Own_Lock_or_Unlock [14 ] 14 IS Own_Lock_or_Unlock [19 ] 19
IS Request_Timeout [62 ] 62 IS Request_Timeout [60 ] 60
I_L Load [0 ] 0 I_L Load [0 ] 0
I_L Ifetch [0 ] 0 I_L Ifetch [0 ] 0
@ -549,30 +549,30 @@ IS_L Own_Lock_or_Unlock [0 ] 0
IS_L Request_Timeout [0 ] 0 IS_L Request_Timeout [0 ] 0
Cache Stats: system.l2_cntrl0.L2cacheMemory Cache Stats: system.l2_cntrl0.L2cacheMemory
system.l2_cntrl0.L2cacheMemory_total_misses: 849 system.l2_cntrl0.L2cacheMemory_total_misses: 872
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 849 system.l2_cntrl0.L2cacheMemory_total_demand_misses: 872
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.3651% system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.5505%
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.6349% system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4495%
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 849 100% system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 872 100%
--- L2Cache --- --- L2Cache ---
- Event Counts - - Event Counts -
L1_GETS [92 ] 92 L1_GETS [95 ] 95
L1_GETS_Last_Token [0 ] 0 L1_GETS_Last_Token [0 ] 0
L1_GETX [797 ] 797 L1_GETX [816 ] 816
L1_INV [0 ] 0 L1_INV [0 ] 0
Transient_GETX [0 ] 0 Transient_GETX [0 ] 0
Transient_GETS [0 ] 0 Transient_GETS [0 ] 0
Transient_GETS_Last_Token [0 ] 0 Transient_GETS_Last_Token [0 ] 0
L2_Replacement [793 ] 793 L2_Replacement [817 ] 817
Writeback_Tokens [0 ] 0 Writeback_Tokens [0 ] 0
Writeback_Shared_Data [2 ] 2 Writeback_Shared_Data [1 ] 1
Writeback_All_Tokens [882 ] 882 Writeback_All_Tokens [905 ] 905
Writeback_Owned [0 ] 0 Writeback_Owned [0 ] 0
Data_Shared [0 ] 0 Data_Shared [0 ] 0
Data_Owner [0 ] 0 Data_Owner [0 ] 0
@ -580,19 +580,19 @@ Data_All_Tokens [0 ] 0
Ack [0 ] 0 Ack [0 ] 0
Ack_All_Tokens [0 ] 0 Ack_All_Tokens [0 ] 0
Persistent_GETX [163 ] 163 Persistent_GETX [163 ] 163
Persistent_GETS [18 ] 18 Persistent_GETS [24 ] 24
Persistent_GETS_Last_Token [0 ] 0 Persistent_GETS_Last_Token [0 ] 0
Own_Lock_or_Unlock [181 ] 181 Own_Lock_or_Unlock [186 ] 186
- Transitions - - Transitions -
NP L1_GETS [84 ] 84 NP L1_GETS [91 ] 91
NP L1_GETX [760 ] 760 NP L1_GETX [779 ] 779
NP L1_INV [0 ] 0 NP L1_INV [0 ] 0
NP Transient_GETX [0 ] 0 NP Transient_GETX [0 ] 0
NP Transient_GETS [0 ] 0 NP Transient_GETS [0 ] 0
NP Writeback_Tokens [0 ] 0 NP Writeback_Tokens [0 ] 0
NP Writeback_Shared_Data [1 ] 1 NP Writeback_Shared_Data [0 ] 0
NP Writeback_All_Tokens [796 ] 796 NP Writeback_All_Tokens [821 ] 821
NP Writeback_Owned [0 ] 0 NP Writeback_Owned [0 ] 0
NP Data_Shared [0 ] 0 NP Data_Shared [0 ] 0
NP Data_Owner [0 ] 0 NP Data_Owner [0 ] 0
@ -601,19 +601,19 @@ NP Ack [0 ] 0
NP Persistent_GETX [0 ] 0 NP Persistent_GETX [0 ] 0
NP Persistent_GETS [0 ] 0 NP Persistent_GETS [0 ] 0
NP Persistent_GETS_Last_Token [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0
NP Own_Lock_or_Unlock [152 ] 152 NP Own_Lock_or_Unlock [158 ] 158
I L1_GETS [4 ] 4 I L1_GETS [1 ] 1
I L1_GETS_Last_Token [0 ] 0 I L1_GETS_Last_Token [0 ] 0
I L1_GETX [0 ] 0 I L1_GETX [0 ] 0
I L1_INV [0 ] 0 I L1_INV [0 ] 0
I Transient_GETX [0 ] 0 I Transient_GETX [0 ] 0
I Transient_GETS [0 ] 0 I Transient_GETS [0 ] 0
I Transient_GETS_Last_Token [0 ] 0 I Transient_GETS_Last_Token [0 ] 0
I L2_Replacement [28 ] 28 I L2_Replacement [32 ] 32
I Writeback_Tokens [0 ] 0 I Writeback_Tokens [0 ] 0
I Writeback_Shared_Data [1 ] 1 I Writeback_Shared_Data [1 ] 1
I Writeback_All_Tokens [36 ] 36 I Writeback_All_Tokens [31 ] 31
I Writeback_Owned [0 ] 0 I Writeback_Owned [0 ] 0
I Data_Shared [0 ] 0 I Data_Shared [0 ] 0
I Data_Owner [0 ] 0 I Data_Owner [0 ] 0
@ -631,7 +631,7 @@ S L1_INV [0 ] 0
S Transient_GETX [0 ] 0 S Transient_GETX [0 ] 0
S Transient_GETS [0 ] 0 S Transient_GETS [0 ] 0
S Transient_GETS_Last_Token [0 ] 0 S Transient_GETS_Last_Token [0 ] 0
S L2_Replacement [1 ] 1 S L2_Replacement [0 ] 0
S Writeback_Tokens [0 ] 0 S Writeback_Tokens [0 ] 0
S Writeback_Shared_Data [0 ] 0 S Writeback_Shared_Data [0 ] 0
S Writeback_All_Tokens [0 ] 0 S Writeback_All_Tokens [0 ] 0
@ -652,7 +652,7 @@ O L1_INV [0 ] 0
O Transient_GETX [0 ] 0 O Transient_GETX [0 ] 0
O Transient_GETS [0 ] 0 O Transient_GETS [0 ] 0
O Transient_GETS_Last_Token [0 ] 0 O Transient_GETS_Last_Token [0 ] 0
O L2_Replacement [1 ] 1 O L2_Replacement [0 ] 0
O Writeback_Tokens [0 ] 0 O Writeback_Tokens [0 ] 0
O Writeback_Shared_Data [0 ] 0 O Writeback_Shared_Data [0 ] 0
O Writeback_All_Tokens [2 ] 2 O Writeback_All_Tokens [2 ] 2
@ -665,14 +665,14 @@ O Persistent_GETS [0 ] 0
O Persistent_GETS_Last_Token [0 ] 0 O Persistent_GETS_Last_Token [0 ] 0
O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock [0 ] 0
M L1_GETS [4 ] 4 M L1_GETS [3 ] 3
M L1_GETX [36 ] 36 M L1_GETX [36 ] 36
M L1_INV [0 ] 0 M L1_INV [0 ] 0
M Transient_GETX [0 ] 0 M Transient_GETX [0 ] 0
M Transient_GETS [0 ] 0 M Transient_GETS [0 ] 0
M L2_Replacement [763 ] 763 M L2_Replacement [784 ] 784
M Persistent_GETX [24 ] 24 M Persistent_GETX [23 ] 23
M Persistent_GETS [4 ] 4 M Persistent_GETS [5 ] 5
M Own_Lock_or_Unlock [0 ] 0 M Own_Lock_or_Unlock [0 ] 0
I_L L1_GETS [0 ] 0 I_L L1_GETS [0 ] 0
@ -681,18 +681,18 @@ I_L L1_INV [0 ] 0
I_L Transient_GETX [0 ] 0 I_L Transient_GETX [0 ] 0
I_L Transient_GETS [0 ] 0 I_L Transient_GETS [0 ] 0
I_L Transient_GETS_Last_Token [0 ] 0 I_L Transient_GETS_Last_Token [0 ] 0
I_L L2_Replacement [0 ] 0 I_L L2_Replacement [1 ] 1
I_L Writeback_Tokens [0 ] 0 I_L Writeback_Tokens [0 ] 0
I_L Writeback_Shared_Data [0 ] 0 I_L Writeback_Shared_Data [0 ] 0
I_L Writeback_All_Tokens [48 ] 48 I_L Writeback_All_Tokens [51 ] 51
I_L Writeback_Owned [0 ] 0 I_L Writeback_Owned [0 ] 0
I_L Data_Shared [0 ] 0 I_L Data_Shared [0 ] 0
I_L Data_Owner [0 ] 0 I_L Data_Owner [0 ] 0
I_L Data_All_Tokens [0 ] 0 I_L Data_All_Tokens [0 ] 0
I_L Ack [0 ] 0 I_L Ack [0 ] 0
I_L Persistent_GETX [138 ] 138 I_L Persistent_GETX [139 ] 139
I_L Persistent_GETS [14 ] 14 I_L Persistent_GETS [19 ] 19
I_L Own_Lock_or_Unlock [29 ] 29 I_L Own_Lock_or_Unlock [28 ] 28
S_L L1_GETS [0 ] 0 S_L L1_GETS [0 ] 0
S_L L1_GETS_Last_Token [0 ] 0 S_L L1_GETS_Last_Token [0 ] 0
@ -716,83 +716,83 @@ S_L Persistent_GETS_Last_Token [0 ] 0
S_L Own_Lock_or_Unlock [0 ] 0 S_L Own_Lock_or_Unlock [0 ] 0
Memory controller: system.dir_cntrl0.memBuffer: Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1605 memory_total_requests: 1655
memory_reads: 843 memory_reads: 868
memory_writes: 762 memory_writes: 787
memory_refreshes: 541 memory_refreshes: 1564
memory_total_request_delays: 1171 memory_total_request_delays: 503
memory_delays_per_request: 0.729595 memory_delays_per_request: 0.303927
memory_delays_in_input_queue: 153 memory_delays_in_input_queue: 34
memory_delays_behind_head_of_bank_queue: 2 memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 1016 memory_delays_stalled_at_head_of_bank_queue: 469
memory_stalls_for_bank_busy: 265 memory_stalls_for_bank_busy: 134
memory_stalls_for_random_busy: 0 memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0 memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 87 memory_stalls_for_arbitration: 39
memory_stalls_for_bus: 390 memory_stalls_for_bus: 192
memory_stalls_for_tfaw: 0 memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 196 memory_stalls_for_read_write_turnaround: 48
memory_stalls_for_read_read_turnaround: 78 memory_stalls_for_read_read_turnaround: 56
accesses_per_bank: 36 45 70 85 76 62 82 41 44 46 52 30 33 46 34 56 43 52 47 46 58 35 52 38 37 64 59 60 46 39 40 51 accesses_per_bank: 51 47 34 94 74 59 55 45 53 55 62 49 52 51 44 57 49 51 46 44 46 41 54 56 46 55 50 43 43 47 62 40
--- Directory --- --- Directory ---
- Event Counts - - Event Counts -
GETX [795 ] 795 GETX [789 ] 789
GETS [105 ] 105 GETS [94 ] 94
Lockdown [181 ] 181 Lockdown [187 ] 187
Unlockdown [181 ] 181 Unlockdown [186 ] 186
Own_Lock_or_Unlock [0 ] 0 Own_Lock_or_Unlock [0 ] 0
Own_Lock_or_Unlock_Tokens [0 ] 0 Own_Lock_or_Unlock_Tokens [0 ] 0
Data_Owner [1 ] 1 Data_Owner [0 ] 0
Data_All_Tokens [762 ] 762 Data_All_Tokens [799 ] 799
Ack_Owner [0 ] 0 Ack_Owner [0 ] 0
Ack_Owner_All_Tokens [72 ] 72 Ack_Owner_All_Tokens [72 ] 72
Tokens [0 ] 0 Tokens [0 ] 0
Ack_All_Tokens [1 ] 1 Ack_All_Tokens [0 ] 0
Request_Timeout [0 ] 0 Request_Timeout [0 ] 0
Memory_Data [841 ] 841 Memory_Data [868 ] 868
Memory_Ack [762 ] 762 Memory_Ack [787 ] 787
DMA_READ [0 ] 0 DMA_READ [0 ] 0
DMA_WRITE [0 ] 0 DMA_WRITE [0 ] 0
DMA_WRITE_All_Tokens [0 ] 0 DMA_WRITE_All_Tokens [0 ] 0
- Transitions - - Transitions -
O GETX [755 ] 755 O GETX [768 ] 768
O GETS [84 ] 84 O GETS [86 ] 86
O Lockdown [4 ] 4 O Lockdown [14 ] 14
O Unlockdown [0 ] 0 O Unlockdown [0 ] 0
O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock [0 ] 0
O Own_Lock_or_Unlock_Tokens [0 ] 0 O Own_Lock_or_Unlock_Tokens [0 ] 0
O Data_Owner [0 ] 0 O Data_Owner [0 ] 0
O Data_All_Tokens [0 ] 0 O Data_All_Tokens [0 ] 0
O Tokens [0 ] 0 O Tokens [0 ] 0
O Ack_All_Tokens [1 ] 1 O Ack_All_Tokens [0 ] 0
O DMA_READ [0 ] 0 O DMA_READ [0 ] 0
O DMA_WRITE [0 ] 0 O DMA_WRITE [0 ] 0
O DMA_WRITE_All_Tokens [0 ] 0 O DMA_WRITE_All_Tokens [0 ] 0
NO GETX [2 ] 2 NO GETX [2 ] 2
NO GETS [4 ] 4 NO GETS [4 ] 4
NO Lockdown [162 ] 162 NO Lockdown [166 ] 166
NO Unlockdown [0 ] 0 NO Unlockdown [0 ] 0
NO Own_Lock_or_Unlock [0 ] 0 NO Own_Lock_or_Unlock [0 ] 0
NO Own_Lock_or_Unlock_Tokens [0 ] 0 NO Own_Lock_or_Unlock_Tokens [0 ] 0
NO Data_Owner [1 ] 1 NO Data_Owner [0 ] 0
NO Data_All_Tokens [761 ] 761 NO Data_All_Tokens [787 ] 787
NO Ack_Owner [0 ] 0 NO Ack_Owner [0 ] 0
NO Ack_Owner_All_Tokens [72 ] 72 NO Ack_Owner_All_Tokens [72 ] 72
NO Tokens [0 ] 0 NO Tokens [0 ] 0
NO DMA_READ [0 ] 0 NO DMA_READ [0 ] 0
NO DMA_WRITE [0 ] 0 NO DMA_WRITE [0 ] 0
L GETX [4 ] 4 L GETX [10 ] 10
L GETS [0 ] 0 L GETS [2 ] 2
L Lockdown [0 ] 0 L Lockdown [0 ] 0
L Unlockdown [181 ] 181 L Unlockdown [185 ] 185
L Own_Lock_or_Unlock [0 ] 0 L Own_Lock_or_Unlock [0 ] 0
L Own_Lock_or_Unlock_Tokens [0 ] 0 L Own_Lock_or_Unlock_Tokens [0 ] 0
L Data_Owner [0 ] 0 L Data_Owner [0 ] 0
L Data_All_Tokens [1 ] 1 L Data_All_Tokens [12 ] 12
L Ack_Owner [0 ] 0 L Ack_Owner [0 ] 0
L Ack_Owner_All_Tokens [0 ] 0 L Ack_Owner_All_Tokens [0 ] 0
L Tokens [0 ] 0 L Tokens [0 ] 0
@ -801,7 +801,7 @@ L DMA_WRITE [0 ] 0
L DMA_WRITE_All_Tokens [0 ] 0 L DMA_WRITE_All_Tokens [0 ] 0
O_W GETX [0 ] 0 O_W GETX [0 ] 0
O_W GETS [17 ] 17 O_W GETS [0 ] 0
O_W Lockdown [0 ] 0 O_W Lockdown [0 ] 0
O_W Unlockdown [0 ] 0 O_W Unlockdown [0 ] 0
O_W Own_Lock_or_Unlock [0 ] 0 O_W Own_Lock_or_Unlock [0 ] 0
@ -811,16 +811,16 @@ O_W Data_All_Tokens [0 ] 0
O_W Ack_Owner [0 ] 0 O_W Ack_Owner [0 ] 0
O_W Tokens [0 ] 0 O_W Tokens [0 ] 0
O_W Ack_All_Tokens [0 ] 0 O_W Ack_All_Tokens [0 ] 0
O_W Memory_Data [0 ] 0 O_W Memory_Data [1 ] 1
O_W Memory_Ack [762 ] 762 O_W Memory_Ack [787 ] 787
O_W DMA_READ [0 ] 0 O_W DMA_READ [0 ] 0
O_W DMA_WRITE [0 ] 0 O_W DMA_WRITE [0 ] 0
O_W DMA_WRITE_All_Tokens [0 ] 0 O_W DMA_WRITE_All_Tokens [0 ] 0
L_O_W GETX [34 ] 34 L_O_W GETX [9 ] 9
L_O_W GETS [0 ] 0 L_O_W GETS [2 ] 2
L_O_W Lockdown [0 ] 0 L_O_W Lockdown [0 ] 0
L_O_W Unlockdown [0 ] 0 L_O_W Unlockdown [1 ] 1
L_O_W Own_Lock_or_Unlock [0 ] 0 L_O_W Own_Lock_or_Unlock [0 ] 0
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
L_O_W Data_Owner [0 ] 0 L_O_W Data_Owner [0 ] 0
@ -828,7 +828,7 @@ L_O_W Data_All_Tokens [0 ] 0
L_O_W Ack_Owner [0 ] 0 L_O_W Ack_Owner [0 ] 0
L_O_W Tokens [0 ] 0 L_O_W Tokens [0 ] 0
L_O_W Ack_All_Tokens [0 ] 0 L_O_W Ack_All_Tokens [0 ] 0
L_O_W Memory_Data [4 ] 4 L_O_W Memory_Data [13 ] 13
L_O_W Memory_Ack [0 ] 0 L_O_W Memory_Ack [0 ] 0
L_O_W DMA_READ [0 ] 0 L_O_W DMA_READ [0 ] 0
L_O_W DMA_WRITE [0 ] 0 L_O_W DMA_WRITE [0 ] 0
@ -845,7 +845,7 @@ L_NO_W Data_All_Tokens [0 ] 0
L_NO_W Ack_Owner [0 ] 0 L_NO_W Ack_Owner [0 ] 0
L_NO_W Tokens [0 ] 0 L_NO_W Tokens [0 ] 0
L_NO_W Ack_All_Tokens [0 ] 0 L_NO_W Ack_All_Tokens [0 ] 0
L_NO_W Memory_Data [15 ] 15 L_NO_W Memory_Data [7 ] 7
L_NO_W DMA_READ [0 ] 0 L_NO_W DMA_READ [0 ] 0
L_NO_W DMA_WRITE [0 ] 0 L_NO_W DMA_WRITE [0 ] 0
L_NO_W DMA_WRITE_All_Tokens [0 ] 0 L_NO_W DMA_WRITE_All_Tokens [0 ] 0
@ -886,7 +886,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0
NO_W GETX [0 ] 0 NO_W GETX [0 ] 0
NO_W GETS [0 ] 0 NO_W GETS [0 ] 0
NO_W Lockdown [15 ] 15 NO_W Lockdown [7 ] 7
NO_W Unlockdown [0 ] 0 NO_W Unlockdown [0 ] 0
NO_W Own_Lock_or_Unlock [0 ] 0 NO_W Own_Lock_or_Unlock [0 ] 0
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
@ -895,7 +895,7 @@ NO_W Data_All_Tokens [0 ] 0
NO_W Ack_Owner [0 ] 0 NO_W Ack_Owner [0 ] 0
NO_W Tokens [0 ] 0 NO_W Tokens [0 ] 0
NO_W Ack_All_Tokens [0 ] 0 NO_W Ack_All_Tokens [0 ] 0
NO_W Memory_Data [822 ] 822 NO_W Memory_Data [847 ] 847
NO_W DMA_READ [0 ] 0 NO_W DMA_READ [0 ] 0
NO_W DMA_WRITE [0 ] 0 NO_W DMA_WRITE [0 ] 0
NO_W DMA_WRITE_All_Tokens [0 ] 0 NO_W DMA_WRITE_All_Tokens [0 ] 0

10
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
View file

@ -1,10 +1,12 @@
Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 28 2012 11:35:39 gem5 compiled Sep 9 2012 13:38:07
gem5 started Jul 28 2012 11:36:05 gem5 started Sep 9 2012 13:38:15
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 259241 because Ruby Tester completed Exiting @ tick 225141 because Ruby Tester completed