Registers: Eliminate the ISA defined RegFile class.
This commit is contained in:
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9bf22992ee
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5c37d10624
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@ -57,7 +57,6 @@ enum MiscRegIndex
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class MiscRegFile
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class MiscRegFile
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{
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{
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public:
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public:
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friend class RegFile;
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typedef uint64_t InternalProcReg;
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typedef uint64_t InternalProcReg;
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protected:
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protected:
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@ -52,22 +52,6 @@ const int reg_redir[NumIntRegs] = {
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/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
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/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
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#endif
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#endif
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void
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RegFile::serialize(EventManager *em, ostream &os)
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{
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#if FULL_SYSTEM
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SERIALIZE_SCALAR(intrflag);
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#endif
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}
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void
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RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
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{
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#if FULL_SYSTEM
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UNSERIALIZE_SCALAR(intrflag);
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#endif
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}
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void
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void
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copyRegs(ThreadContext *src, ThreadContext *dest)
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copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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{
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@ -46,22 +46,6 @@ namespace AlphaISA {
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// redirected register map, really only used for the full system case.
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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extern const int reg_redir[NumIntRegs];
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class RegFile {
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public:
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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#endif // FULL_SYSTEM
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void
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clear()
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{
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}
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void serialize(EventManager *em, std::ostream &os);
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion);
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};
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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@ -433,7 +433,6 @@ void InterruptFault::invoke(ThreadContext *tc)
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{
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{
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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DPRINTF(Arm,"%s encountered.\n", name());
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DPRINTF(Arm,"%s encountered.\n", name());
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//RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
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setExceptionState(tc,0x0A);
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setExceptionState(tc,0x0A);
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Addr HandlerBase;
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Addr HandlerBase;
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@ -469,7 +468,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc)
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{
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{
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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DPRINTF(Arm,"%s encountered.\n", name());
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DPRINTF(Arm,"%s encountered.\n", name());
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//RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
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setExceptionState(tc,0x0A);
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setExceptionState(tc,0x0A);
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Addr HandlerBase;
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Addr HandlerBase;
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HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector
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HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector
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@ -84,8 +84,6 @@ namespace ArmISA
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assert(misc_reg < NumMiscRegs);
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assert(misc_reg < NumMiscRegs);
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miscRegFile[misc_reg] = val;
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miscRegFile[misc_reg] = val;
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}
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}
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friend class RegFile;
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};
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};
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} // namespace ArmISA
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} // namespace ArmISA
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@ -93,20 +93,6 @@ namespace ArmISA
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r14_abt
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r14_abt
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};
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};
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class RegFile
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{
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public:
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void clear()
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{}
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void serialize(EventManager *em, std::ostream &os)
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{}
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion)
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{}
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};
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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@ -435,7 +435,6 @@ void InterruptFault::invoke(ThreadContext *tc)
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{
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{
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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DPRINTF(MipsPRA,"%s encountered.\n", name());
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DPRINTF(MipsPRA,"%s encountered.\n", name());
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//RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
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setExceptionState(tc,0x0A);
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setExceptionState(tc,0x0A);
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Addr HandlerBase;
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Addr HandlerBase;
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@ -471,7 +470,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc)
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{
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{
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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DPRINTF(MipsPRA,"%s encountered.\n", name());
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DPRINTF(MipsPRA,"%s encountered.\n", name());
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//RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
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setExceptionState(tc,0x0A);
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setExceptionState(tc,0x0A);
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Addr HandlerBase;
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Addr HandlerBase;
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HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
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HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
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@ -48,9 +48,6 @@ namespace MipsISA
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{
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{
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class MiscRegFile {
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class MiscRegFile {
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public:
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public:
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// Give RegFile object, private access
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friend class RegFile;
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// The MIPS name for this file is CP0 or Coprocessor 0
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// The MIPS name for this file is CP0 or Coprocessor 0
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typedef MiscRegFile CP0;
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typedef MiscRegFile CP0;
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@ -92,27 +92,6 @@ namespace MipsISA
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//TotalArchRegs = NumIntArchRegs * ShadowSets
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//TotalArchRegs = NumIntArchRegs * ShadowSets
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const int TotalArchRegs = NumIntArchRegs;
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const int TotalArchRegs = NumIntArchRegs;
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class RegFile {
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public:
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void clear()
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{}
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void reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes, BaseCPU *_cpu)
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{}
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void setShadowSet(int css)
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{}
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public:
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void serialize(EventManager *em, std::ostream &os)
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{}
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion)
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{}
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};
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} // namespace MipsISA
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} // namespace MipsISA
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#endif
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#endif
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@ -44,8 +44,6 @@ namespace BigEndianGuest {}
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namespace SparcISA
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namespace SparcISA
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{
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{
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class RegFile;
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const int MachineBytes = 8;
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const int MachineBytes = 8;
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//This makes sure the big endian versions of certain functions are used.
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//This makes sure the big endian versions of certain functions are used.
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@ -47,20 +47,6 @@ namespace SparcISA
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const int NumIntArchRegs = 32;
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const int NumIntArchRegs = 32;
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const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
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const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
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class RegFile
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{
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public:
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void clear()
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{}
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void serialize(EventManager *em, std::ostream &os)
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{}
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion)
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{}
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};
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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@ -84,19 +84,6 @@ namespace X86ISA
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NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
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NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
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const int NumFloatArchRegs = NumFloatRegs + 8;
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const int NumFloatArchRegs = NumFloatRegs + 8;
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class RegFile
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{
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public:
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void clear()
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{}
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void serialize(EventManager *em, std::ostream &os)
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{}
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion)
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{}
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};
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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@ -77,7 +77,6 @@ class InOrderCPU : public BaseCPU
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typedef TheISA::IntReg IntReg;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::MiscReg MiscReg;
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//DynInstPtr TypeDefs
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//DynInstPtr TypeDefs
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@ -110,7 +110,6 @@ SimpleThread::SimpleThread()
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#endif
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#endif
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{
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{
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tc = new ProxyThreadContext<SimpleThread>(this);
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tc = new ProxyThreadContext<SimpleThread>(this);
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regs.clear();
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}
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}
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SimpleThread::~SimpleThread()
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SimpleThread::~SimpleThread()
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@ -191,7 +190,6 @@ void
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SimpleThread::serialize(ostream &os)
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SimpleThread::serialize(ostream &os)
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{
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{
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ThreadState::serialize(os);
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ThreadState::serialize(os);
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regs.serialize(cpu, os);
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SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
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SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
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SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
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SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
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SERIALIZE_SCALAR(microPC);
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SERIALIZE_SCALAR(microPC);
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@ -207,7 +205,6 @@ void
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SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
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SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
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{
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{
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ThreadState::unserialize(cp, section);
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ThreadState::unserialize(cp, section);
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regs.unserialize(cpu, cp, section);
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UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
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UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
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UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
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UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
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UNSERIALIZE_SCALAR(microPC);
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UNSERIALIZE_SCALAR(microPC);
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@ -90,7 +90,6 @@ class TranslatingPort;
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class SimpleThread : public ThreadState
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class SimpleThread : public ThreadState
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{
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{
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protected:
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protected:
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatReg FloatReg;
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@ -99,7 +98,6 @@ class SimpleThread : public ThreadState
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typedef ThreadContext::Status Status;
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typedef ThreadContext::Status Status;
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protected:
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protected:
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RegFile regs; // correct-path register context
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union {
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union {
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FloatReg f[TheISA::NumFloatRegs];
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FloatReg f[TheISA::NumFloatRegs];
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FloatRegBits i[TheISA::NumFloatRegs];
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FloatRegBits i[TheISA::NumFloatRegs];
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@ -253,7 +251,6 @@ class SimpleThread : public ThreadState
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void clearArchRegs()
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void clearArchRegs()
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{
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{
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regs.clear();
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microPC = 0;
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microPC = 0;
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nextMicroPC = 1;
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nextMicroPC = 1;
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PC = nextPC = nextNPC = 0;
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PC = nextPC = nextNPC = 0;
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@ -79,7 +79,6 @@ namespace TheISA {
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class ThreadContext
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class ThreadContext
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{
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{
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protected:
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protected:
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatReg FloatReg;
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@ -496,7 +496,6 @@ class Tru64 : public OperatingSystem
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{
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{
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using namespace TheISA;
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using namespace TheISA;
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using TheISA::RegFile;
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TypedBufferArg<Tru64::sigcontext> sc(process->getSyscallArg(tc, 0));
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TypedBufferArg<Tru64::sigcontext> sc(process->getSyscallArg(tc, 0));
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sc.copyIn(tc->getMemPort());
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sc.copyIn(tc->getMemPort());
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