SPARC: Make PSTATE and HPSTATE a BitUnion.
This gets rid of cryptic bits of code with lots of bit manipulation, and makes some comments redundant.
This commit is contained in:
parent
aa513a4a99
commit
5b557a314f
14 changed files with 182 additions and 156 deletions
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@ -276,17 +276,15 @@ enterREDState(ThreadContext *tc)
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{
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//@todo Disable the mmu?
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//@todo Disable watchpoints?
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MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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// HPSTATE.red = 1
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HPSTATE |= (1 << 5);
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// HPSTATE.hpriv = 1
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HPSTATE |= (1 << 2);
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tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
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HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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hpstate.red = 1;
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hpstate.hpriv = 1;
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tc->setMiscReg(MISCREG_HPSTATE, hpstate);
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// PSTATE.priv is set to 1 here. The manual says it should be 0, but
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// Legion sets it to 1.
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MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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PSTATE |= (1 << 2);
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tc->setMiscReg(MISCREG_PSTATE, PSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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pstate.priv = 1;
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tc->setMiscReg(MISCREG_PSTATE, pstate);
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}
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/**
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@ -299,8 +297,8 @@ doREDFault(ThreadContext *tc, TrapType tt)
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{
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MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
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MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
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MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
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MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
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MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
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@ -310,7 +308,7 @@ doREDFault(ThreadContext *tc, TrapType tt)
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TL++;
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Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
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Addr pcMask = pstate.am ? mask(32) : mask(64);
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// set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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@ -319,7 +317,7 @@ doREDFault(ThreadContext *tc, TrapType tt)
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// set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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// set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, PSTATE);
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replaceBits(TSTATE, 20, 8, pstate);
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// set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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@ -332,7 +330,7 @@ doREDFault(ThreadContext *tc, TrapType tt)
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tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
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// set HTSTATE.hpstate to hpstate
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tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
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tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
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// TT = trap type;
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tc->setMiscRegNoEffect(MISCREG_TT, tt);
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@ -340,19 +338,17 @@ doREDFault(ThreadContext *tc, TrapType tt)
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// Update GL
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tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
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PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
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PSTATE |= (1 << 4); // set PSTATE.pef to 1
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tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
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bool priv = pstate.priv; // just save the priv bit
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pstate = 0;
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pstate.priv = priv;
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pstate.pef = 1;
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tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
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// set HPSTATE.red to 1
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HPSTATE |= (1 << 5);
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// set HPSTATE.hpriv to 1
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HPSTATE |= (1 << 2);
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// set HPSTATE.ibe to 0
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HPSTATE &= ~(1 << 10);
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// set HPSTATE.tlz to 0
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HPSTATE &= ~(1 << 0);
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
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hpstate.red = 1;
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hpstate.hpriv = 1;
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hpstate.ibe = 0;
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hpstate.tlz = 0;
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
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bool changedCWP = true;
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if (tt == 0x24)
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@ -380,8 +376,8 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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{
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MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
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MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
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MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
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MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
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MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
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@ -393,7 +389,7 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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TL++;
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tc->setMiscRegNoEffect(MISCREG_TL, TL);
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Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
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Addr pcMask = pstate.am ? mask(32) : mask(64);
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// Save off state
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@ -404,7 +400,7 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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// set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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// set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, PSTATE);
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replaceBits(TSTATE, 20, 8, pstate);
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// set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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@ -417,7 +413,7 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
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// set HTSTATE.hpstate to hpstate
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tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
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tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
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// TT = trap type;
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tc->setMiscRegNoEffect(MISCREG_TT, tt);
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@ -428,26 +424,26 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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else
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tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
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// PSTATE.mm is unchanged
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PSTATE |= (1 << 4); // PSTATE.pef = whether or not an fpu is present
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PSTATE &= ~(1 << 3); // PSTATE.am = 0
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PSTATE &= ~(1 << 1); // PSTATE.ie = 0
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// PSTATE.tle is unchanged
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// PSTATE.tct = 0
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// pstate.mm is unchanged
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pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
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pstate.am = 0;
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pstate.ie = 0;
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// pstate.tle is unchanged
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// pstate.tct = 0
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if (gotoHpriv) {
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PSTATE &= ~(1 << 9); // PSTATE.cle = 0
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pstate.cle = 0;
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// The manual says PSTATE.priv should be 0, but Legion leaves it alone
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HPSTATE &= ~(1 << 5); // HPSTATE.red = 0
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HPSTATE |= (1 << 2); // HPSTATE.hpriv = 1
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HPSTATE &= ~(1 << 10); // HPSTATE.ibe = 0
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// HPSTATE.tlz is unchanged
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
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hpstate.red = 0;
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hpstate.hpriv = 1;
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hpstate.ibe = 0;
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// hpstate.tlz is unchanged
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
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} else { // we are going to priv
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PSTATE |= (1 << 2); // PSTATE.priv = 1
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replaceBits(PSTATE, 9, 9, PSTATE >> 8); // PSTATE.cle = PSTATE.tle
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pstate.priv = 1;
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pstate.cle = pstate.tle;
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}
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tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
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tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
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bool changedCWP = true;
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@ -506,22 +502,22 @@ SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
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// in the middle could change it in the regfile out from under us.
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MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
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MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
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MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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Addr PC, NPC;
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PrivilegeLevel current;
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if (hpstate & HPSTATE::hpriv)
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if (hpstate.hpriv)
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current = Hyperprivileged;
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else if (pstate & PSTATE::priv)
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else if (pstate.priv)
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current = Privileged;
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else
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current = User;
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PrivilegeLevel level = getNextLevel(current);
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if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
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if (hpstate.red || (tl == MaxTL - 1)) {
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getREDVector(5, PC, NPC);
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doREDFault(tc, tt);
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// This changes the hpstate and pstate, so we need to make sure we
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@ -565,20 +561,18 @@ PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
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tc->setMiscRegNoEffect(MISCREG_TT, trapType());
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tc->setMiscReg(MISCREG_GL, MaxGL);
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// Turn on pef and priv, set everything else to 0
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tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
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PSTATE pstate = 0;
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pstate.pef = 1;
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pstate.priv = 1;
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tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
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// Turn on red and hpriv, set everything else to 0
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MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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// HPSTATE.red = 1
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HPSTATE |= (1 << 5);
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// HPSTATE.hpriv = 1
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HPSTATE |= (1 << 2);
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// HPSTATE.ibe = 0
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HPSTATE &= ~(1 << 10);
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// HPSTATE.tlz = 0
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HPSTATE &= ~(1 << 0);
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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hpstate.red = 1;
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hpstate.hpriv = 1;
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hpstate.ibe = 0;
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hpstate.tlz = 0;
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
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// The tick register is unreadable by nonprivileged software
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tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
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@ -127,17 +127,16 @@ class Interrupts : public SimObject
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Fault
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getInterrupt(ThreadContext *tc)
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{
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int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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bool ie = pstate & PSTATE::ie;
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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// THESE ARE IN ORDER OF PRIORITY
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// since there are early returns, and the highest
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// priority interrupts should get serviced,
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// it is v. important that new interrupts are inserted
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// in the right order of processing
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if (hpstate & HPSTATE::hpriv) {
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if (ie) {
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if (hpstate.hpriv) {
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if (pstate.ie) {
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if (interrupts[IT_HINTP]) {
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// This will be cleaned by a HINTP write
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return new HstickMatch;
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@ -160,7 +159,7 @@ class Interrupts : public SimObject
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// this will be cleared by an ASI read (or write)
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return new InterruptVector;
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}
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if (ie) {
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if (pstate.ie) {
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if (interrupts[IT_CPU_MONDO]) {
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return new CpuMondo;
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}
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@ -175,7 +174,7 @@ class Interrupts : public SimObject
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if (interrupts[IT_RES_ERROR]) {
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return new ResumableError;
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}
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} // !hpriv && ie
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} // !hpriv && pstate.ie
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} // !hpriv
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return NoFault;
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}
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@ -40,10 +40,22 @@
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namespace SparcISA
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{
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enum RegMask
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static PSTATE
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buildPstateMask()
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{
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PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
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};
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PSTATE mask = 0;
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mask.ie = 1;
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mask.priv = 1;
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mask.am = 1;
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mask.pef = 1;
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mask.mm = 3;
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mask.tle = 1;
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mask.cle = 1;
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mask.pid1 = 1;
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return mask;
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}
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static const PSTATE PstateMask = buildPstateMask();
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void
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ISA::reloadRegMap()
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@ -110,7 +122,8 @@ ISA::clear()
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// otherwin = 0;
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// wstate = 0;
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// In a T1, bit 11 is apparently always 1
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hpstate = (1 << 11);
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hpstate = 0;
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hpstate.id = 1;
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memset(htstate, 0, sizeof(htstate));
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hintp = 0;
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htba = 0;
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@ -163,9 +176,10 @@ ISA::readMiscRegNoEffect(int miscReg)
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* |^lsuim
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* ^lsudm
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*/
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return bits((uint64_t)hpstate,2,2) |
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bits((uint64_t)hpstate,5,5) << 1 |
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bits((uint64_t)pstate,3,2) << 2 |
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return (uint64_t)hpstate.hpriv |
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(uint64_t)hpstate.red << 1 |
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(uint64_t)pstate.priv << 2 |
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(uint64_t)pstate.am << 3 |
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bits((uint64_t)lsuCtrlReg,3,2) << 4 |
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bits((uint64_t)partId,7,0) << 8 |
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bits((uint64_t)tl,2,0) << 16 |
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@ -215,7 +229,7 @@ ISA::readMiscRegNoEffect(int miscReg)
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case MISCREG_TBA:
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return tba;
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case MISCREG_PSTATE:
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return pstate;
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return (MiscReg)pstate;
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case MISCREG_TL:
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return tl;
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case MISCREG_PIL:
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@ -238,7 +252,7 @@ ISA::readMiscRegNoEffect(int miscReg)
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/** Hyper privileged registers */
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case MISCREG_HPSTATE:
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return hpstate;
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return (MiscReg)hpstate;
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case MISCREG_HTSTATE:
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return htstate[tl-1];
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case MISCREG_HINTP:
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@ -408,7 +422,7 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
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tba = val & ULL(~0x7FFF);
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break;
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case MISCREG_PSTATE:
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pstate = (val & PSTATE_MASK);
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pstate = (val & PstateMask);
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break;
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case MISCREG_TL:
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tl = val;
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@ -550,15 +564,17 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
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// Set up performance counting based on pcr value
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break;
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case MISCREG_PSTATE:
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pstate = val & PSTATE_MASK;
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pstate = val & PstateMask;
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return;
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case MISCREG_TL:
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{
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tl = val;
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if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
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if (hpstate.tlz && tl == 0 && !hpstate.hpriv)
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tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
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else
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tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
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return;
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}
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case MISCREG_CWP:
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new_val = val >= NWindows ? NWindows - 1 : val;
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if (val >= NWindows)
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@ -616,12 +632,12 @@ ISA::serialize(EventManager *em, std::ostream &os)
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SERIALIZE_ARRAY(tstate,MaxTL);
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SERIALIZE_ARRAY(tt,MaxTL);
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SERIALIZE_SCALAR(tba);
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SERIALIZE_SCALAR(pstate);
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SERIALIZE_SCALAR((uint16_t)pstate);
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SERIALIZE_SCALAR(tl);
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SERIALIZE_SCALAR(pil);
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SERIALIZE_SCALAR(cwp);
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SERIALIZE_SCALAR(gl);
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SERIALIZE_SCALAR(hpstate);
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SERIALIZE_SCALAR((uint64_t)hpstate);
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SERIALIZE_ARRAY(htstate,MaxTL);
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SERIALIZE_SCALAR(hintp);
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SERIALIZE_SCALAR(htba);
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@ -692,13 +708,21 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
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UNSERIALIZE_ARRAY(tstate,MaxTL);
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UNSERIALIZE_ARRAY(tt,MaxTL);
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UNSERIALIZE_SCALAR(tba);
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{
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uint16_t pstate;
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UNSERIALIZE_SCALAR(pstate);
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this->pstate = pstate;
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}
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UNSERIALIZE_SCALAR(tl);
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UNSERIALIZE_SCALAR(pil);
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UNSERIALIZE_SCALAR(cwp);
|
||||
UNSERIALIZE_SCALAR(gl);
|
||||
reloadRegMap();
|
||||
{
|
||||
uint64_t hpstate;
|
||||
UNSERIALIZE_SCALAR(hpstate);
|
||||
this->hpstate = hpstate;
|
||||
}
|
||||
UNSERIALIZE_ARRAY(htstate,MaxTL);
|
||||
UNSERIALIZE_SCALAR(hintp);
|
||||
UNSERIALIZE_SCALAR(htba);
|
||||
|
|
|
@ -71,7 +71,7 @@ class ISA
|
|||
// on the previous level)
|
||||
uint64_t tba; // Trap Base Address
|
||||
|
||||
uint16_t pstate; // Process State Register
|
||||
PSTATE pstate; // Process State Register
|
||||
uint8_t tl; // Trap Level
|
||||
uint8_t pil; // Process Interrupt Register
|
||||
uint8_t cwp; // Current Window Pointer
|
||||
|
@ -83,7 +83,7 @@ class ISA
|
|||
uint8_t gl; // Global level register
|
||||
|
||||
/** Hyperprivileged Registers */
|
||||
uint64_t hpstate; // Hyperprivileged State Register
|
||||
HPSTATE hpstate; // Hyperprivileged State Register
|
||||
uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
|
||||
uint64_t hintp;
|
||||
uint64_t htba; // Hyperprivileged Trap Base Address register
|
||||
|
@ -172,8 +172,8 @@ class ISA
|
|||
|
||||
protected:
|
||||
|
||||
bool isHyperPriv() { return (hpstate & (1 << 2)); }
|
||||
bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
|
||||
bool isHyperPriv() { return hpstate.hpriv; }
|
||||
bool isPriv() { return hpstate.hpriv || pstate.priv; }
|
||||
bool isNonPriv() { return !isPriv(); }
|
||||
|
||||
public:
|
||||
|
|
|
@ -567,8 +567,8 @@ output exec {{
|
|||
checkFpEnableFault(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
if (FullSystem) {
|
||||
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
|
||||
xc->readMiscReg(MISCREG_FPRS) & 0x4) {
|
||||
PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE);
|
||||
if (pstate.pef && xc->readMiscReg(MISCREG_FPRS) & 0x4) {
|
||||
return NoFault;
|
||||
} else {
|
||||
return new FpDisabled;
|
||||
|
|
|
@ -139,7 +139,7 @@ decode OP default Unknown::unknown()
|
|||
}
|
||||
0x1: BranchN::call(30, {{
|
||||
IntReg midVal;
|
||||
R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC);
|
||||
R15 = midVal = (Pstate.am ? (PC)<31:0> : PC);
|
||||
NNPC = midVal + disp;
|
||||
}},None, None, IsIndirectControl, IsCall);
|
||||
0x2: decode OP3 {
|
||||
|
@ -327,7 +327,7 @@ decode OP default Unknown::unknown()
|
|||
0x03: NoPriv::rdasi({{Rd = Asi;}});
|
||||
0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
|
||||
0x05: NoPriv::rdpc({{
|
||||
if (Pstate<3:>)
|
||||
if (Pstate.am)
|
||||
Rd = (PC)<31:0>;
|
||||
else
|
||||
Rd = PC;
|
||||
|
@ -356,7 +356,7 @@ decode OP default Unknown::unknown()
|
|||
0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}});
|
||||
0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
|
||||
0x1A: Priv::rdstrand_sts_reg({{
|
||||
if (Pstate<2:> && !Hpstate<2:>)
|
||||
if (Pstate.am && !Hpstate.hpriv)
|
||||
Rd = StrandStsReg<0:>;
|
||||
else
|
||||
Rd = StrandStsReg;
|
||||
|
@ -479,7 +479,7 @@ decode OP default Unknown::unknown()
|
|||
0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
|
||||
// 0x12 should cause an illegal instruction exception
|
||||
0x13: NoPriv::wrgsr({{
|
||||
if (Fprs<2:> == 0 || Pstate<4:> == 0)
|
||||
if (Fprs<2:> == 0 || Pstate.pef == 0)
|
||||
return new FpDisabled;
|
||||
Gsr = Rs1 ^ Rs2_or_imm13;
|
||||
}});
|
||||
|
@ -488,7 +488,7 @@ decode OP default Unknown::unknown()
|
|||
0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x18: NoPriv::wrstick({{
|
||||
if (!Hpstate<2:>)
|
||||
if (!Hpstate.hpriv)
|
||||
return new IllegalInstruction;
|
||||
Stick = Rs1 ^ Rs2_or_imm13;
|
||||
}});
|
||||
|
@ -536,7 +536,7 @@ decode OP default Unknown::unknown()
|
|||
0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x07: Priv::wrprtl({{
|
||||
if (Pstate<2:> && !Hpstate<2:>)
|
||||
if (Pstate.priv && !Hpstate.hpriv)
|
||||
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
|
||||
else
|
||||
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
|
||||
|
@ -550,7 +550,7 @@ decode OP default Unknown::unknown()
|
|||
0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
|
||||
// 0x0F should cause an illegal instruction exception
|
||||
0x10: Priv::wrprgl({{
|
||||
if (Pstate<2:> && !Hpstate<2:>)
|
||||
if (Pstate.priv && !Hpstate.hpriv)
|
||||
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
|
||||
else
|
||||
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
|
||||
|
@ -997,7 +997,7 @@ decode OP default Unknown::unknown()
|
|||
if (target & 0x3) {
|
||||
fault = new MemAddressNotAligned;
|
||||
} else {
|
||||
if (Pstate<3:>)
|
||||
if (Pstate.am)
|
||||
Rd = (PC)<31:0>;
|
||||
else
|
||||
Rd = PC;
|
||||
|
|
|
@ -317,17 +317,17 @@ let {{
|
|||
# are split into ones that are available in priv and hpriv, and
|
||||
# those that are only available in hpriv
|
||||
AlternateASIPrivFaultCheck = '''
|
||||
if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
|
||||
if ((!Pstate.priv && !Hpstate.hpriv &&
|
||||
!asiIsUnPriv((ASI)EXT_ASI)) ||
|
||||
(!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI)))
|
||||
(!Hpstate.hpriv && asiIsHPriv((ASI)EXT_ASI)))
|
||||
fault = new PrivilegedAction;
|
||||
else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
|
||||
else if (asiIsAsIfUser((ASI)EXT_ASI) && !Pstate.priv)
|
||||
fault = new PrivilegedAction;
|
||||
'''
|
||||
|
||||
TruncateEA = '''
|
||||
if (!FullSystem)
|
||||
EA = Pstate<3:> ? EA<31:0> : EA;
|
||||
EA = Pstate.am ? EA<31:0> : EA;
|
||||
'''
|
||||
}};
|
||||
|
||||
|
|
|
@ -264,7 +264,7 @@ let {{
|
|||
}};
|
||||
|
||||
def format Priv(code, extraCond=true, checkTl=false, *opt_flags) {{
|
||||
checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCond
|
||||
checkCode = "(%s) && !(Pstate.priv || Hpstate.hpriv)" % extraCond
|
||||
if checkTl != "false":
|
||||
tlCheck = "Tl == 0"
|
||||
else:
|
||||
|
@ -289,7 +289,7 @@ def format NoPriv(code, checkTl=false, *opt_flags) {{
|
|||
}};
|
||||
|
||||
def format HPriv(code, checkTl=false, *opt_flags) {{
|
||||
checkCode = "!Hpstate<2:2>"
|
||||
checkCode = "!Hpstate.hpriv"
|
||||
if checkTl != "false":
|
||||
tlCheck = "Tl == 0"
|
||||
else:
|
||||
|
|
|
@ -40,7 +40,10 @@ def operand_types {{
|
|||
'tudw' : 'Twin64_t',
|
||||
'tuw' : 'Twin32_t',
|
||||
'sf' : 'float',
|
||||
'df' : 'double'
|
||||
'df' : 'double',
|
||||
|
||||
'pstate' : 'PSTATE',
|
||||
'hpstate' : 'HPSTATE'
|
||||
}};
|
||||
|
||||
output header {{
|
||||
|
@ -167,7 +170,7 @@ def operands {{
|
|||
'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
|
||||
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
|
||||
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
|
||||
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
|
||||
'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59),
|
||||
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
|
||||
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
|
||||
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
|
||||
|
@ -183,7 +186,7 @@ def operands {{
|
|||
'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
|
||||
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
|
||||
|
||||
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
|
||||
'Hpstate': ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69),
|
||||
'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
|
||||
'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
|
||||
'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#ifndef __ARCH_SPARC_MISCREGS_HH__
|
||||
#define __ARCH_SPARC_MISCREGS_HH__
|
||||
|
||||
#include "base/bitunion.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
namespace SparcISA
|
||||
|
@ -115,26 +116,25 @@ enum MiscRegIndex
|
|||
MISCREG_NUMMISCREGS
|
||||
};
|
||||
|
||||
struct HPSTATE
|
||||
{
|
||||
const static uint64_t id = 0x800; // this impl. dependent (id) field m
|
||||
const static uint64_t ibe = 0x400;
|
||||
const static uint64_t red = 0x20;
|
||||
const static uint64_t hpriv = 0x4;
|
||||
const static uint64_t tlz = 0x1;
|
||||
};
|
||||
BitUnion64(HPSTATE)
|
||||
Bitfield<0> tlz;
|
||||
Bitfield<2> hpriv;
|
||||
Bitfield<5> red;
|
||||
Bitfield<10> ibe;
|
||||
Bitfield<11> id; // this impl. dependent (id) field m
|
||||
EndBitUnion(HPSTATE)
|
||||
|
||||
|
||||
struct PSTATE
|
||||
{
|
||||
const static int cle = 0x200;
|
||||
const static int tle = 0x100;
|
||||
const static int mm = 0xC0;
|
||||
const static int pef = 0x10;
|
||||
const static int am = 0x8;
|
||||
const static int priv = 0x4;
|
||||
const static int ie = 0x2;
|
||||
};
|
||||
BitUnion16(PSTATE)
|
||||
Bitfield<1> ie;
|
||||
Bitfield<2> priv;
|
||||
Bitfield<3> am;
|
||||
Bitfield<4> pef;
|
||||
Bitfield<6, 7> mm;
|
||||
Bitfield<8> tle;
|
||||
Bitfield<9> cle;
|
||||
Bitfield<10> pid0;
|
||||
Bitfield<11> pid1;
|
||||
EndBitUnion(PSTATE)
|
||||
|
||||
struct STS
|
||||
{
|
||||
|
|
|
@ -161,7 +161,10 @@ Sparc32LiveProcess::initState()
|
|||
|
||||
ThreadContext *tc = system->getThreadContext(contextIds[0]);
|
||||
// The process runs in user mode with 32 bit addresses
|
||||
tc->setMiscReg(MISCREG_PSTATE, 0x0a);
|
||||
PSTATE pstate = 0;
|
||||
pstate.ie = 1;
|
||||
pstate.am = 1;
|
||||
tc->setMiscReg(MISCREG_PSTATE, pstate);
|
||||
|
||||
argsInit(32 / 8, VMPageSize);
|
||||
}
|
||||
|
@ -173,7 +176,9 @@ Sparc64LiveProcess::initState()
|
|||
|
||||
ThreadContext *tc = system->getThreadContext(contextIds[0]);
|
||||
// The process runs in user mode
|
||||
tc->setMiscReg(MISCREG_PSTATE, 0x02);
|
||||
PSTATE pstate = 0;
|
||||
pstate.ie = 1;
|
||||
tc->setMiscReg(MISCREG_PSTATE, pstate);
|
||||
|
||||
argsInit(sizeof(IntReg), VMPageSize);
|
||||
}
|
||||
|
@ -533,27 +538,22 @@ SparcLiveProcess::setSyscallReturn(ThreadContext *tc,
|
|||
// check for error condition. SPARC syscall convention is to
|
||||
// indicate success/failure in reg the carry bit of the ccr
|
||||
// and put the return value itself in the standard return value reg ().
|
||||
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
|
||||
if (return_value.successful()) {
|
||||
// no error, clear XCC.C
|
||||
tc->setIntReg(NumIntArchRegs + 2,
|
||||
tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
|
||||
// tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
|
||||
IntReg val = return_value.value();
|
||||
if (bits(tc->readMiscRegNoEffect(
|
||||
SparcISA::MISCREG_PSTATE), 3, 3)) {
|
||||
if (pstate.am)
|
||||
val = bits(val, 31, 0);
|
||||
}
|
||||
tc->setIntReg(ReturnValueReg, val);
|
||||
} else {
|
||||
// got an error, set XCC.C
|
||||
tc->setIntReg(NumIntArchRegs + 2,
|
||||
tc->readIntReg(NumIntArchRegs + 2) | 0x11);
|
||||
// tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
|
||||
IntReg val = -return_value.value();
|
||||
if (bits(tc->readMiscRegNoEffect(
|
||||
SparcISA::MISCREG_PSTATE), 3, 3)) {
|
||||
if (pstate.am)
|
||||
val = bits(val, 31, 0);
|
||||
}
|
||||
tc->setIntReg(ReturnValueReg, val);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -181,9 +181,9 @@ RemoteGDB::getregs()
|
|||
memset(gdbregs.regs, 0, gdbregs.size);
|
||||
|
||||
PCState pc = context->pcState();
|
||||
PSTATE pstate = context->readMiscReg(MISCREG_PSTATE);
|
||||
|
||||
if (context->readMiscReg(MISCREG_PSTATE) &
|
||||
PSTATE::am) {
|
||||
if (pstate.am) {
|
||||
uint32_t *regs;
|
||||
regs = (uint32_t*)gdbregs.regs;
|
||||
regs[Reg32Pc] = htobe((uint32_t)pc.pc());
|
||||
|
@ -192,7 +192,7 @@ RemoteGDB::getregs()
|
|||
regs[x] = htobe((uint32_t)context->readIntReg(x - RegG0));
|
||||
|
||||
regs[Reg32Y] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1));
|
||||
regs[Reg32Psr] = htobe((uint32_t)context->readMiscReg(MISCREG_PSTATE));
|
||||
regs[Reg32Psr] = htobe((uint32_t)pstate);
|
||||
regs[Reg32Fsr] = htobe((uint32_t)context->readMiscReg(MISCREG_FSR));
|
||||
regs[Reg32Csr] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2));
|
||||
} else {
|
||||
|
@ -206,7 +206,7 @@ RemoteGDB::getregs()
|
|||
gdbregs.regs[RegY] = htobe(context->readIntReg(NumIntArchRegs + 1));
|
||||
gdbregs.regs[RegState] = htobe(
|
||||
context->readMiscReg(MISCREG_CWP) |
|
||||
context->readMiscReg(MISCREG_PSTATE) << 8 |
|
||||
pstate << 8 |
|
||||
context->readMiscReg(MISCREG_ASI) << 24 |
|
||||
context->readIntReg(NumIntArchRegs + 2) << 32);
|
||||
}
|
||||
|
|
|
@ -206,13 +206,18 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
|
|||
break;
|
||||
|
||||
case MISCREG_HPSTATE:
|
||||
{
|
||||
HPSTATE newVal = val;
|
||||
newVal.id = 1;
|
||||
// T1000 spec says impl. dependent val must always be 1
|
||||
setMiscRegNoEffect(miscReg, val | HPSTATE::id);
|
||||
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
|
||||
setMiscRegNoEffect(miscReg, newVal);
|
||||
newVal = hpstate;
|
||||
if (newVal.tlz && tl == 0 && !newVal.hpriv)
|
||||
cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
|
||||
else
|
||||
cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
|
||||
break;
|
||||
}
|
||||
case MISCREG_HTSTATE:
|
||||
setMiscRegNoEffect(miscReg, val);
|
||||
break;
|
||||
|
|
|
@ -58,8 +58,9 @@ uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
|
|||
static inline bool
|
||||
inUserMode(ThreadContext *tc)
|
||||
{
|
||||
return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
|
||||
(tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
|
||||
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
|
||||
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
|
||||
return !(pstate.priv || hpstate.hpriv);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in a new issue