O3: Pack the comm structures a bit better to reduce their size.
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1 changed files with 54 additions and 43 deletions
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@ -121,12 +121,12 @@ template<class Impl>
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struct TimeBufStruct {
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struct TimeBufStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::DynInstPtr DynInstPtr;
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struct decodeComm {
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struct decodeComm {
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uint64_t branchAddr;
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TheISA::PCState nextPC;
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InstSeqNum doneSeqNum;
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DynInstPtr mispredictInst;
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DynInstPtr mispredictInst;
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DynInstPtr squashInst;
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DynInstPtr squashInst;
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InstSeqNum doneSeqNum;
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Addr mispredPC;
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Addr mispredPC;
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TheISA::PCState nextPC;
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uint64_t branchAddr;
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unsigned branchCount;
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unsigned branchCount;
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bool squash;
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bool squash;
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bool predIncorrect;
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bool predIncorrect;
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@ -143,9 +143,7 @@ struct TimeBufStruct {
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struct iewComm {
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struct iewComm {
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// Also eventually include skid buffer space.
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// Also eventually include skid buffer space.
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bool usedIQ;
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unsigned freeIQEntries;
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unsigned freeIQEntries;
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bool usedLSQ;
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unsigned freeLSQEntries;
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unsigned freeLSQEntries;
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unsigned iqCount;
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unsigned iqCount;
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@ -153,57 +151,70 @@ struct TimeBufStruct {
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unsigned dispatched;
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unsigned dispatched;
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unsigned dispatchedToLSQ;
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unsigned dispatchedToLSQ;
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bool usedIQ;
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bool usedLSQ;
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};
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};
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iewComm iewInfo[Impl::MaxThreads];
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iewComm iewInfo[Impl::MaxThreads];
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struct commitComm {
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struct commitComm {
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/////////////////////////////////////////////////////////////////////
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// This code has been re-structured for better packing of variables
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// instead of by stage which is the more logical way to arrange the
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// data.
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// F = Fetch
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// D = Decode
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// I = IEW
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// R = Rename
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// As such each member is annotated with who consumes it
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// e.g. bool variable name // *F,R for Fetch and Rename
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/////////////////////////////////////////////////////////////////////
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/////////////// For Decode, IEW, Rename, Fetch ///////////
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/// The pc of the next instruction to execute. This is the next
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bool squash;
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/// instruction for a branch mispredict, but the same instruction for
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bool robSquashing;
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/// order violation and the like
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TheISA::PCState pc; // *F
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////////// For Fetch & IEW /////////////
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/// Provide fetch the instruction that mispredicted, if this
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// Represents the instruction that has either been retired or
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/// pointer is not-null a misprediction occured
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// squashed. Similar to having a single bus that broadcasts the
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DynInstPtr mispredictInst; // *F
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// retired or squashed sequence number.
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InstSeqNum doneSeqNum;
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////////////// For Rename /////////////////
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/// Instruction that caused the a non-mispredict squash
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// Rename should re-read number of free rob entries
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DynInstPtr squashInst; // *F
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bool usedROB;
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// Notify Rename that the ROB is empty
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bool emptyROB;
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// Tell Rename how many free entries it has in the ROB
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unsigned freeROBEntries;
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/// Hack for now to send back an uncached access to the IEW stage.
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DynInstPtr uncachedLoad; // *I
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///////////// For Fetch //////////////////
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/// Communication specifically to the IQ to tell the IQ that it can
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// Provide fetch the instruction that mispredicted, if this
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/// schedule a non-speculative instruction.
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// pointer is not-null a misprediction occured
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InstSeqNum nonSpecSeqNum; // *I
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DynInstPtr mispredictInst;
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// Was the branch taken or not
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bool branchTaken;
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// The pc of the next instruction to execute. This is the next
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// instruction for a branch mispredict, but the same instruction for
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// order violation and the like
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TheISA::PCState pc;
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// Instruction that caused the a non-mispredict squash
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/// Represents the instruction that has either been retired or
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DynInstPtr squashInst;
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/// squashed. Similar to having a single bus that broadcasts the
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// If an interrupt is pending and fetch should stall
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/// retired or squashed sequence number.
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bool interruptPending;
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InstSeqNum doneSeqNum; // *F, I
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// If the interrupt ended up being cleared before being handled
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bool clearInterrupt;
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//////////// For IEW //////////////////
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/// Tell Rename how many free entries it has in the ROB
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// Communication specifically to the IQ to tell the IQ that it can
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unsigned freeROBEntries; // *R
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// schedule a non-speculative instruction.
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InstSeqNum nonSpecSeqNum;
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// Hack for now to send back an uncached access to the IEW stage.
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bool squash; // *F, D, R, I
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bool uncached;
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bool robSquashing; // *F, D, R, I
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DynInstPtr uncachedLoad;
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/// Rename should re-read number of free rob entries
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bool usedROB; // *R
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/// Notify Rename that the ROB is empty
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bool emptyROB; // *R
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/// Was the branch taken or not
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bool branchTaken; // *F
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/// If an interrupt is pending and fetch should stall
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bool interruptPending; // *F
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/// If the interrupt ended up being cleared before being handled
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bool clearInterrupt; // *F
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/// Hack for now to send back an uncached access to the IEW stage.
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bool uncached; // *I
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};
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};
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