Alpha: Take advantage of new PCState syntax.
This commit is contained in:
parent
f26051eb1a
commit
5a895ab92c
|
@ -221,10 +221,10 @@ def format CondBranch(code) {{
|
||||||
code = '''
|
code = '''
|
||||||
bool cond;
|
bool cond;
|
||||||
%(code)s;
|
%(code)s;
|
||||||
PCState pc = PCS;
|
|
||||||
if (cond)
|
if (cond)
|
||||||
pc.npc(pc.npc() + disp);
|
NPC = NPC + disp;
|
||||||
PCS = pc;
|
else
|
||||||
|
NPC = NPC;
|
||||||
''' % { "code" : code }
|
''' % { "code" : code }
|
||||||
iop = InstObjParams(name, Name, 'Branch', code,
|
iop = InstObjParams(name, Name, 'Branch', code,
|
||||||
('IsDirectControl', 'IsCondControl'))
|
('IsDirectControl', 'IsCondControl'))
|
||||||
|
@ -237,18 +237,17 @@ def format CondBranch(code) {{
|
||||||
let {{
|
let {{
|
||||||
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
|
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
|
||||||
# Declare basic control transfer w/o link (i.e. link reg is R31)
|
# Declare basic control transfer w/o link (i.e. link reg is R31)
|
||||||
readpc_code = 'PCState pc = PCS;'
|
nolink_code = 'NPC = %s;\n' % npc_expr
|
||||||
nolink_code = 'pc.npc(%s);\nPCS = pc' % npc_expr
|
|
||||||
nolink_iop = InstObjParams(name, Name, base_class,
|
nolink_iop = InstObjParams(name, Name, base_class,
|
||||||
readpc_code + nolink_code, flags)
|
nolink_code, flags)
|
||||||
header_output = BasicDeclare.subst(nolink_iop)
|
header_output = BasicDeclare.subst(nolink_iop)
|
||||||
decoder_output = BasicConstructor.subst(nolink_iop)
|
decoder_output = BasicConstructor.subst(nolink_iop)
|
||||||
exec_output = BasicExecute.subst(nolink_iop)
|
exec_output = BasicExecute.subst(nolink_iop)
|
||||||
|
|
||||||
# Generate declaration of '*AndLink' version, append to decls
|
# Generate declaration of '*AndLink' version, append to decls
|
||||||
link_code = 'Ra = pc.npc() & ~3;\n' + nolink_code
|
link_code = 'Ra = NPC & ~3;\n' + nolink_code
|
||||||
link_iop = InstObjParams(name, Name + 'AndLink', base_class,
|
link_iop = InstObjParams(name, Name + 'AndLink', base_class,
|
||||||
readpc_code + link_code, flags)
|
link_code, flags)
|
||||||
header_output += BasicDeclare.subst(link_iop)
|
header_output += BasicDeclare.subst(link_iop)
|
||||||
decoder_output += BasicConstructor.subst(link_iop)
|
decoder_output += BasicConstructor.subst(link_iop)
|
||||||
exec_output += BasicExecute.subst(link_iop)
|
exec_output += BasicExecute.subst(link_iop)
|
||||||
|
@ -263,13 +262,13 @@ def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
|
||||||
def format UncondBranch(*flags) {{
|
def format UncondBranch(*flags) {{
|
||||||
flags += ('IsUncondControl', 'IsDirectControl')
|
flags += ('IsUncondControl', 'IsDirectControl')
|
||||||
(header_output, decoder_output, decode_block, exec_output) = \
|
(header_output, decoder_output, decode_block, exec_output) = \
|
||||||
UncondCtrlBase(name, Name, 'Branch', 'pc.npc() + disp', flags)
|
UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def format Jump(*flags) {{
|
def format Jump(*flags) {{
|
||||||
flags += ('IsUncondControl', 'IsIndirectControl')
|
flags += ('IsUncondControl', 'IsIndirectControl')
|
||||||
(header_output, decoder_output, decode_block, exec_output) = \
|
(header_output, decoder_output, decode_block, exec_output) = \
|
||||||
UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (pc.npc() & 1)', flags)
|
UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -850,10 +850,8 @@ decode OPCODE default Unknown::unknown() {
|
||||||
bool dopal = xc->simPalCheck(palFunc);
|
bool dopal = xc->simPalCheck(palFunc);
|
||||||
|
|
||||||
if (dopal) {
|
if (dopal) {
|
||||||
PCState pc = PCS;
|
xc->setMiscReg(IPR_EXC_ADDR, NPC);
|
||||||
xc->setMiscReg(IPR_EXC_ADDR, pc.npc());
|
NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
|
||||||
pc.npc(xc->readMiscReg(IPR_PAL_BASE) + palOffset);
|
|
||||||
PCS = pc;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
|
@ -1019,14 +1017,13 @@ decode OPCODE default Unknown::unknown() {
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
#endif
|
#endif
|
||||||
0x54: m5panic({{
|
0x54: m5panic({{
|
||||||
panic("M5 panic instruction called at pc=%#x.",
|
panic("M5 panic instruction called at pc = %#x.", PC);
|
||||||
xc->pcState().pc());
|
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
|
#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
|
||||||
0x55: decode RA {
|
0x55: decode RA {
|
||||||
0x00: m5a_old({{
|
0x00: m5a_old({{
|
||||||
panic("Deprecated M5 annotate instruction executed at pc=%#x\n",
|
panic("Deprecated M5 annotate instruction executed "
|
||||||
xc->pcState().pc());
|
"at pc = %#x\n", PC);
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
0x01: m5a_bsm({{
|
0x01: m5a_bsm({{
|
||||||
CPANN(swSmBegin);
|
CPANN(swSmBegin);
|
||||||
|
|
|
@ -186,7 +186,8 @@ def operands {{
|
||||||
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
|
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
|
||||||
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
||||||
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||||
'PCS': ('PCState', 'uq', None, ( None, None, 'IsControl' ), 4),
|
'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
|
||||||
|
'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
|
||||||
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
|
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
|
||||||
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
|
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
|
||||||
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
|
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
|
||||||
|
|
Loading…
Reference in a new issue