From 596cbe19d4591b900acc022ff5a38fc7ee9a5df7 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:17 -0500
Subject: [PATCH] ARM: Make sure undefined unconditional ARM instructions
 decode as such.

---
 src/arch/arm/isa/formats/uncond.isa | 43 ++++++++++++++++-------------
 1 file changed, 24 insertions(+), 19 deletions(-)

diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index 177b67ff2..8aa460081 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -235,34 +235,39 @@ def format ArmUnconditional() {{
                     return new BlxImm(machInst, imm);
                 }
               case 0x2:
-                if (CPNUM == 0xa || CPNUM == 0xb) {
-                    return decodeExtensionRegLoadStore(machInst);
-                }
-                if (bits(op1, 0) == 1) {
-                    if (rn == INTREG_PC) {
-                        if (bits(op1, 4, 3) != 0x0) {
+                if (bits(op1, 4, 0) != 0) {
+                    if (CPNUM == 0xa || CPNUM == 0xb) {
+                        return decodeExtensionRegLoadStore(machInst);
+                    }
+                    if (bits(op1, 0) == 1) {
+                        if (rn == INTREG_PC) {
+                            if (bits(op1, 4, 3) != 0x0) {
+                                return new WarnUnimplemented(
+                                        "ldc, ldc2 (literal)", machInst);
+                            }
+                        } else {
+                            if (op1 == 0xC3 || op1 == 0xC7) {
+                                return new WarnUnimplemented(
+                                        "ldc, ldc2 (immediate)", machInst);
+                            }
+                        }
+                        if (op1 == 0xC5) {
                             return new WarnUnimplemented(
-                                    "ldc, ldc2 (literal)", machInst);
+                                    "mrrc, mrrc2", machInst);
                         }
                     } else {
-                        if (op1 == 0xC3 || op1 == 0xC7) {
+                        if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
                             return new WarnUnimplemented(
-                                    "ldc, ldc2 (immediate)", machInst);
+                                    "stc, stc2", machInst);
+                        } else if (op1 == 0xC4) {
+                            return new WarnUnimplemented(
+                                    "mcrr, mcrrc", machInst);
                         }
                     }
-                    if (op1 == 0xC5) {
-                        return new WarnUnimplemented("mrrc, mrrc2", machInst);
-                    }
-                } else {
-                    if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
-                        return new WarnUnimplemented("stc, stc2", machInst);
-                    } else if (op1 == 0xC4) {
-                        return new WarnUnimplemented("mcrr, mcrrc", machInst);
-                    }
                 }
                 break;
               case 0x3:
-                {
+                if (bits(op1, 4) == 0) {
                     if (CPNUM == 0xa || CPNUM == 0xb) {
                         return decodeShortFpTransfer(machInst);
                     } else if (CPNUM == 0xf) {