Make the IO bridge accept address headed to all the local APICs.
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559b43a372
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5917fb3292
1 changed files with 4 additions and 3 deletions
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@ -354,7 +354,7 @@ def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port
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return IO_address_space_base + port
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def connectX86ClassicSystem(x86_sys):
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def connectX86ClassicSystem(x86_sys, numCPUs):
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# Constants similar to x86_traits.hh
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# Constants similar to x86_traits.hh
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IO_address_space_base = 0x8000000000000000
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IO_address_space_base = 0x8000000000000000
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pci_config_address_space_base = 0xc000000000000000
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pci_config_address_space_base = 0xc000000000000000
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@ -390,7 +390,8 @@ def connectX86ClassicSystem(x86_sys):
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x86_sys.apicbridge.master = x86_sys.membus.slave
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x86_sys.apicbridge.master = x86_sys.membus.slave
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x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
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x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
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interrupts_address_space_base +
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interrupts_address_space_base +
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APIC_range_size - 1)]
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numCPUs * APIC_range_size
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- 1)]
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# connect the io bus
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# connect the io bus
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x86_sys.pc.attachIO(x86_sys.iobus)
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x86_sys.pc.attachIO(x86_sys.iobus)
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@ -435,7 +436,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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# dma controllers
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# dma controllers
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self._dma_devices = [self.pc.south_bridge.ide]
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self._dma_devices = [self.pc.south_bridge.ide]
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else:
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else:
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connectX86ClassicSystem(self)
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connectX86ClassicSystem(self, numCPUs)
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self.intrctrl = IntrControl()
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self.intrctrl = IntrControl()
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