trying to get ISA to parse correctly ...
arch/mips/isa/formats/unimp.isa: holds unimplemented formats arch/mips/isa/formats/unknown.isa: holds unknown formats --HG-- extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975
This commit is contained in:
parent
9f584bcc6f
commit
5830200d78
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@ -9,7 +9,7 @@
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//
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//
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//@todo: Distinguish "unknown/future" use insts from "reserved"
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//@todo: Distinguish "unknown/future" use insts from "reserved"
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// ones
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// ones
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decode OPCODE_HI default FailUnimpl::unknown() {
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decode OPCODE_HI default Unknown::unknown() {
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// Derived From ... Table A-2 MIPS32 ISA Manual
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// Derived From ... Table A-2 MIPS32 ISA Manual
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0x0: decode OPCODE_LO default FailUnimpl::reserved(){
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0x0: decode OPCODE_LO default FailUnimpl::reserved(){
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@ -66,10 +66,11 @@ decode OPCODE_HI default FailUnimpl::unknown() {
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0x3: movn({{ if (Rt != 0) Rd = Rs; }});
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0x3: movn({{ if (Rt != 0) Rd = Rs; }});
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}
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}
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format WarnUnimpl {
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format WarnUnimpl {
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0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
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0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
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0x5: break({{ }});
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0x5: break();
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0x7: sync({{ }});
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0x7: sync();
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}
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}
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}
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}
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@ -80,14 +81,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
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0x2: mflo({{ Rd = xc->miscRegs.lo; }});
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0x2: mflo({{ Rd = xc->miscRegs.lo; }});
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0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
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0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
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}
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}
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};
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}
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0x3: decode FUNCTION_LO {
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0x3: decode FUNCTION_LO {
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format IntOp {
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format IntOp {
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0x0: mult({{
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0x0: mult({{
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INT64 temp1 = Rs.sw * Rt.sw;
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INT64 temp1 = Rs.sw * Rt.sw;
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xc->miscRegs.hi->temp1<63:32>;
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xc->miscRegs.hi->temp1<63:32>;
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xc->miscRegs.lo->temp1<31:0>
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xc->miscRegs.lo->temp1<31:0>;
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}});
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}});
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0x1: multu({{
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0x1: multu({{
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@ -1,22 +1,29 @@
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//Include the basic format
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//Include the basic format
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//Templates from this format are used later
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//Templates from this format are used later
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##include "m5/arch/mips/isa_desc/formats/basic.format"
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##include "m5/arch/mips/isa/formats/basic.isa"
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//Include the integerOp and integerOpCc format
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//Include the integerOp and integerOpCc format
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##include "m5/arch/mips/isa_desc/formats/integerop.format"
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##include "m5/arch/mips/isa/formats/int.isa"
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//Include the floatOp format
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//Include the floatOp format
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##include "m5/arch/mips/isa_desc/formats/floatop.format"
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##include "m5/arch/mips/isa/formats/fp.isa"
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//Include the mem format
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//Include the mem format
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##include "m5/arch/mips/isa_desc/formats/mem.format"
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##include "m5/arch/mips/isa/formats/mem.isa"
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//Include the trap format
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//Include the trap format
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##include "m5/arch/mips/isa_desc/formats/trap.format"
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##include "m5/arch/mips/isa/formats/trap.isa"
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//Include the branch format
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//Include the branch format
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##include "m5/arch/mips/isa_desc/formats/branch.format"
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##include "m5/arch/mips/isa/formats/branch.isa"
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//Include the noop format
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//Include the noop format
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##include "m5/arch/mips/isa_desc/formats/noop.format"
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##include "m5/arch/mips/isa/formats/noop.isa"
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//Include the noop format
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##include "m5/arch/mips/isa/formats/unimp.isa"
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//Include the noop format
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##include "m5/arch/mips/isa/formats/unknown.isa"
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@ -56,7 +56,7 @@ def template BasicDecodeWithMnemonic {{
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}};
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}};
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// The most basic instruction format... used only for a few misc. insts
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// The most basic instruction format... used only for a few misc. insts
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def format BasicOperate(code, *flags) {{
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def format BasicOp(code, *flags) {{
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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@ -1,57 +1,212 @@
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////////////////////////////////////////////////////////////////////
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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//
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// Branch instructions
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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output header {{
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/**
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* Base class for integer operations.
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/**
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*/
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* Base class for instructions whose disassembly is not purely a
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class Branch : public MipsStaticInst
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* function of the machine instruction (i.e., it depends on the
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* PC). This class overrides the disassemble() method to check
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* the PC and symbol table values before re-using a cached
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* disassembly string. This is necessary for branches and jumps,
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public AlphaStaticInst
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, MachInst _machInst,
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OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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{
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protected:
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}
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/// Constructor
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const std::string &
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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disassemble(Addr pc, const SymbolTable *symtab) const;
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{
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};
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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/**
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};
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* Base class for branches (PC-relative control transfers),
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* conditional or unconditional.
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*/
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class Branch : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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/// Constructor.
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(BRDISP << 2)
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{
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}
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Addr branchTarget(Addr branchPC) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for jumps (register-indirect control transfers). In
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* the Alpha ISA, these are always unconditional.
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*/
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class Jump : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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public:
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/// Constructor
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Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(BRDISP)
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{
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}
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Addr branchTarget(ExecContext *xc) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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}};
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output decoder {{
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output decoder {{
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std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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Addr
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Branch::branchTarget(Addr branchPC) const
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{
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return branchPC + 4 + disp;
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}
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Addr
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Jump::branchTarget(ExecContext *xc) const
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{
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Addr NPC = xc->readPC() + 4;
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uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
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return (Rb & ~3) | (NPC & 1);
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}
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const std::string &
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PCDependentDisassembly::disassemble(Addr pc,
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const SymbolTable *symtab) const
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{
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if (!cachedDisassembly ||
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pc != cachedPC || symtab != cachedSymtab)
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{
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{
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return "Disassembly of integer instruction\n";
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if (cachedDisassembly)
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delete cachedDisassembly;
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cachedDisassembly =
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new std::string(generateDisassembly(pc, symtab));
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cachedPC = pc;
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cachedSymtab = symtab;
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}
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}
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return *cachedDisassembly;
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}
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std::string
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Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// There's only one register arg (RA), but it could be
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// either a source (the condition for conditional
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// branches) or a destination (the link reg for
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// unconditional branches)
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ",";
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}
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else if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numSrcRegs == 0 && _numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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Addr target = pc + 4 + disp;
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std::string str;
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if (symtab && symtab->findSymbol(target, str))
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ss << str;
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else
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ccprintf(ss, "0x%x", target);
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return ss.str();
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}
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std::string
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Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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ccprintf(ss, "(r%d)", RB);
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return ss.str();
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}
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}};
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}};
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def template BranchExecute {{
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def template JumpOrBranchDecode {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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return (RA == 31)
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{
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? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
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//Attempt to execute the instruction
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: (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
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try
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{
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checkPriv;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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}
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//If we have an exception for some reason,
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//deal with it
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catch(MipsException except)
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{
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//Deal with exception
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return No_Fault;
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}
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//Write the resulting state to the execution context
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%(op_wb)s;
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return No_Fault;
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}
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}};
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}};
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def format CondBranch(code) {{
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def format CondBranch(code) {{
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@ -64,3 +219,41 @@ def format CondBranch(code) {{
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exec_output = BasicExecute.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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}};
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let {{
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def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
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# Declare basic control transfer w/o link (i.e. link reg is R31)
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nolink_code = 'NPC = %s;\n' % npc_expr
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nolink_iop = InstObjParams(name, Name, base_class,
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CodeBlock(nolink_code), flags)
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header_output = BasicDeclare.subst(nolink_iop)
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decoder_output = BasicConstructor.subst(nolink_iop)
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exec_output = BasicExecute.subst(nolink_iop)
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# Generate declaration of '*AndLink' version, append to decls
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link_code = 'Ra = NPC & ~3;\n' + nolink_code
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link_iop = InstObjParams(name, Name + 'AndLink', base_class,
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CodeBlock(link_code), flags)
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header_output += BasicDeclare.subst(link_iop)
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decoder_output += BasicConstructor.subst(link_iop)
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exec_output += BasicExecute.subst(link_iop)
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# need to use link_iop for the decode template since it is expecting
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# the shorter version of class_name (w/o "AndLink")
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return (header_output, decoder_output,
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JumpOrBranchDecode.subst(nolink_iop), exec_output)
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}};
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def format UncondBranch(*flags) {{
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flags += ('IsUncondControl', 'IsDirectControl')
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(header_output, decoder_output, decode_block, exec_output) = \
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UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
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}};
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def format Jump(*flags) {{
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flags += ('IsUncondControl', 'IsIndirectControl')
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(header_output, decoder_output, decode_block, exec_output) = \
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UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
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|
}};
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|
|
@ -53,9 +53,9 @@ def format IntOp(code, *opt_flags) {{
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orig_code = code
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orig_code = code
|
||||||
cblk = CodeBlock(code)
|
cblk = CodeBlock(code)
|
||||||
|
|
||||||
//Figure out if we are creating a IntImmOp or a IntOp
|
# Figure out if we are creating a IntImmOp or a IntOp
|
||||||
strlen = len(name)
|
strlen = len(name)
|
||||||
if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu'))
|
if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
|
||||||
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
|
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
|
||||||
else:
|
else:
|
||||||
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
|
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
|
||||||
|
|
165
arch/mips/isa/formats/unimp.isa
Normal file
165
arch/mips/isa/formats/unimp.isa
Normal file
|
@ -0,0 +1,165 @@
|
||||||
|
// -*- mode:c++ -*-
|
||||||
|
|
||||||
|
// Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are
|
||||||
|
// met: redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer;
|
||||||
|
// redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in the
|
||||||
|
// documentation and/or other materials provided with the distribution;
|
||||||
|
// neither the name of the copyright holders nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived from
|
||||||
|
// this software without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
output header {{
|
||||||
|
/**
|
||||||
|
* Static instruction class for unimplemented instructions that
|
||||||
|
* cause simulator termination. Note that these are recognized
|
||||||
|
* (legal) instructions that the simulator does not support; the
|
||||||
|
* 'Unknown' class is used for unrecognized/illegal instructions.
|
||||||
|
* This is a leaf class.
|
||||||
|
*/
|
||||||
|
class FailUnimplemented : public AlphaStaticInst
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
/// Constructor
|
||||||
|
FailUnimplemented(const char *_mnemonic, MachInst _machInst)
|
||||||
|
: AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
|
||||||
|
{
|
||||||
|
// don't call execute() (which panics) if we're on a
|
||||||
|
// speculative path
|
||||||
|
flags[IsNonSpeculative] = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
%(BasicExecDeclare)s
|
||||||
|
|
||||||
|
std::string
|
||||||
|
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Base class for unimplemented instructions that cause a warning
|
||||||
|
* to be printed (but do not terminate simulation). This
|
||||||
|
* implementation is a little screwy in that it will print a
|
||||||
|
* warning for each instance of a particular unimplemented machine
|
||||||
|
* instruction, not just for each unimplemented opcode. Should
|
||||||
|
* probably make the 'warned' flag a static member of the derived
|
||||||
|
* class.
|
||||||
|
*/
|
||||||
|
class WarnUnimplemented : public AlphaStaticInst
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
/// Have we warned on this instruction yet?
|
||||||
|
mutable bool warned;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/// Constructor
|
||||||
|
WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
|
||||||
|
: AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
|
||||||
|
{
|
||||||
|
// don't call execute() (which panics) if we're on a
|
||||||
|
// speculative path
|
||||||
|
flags[IsNonSpeculative] = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
%(BasicExecDeclare)s
|
||||||
|
|
||||||
|
std::string
|
||||||
|
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||||
|
};
|
||||||
|
}};
|
||||||
|
|
||||||
|
output decoder {{
|
||||||
|
std::string
|
||||||
|
FailUnimplemented::generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const
|
||||||
|
{
|
||||||
|
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||||
|
}
|
||||||
|
|
||||||
|
std::string
|
||||||
|
WarnUnimplemented::generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const
|
||||||
|
{
|
||||||
|
#ifdef SS_COMPATIBLE_DISASSEMBLY
|
||||||
|
return csprintf("%-10s", mnemonic);
|
||||||
|
#else
|
||||||
|
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}};
|
||||||
|
|
||||||
|
output exec {{
|
||||||
|
Fault
|
||||||
|
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
|
{
|
||||||
|
panic("attempt to execute unimplemented instruction '%s' "
|
||||||
|
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
|
||||||
|
return Unimplemented_Opcode_Fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault
|
||||||
|
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
|
{
|
||||||
|
if (!warned) {
|
||||||
|
warn("instruction '%s' unimplemented\n", mnemonic);
|
||||||
|
warned = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return No_Fault;
|
||||||
|
}
|
||||||
|
}};
|
||||||
|
|
||||||
|
|
||||||
|
def format FailUnimpl() {{
|
||||||
|
iop = InstObjParams(name, 'FailUnimplemented')
|
||||||
|
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||||
|
}};
|
||||||
|
|
||||||
|
def format WarnUnimpl() {{
|
||||||
|
iop = InstObjParams(name, 'WarnUnimplemented')
|
||||||
|
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||||
|
}};
|
||||||
|
|
||||||
|
output header {{
|
||||||
|
/**
|
||||||
|
* Static instruction class for unknown (illegal) instructions.
|
||||||
|
* These cause simulator termination if they are executed in a
|
||||||
|
* non-speculative mode. This is a leaf class.
|
||||||
|
*/
|
||||||
|
class Unknown : public AlphaStaticInst
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
/// Constructor
|
||||||
|
Unknown(MachInst _machInst)
|
||||||
|
: AlphaStaticInst("unknown", _machInst, No_OpClass)
|
||||||
|
{
|
||||||
|
// don't call execute() (which panics) if we're on a
|
||||||
|
// speculative path
|
||||||
|
flags[IsNonSpeculative] = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
%(BasicExecDeclare)s
|
||||||
|
|
||||||
|
std::string
|
||||||
|
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||||
|
};
|
||||||
|
}};
|
||||||
|
|
52
arch/mips/isa/formats/unknown.isa
Normal file
52
arch/mips/isa/formats/unknown.isa
Normal file
|
@ -0,0 +1,52 @@
|
||||||
|
// -*- mode:c++ -*-
|
||||||
|
|
||||||
|
// Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are
|
||||||
|
// met: redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer;
|
||||||
|
// redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in the
|
||||||
|
// documentation and/or other materials provided with the distribution;
|
||||||
|
// neither the name of the copyright holders nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived from
|
||||||
|
// this software without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
output decoder {{
|
||||||
|
std::string
|
||||||
|
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||||
|
{
|
||||||
|
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
|
||||||
|
"unknown", machInst, OPCODE);
|
||||||
|
}
|
||||||
|
}};
|
||||||
|
|
||||||
|
output exec {{
|
||||||
|
Fault
|
||||||
|
Unknown::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
|
{
|
||||||
|
panic("attempt to execute unknown instruction "
|
||||||
|
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
|
||||||
|
return Unimplemented_Opcode_Fault;
|
||||||
|
}
|
||||||
|
}};
|
||||||
|
|
||||||
|
def format Unknown() {{
|
||||||
|
decode_block = 'return new Unknown(machInst);\n'
|
||||||
|
}};
|
||||||
|
|
|
@ -26,7 +26,7 @@
|
||||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
##include "m5/arch/sparc/isa_desc/includes.h"
|
##include "m5/arch/mips/isa/includes.isa"
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
||||||
//
|
//
|
||||||
|
@ -37,16 +37,16 @@
|
||||||
namespace MipsISA;
|
namespace MipsISA;
|
||||||
|
|
||||||
//Include the bitfield definitions
|
//Include the bitfield definitions
|
||||||
##include "m5/arch/mips/isa_desc/bitfields.h"
|
##include "m5/arch/mips/isa/bitfields.isa"
|
||||||
|
|
||||||
//Include the operand_types and operand definitions
|
//Include the operand_types and operand definitions
|
||||||
##include "m5/arch/mips/isa_desc/operands.h"
|
##include "m5/arch/mips/isa/operands.isa"
|
||||||
|
|
||||||
//Include the base class for mips instructions, and some support code
|
//Include the base class for mips instructions, and some support code
|
||||||
##include "m5/arch/mips/isa_desc/base.h"
|
##include "m5/arch/mips/isa/base.isa"
|
||||||
|
|
||||||
//Include the definitions for the instruction formats
|
//Include the definitions for the instruction formats
|
||||||
##include "m5/arch/mips/isa_desc/formats.h"
|
##include "m5/arch/mips/isa/formats.isa"
|
||||||
|
|
||||||
//Include the decoder definition
|
//Include the decoder definition
|
||||||
##include "m5/arch/mips/isa_desc/decoder.h"
|
##include "m5/arch/mips/isa/decoder.isa"
|
||||||
|
|
Loading…
Reference in a new issue